1 /*- 2 * Copyright (c) 2011 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/lock.h> 33 #include <sys/mutex.h> 34 #include <sys/smp.h> 35 36 #include <vm/vm.h> 37 #include <vm/vm_kern.h> 38 #include <vm/vm_extern.h> 39 40 #include <machine/smp.h> 41 #include <machine/fdt.h> 42 #include <machine/armreg.h> 43 44 #include <arm/mv/mvwin.h> 45 46 #define MV_AXP_CPU_DIVCLK_BASE (MV_BASE + 0x18700) 47 #define CPU_DIVCLK_CTRL0 0x00 48 #define CPU_DIVCLK_CTRL2_RATIO_FULL0 0x08 49 #define CPU_DIVCLK_CTRL2_RATIO_FULL1 0x0c 50 #define CPU_DIVCLK_MASK(x) (~(0xff << (8 * (x)))) 51 52 #define CPU_PMU(x) (MV_BASE + 0x22100 + (0x100 * (x))) 53 #define CPU_PMU_BOOT 0x24 54 55 #define MP (MV_BASE + 0x20800) 56 #define MP_SW_RESET(x) ((x) * 8) 57 58 #define CPU_RESUME_CONTROL (0x20988) 59 60 void armadaxp_init_coher_fabric(void); 61 int platform_get_ncpus(void); 62 63 /* Coherency Fabric registers */ 64 static uint32_t 65 read_cpu_clkdiv(uint32_t reg) 66 { 67 68 return (bus_space_read_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg)); 69 } 70 71 static void 72 write_cpu_clkdiv(uint32_t reg, uint32_t val) 73 { 74 75 bus_space_write_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg, val); 76 } 77 78 void 79 platform_mp_setmaxid(void) 80 { 81 82 mp_maxid = 3; 83 } 84 85 int 86 platform_mp_probe(void) 87 { 88 89 mp_ncpus = platform_get_ncpus(); 90 91 return (mp_ncpus > 1); 92 } 93 94 void 95 platform_mp_init_secondary(void) 96 { 97 } 98 99 void mpentry(void); 100 void mptramp(void); 101 102 103 104 void 105 platform_mp_start_ap(void) 106 { 107 uint32_t reg, *src, *dst, cpu_num, div_val, cputype; 108 vm_offset_t smp_boot; 109 /* 110 * Initialization procedure depends on core revision, 111 * in this step CHIP ID is checked to choose proper procedure 112 */ 113 cputype = cpufunc_id(); 114 cputype &= CPU_ID_CPU_MASK; 115 116 smp_boot = kva_alloc(PAGE_SIZE); 117 pmap_kenter_nocache(smp_boot, 0xffff0000); 118 dst = (uint32_t *) smp_boot; 119 120 for (src = (uint32_t *)mptramp; src < (uint32_t *)mpentry; 121 src++, dst++) { 122 *dst = *src; 123 } 124 kva_free(smp_boot, PAGE_SIZE); 125 126 if (cputype == CPU_ID_MV88SV584X_V7) { 127 /* Core rev A0 */ 128 div_val = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); 129 div_val &= 0x3f; 130 131 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) { 132 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); 133 reg &= CPU_DIVCLK_MASK(cpu_num); 134 reg |= div_val << (cpu_num * 8); 135 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg); 136 } 137 } else { 138 /* Core rev Z1 */ 139 div_val = 0x01; 140 141 if (mp_ncpus > 1) { 142 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0); 143 reg &= CPU_DIVCLK_MASK(3); 144 reg |= div_val << 24; 145 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0, reg); 146 } 147 148 for (cpu_num = 2; cpu_num < mp_ncpus; cpu_num++ ) { 149 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); 150 reg &= CPU_DIVCLK_MASK(cpu_num); 151 reg |= div_val << (cpu_num * 8); 152 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg); 153 } 154 } 155 156 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0); 157 reg |= ((0x1 << (mp_ncpus - 1)) - 1) << 21; 158 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); 159 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0); 160 reg |= 0x01000000; 161 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); 162 163 DELAY(100); 164 reg &= ~(0xf << 21); 165 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); 166 DELAY(100); 167 168 bus_space_write_4(fdtbus_bs_tag, MV_BASE, CPU_RESUME_CONTROL, 0); 169 170 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) 171 bus_space_write_4(fdtbus_bs_tag, CPU_PMU(cpu_num), CPU_PMU_BOOT, 172 pmap_kextract((vm_offset_t)mpentry)); 173 174 cpu_idcache_wbinv_all(); 175 176 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) 177 bus_space_write_4(fdtbus_bs_tag, MP, MP_SW_RESET(cpu_num), 0); 178 179 /* XXX: Temporary workaround for hangup after releasing AP's */ 180 wmb(); 181 DELAY(10); 182 183 armadaxp_init_coher_fabric(); 184 } 185 186 void 187 platform_ipi_send(cpuset_t cpus, u_int ipi) 188 { 189 190 pic_ipi_send(cpus, ipi); 191 } 192