1 /*- 2 * Copyright (c) 2011 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/lock.h> 33 #include <sys/mutex.h> 34 #include <sys/smp.h> 35 36 #include <vm/vm.h> 37 #include <vm/vm_kern.h> 38 #include <vm/vm_extern.h> 39 #include <vm/pmap.h> 40 41 #include <dev/fdt/fdt_common.h> 42 43 #include <machine/smp.h> 44 #include <machine/fdt.h> 45 #include <machine/armreg.h> 46 47 #include <arm/mv/mvwin.h> 48 49 #define MV_AXP_CPU_DIVCLK_BASE (MV_BASE + 0x18700) 50 #define CPU_DIVCLK_CTRL0 0x00 51 #define CPU_DIVCLK_CTRL2_RATIO_FULL0 0x08 52 #define CPU_DIVCLK_CTRL2_RATIO_FULL1 0x0c 53 #define CPU_DIVCLK_MASK(x) (~(0xff << (8 * (x)))) 54 55 #define CPU_PMU(x) (MV_BASE + 0x22100 + (0x100 * (x))) 56 #define CPU_PMU_BOOT 0x24 57 58 #define MP (MV_BASE + 0x20800) 59 #define MP_SW_RESET(x) ((x) * 8) 60 61 #define CPU_RESUME_CONTROL (0x20988) 62 63 void armadaxp_init_coher_fabric(void); 64 int platform_get_ncpus(void); 65 66 /* Coherency Fabric registers */ 67 static uint32_t 68 read_cpu_clkdiv(uint32_t reg) 69 { 70 71 return (bus_space_read_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg)); 72 } 73 74 static void 75 write_cpu_clkdiv(uint32_t reg, uint32_t val) 76 { 77 78 bus_space_write_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg, val); 79 } 80 81 void 82 platform_mp_setmaxid(void) 83 { 84 85 mp_maxid = 3; 86 } 87 88 int 89 platform_mp_probe(void) 90 { 91 92 mp_ncpus = platform_get_ncpus(); 93 94 return (mp_ncpus > 1); 95 } 96 97 void 98 platform_mp_init_secondary(void) 99 { 100 } 101 102 void mptramp(void); 103 void mptramp_end(void); 104 extern vm_offset_t mptramp_pmu_boot; 105 106 void 107 platform_mp_start_ap(void) 108 { 109 uint32_t reg, *src, *dst, cpu_num, div_val, cputype; 110 vm_offset_t pmu_boot_off; 111 /* 112 * Initialization procedure depends on core revision, 113 * in this step CHIP ID is checked to choose proper procedure 114 */ 115 cputype = cpufunc_id(); 116 cputype &= CPU_ID_CPU_MASK; 117 118 /* 119 * Set the PA of CPU0 Boot Address Redirect register used in 120 * mptramp according to the actual SoC registers' base address. 121 */ 122 pmu_boot_off = (CPU_PMU(0) - MV_BASE) + CPU_PMU_BOOT; 123 mptramp_pmu_boot = fdt_immr_pa + pmu_boot_off; 124 dst = pmap_mapdev(0xffff0000, PAGE_SIZE); 125 for (src = (uint32_t *)mptramp; src < (uint32_t *)mptramp_end; 126 src++, dst++) { 127 *dst = *src; 128 } 129 pmap_unmapdev((vm_offset_t)dst, PAGE_SIZE); 130 if (cputype == CPU_ID_MV88SV584X_V7) { 131 /* Core rev A0 */ 132 div_val = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); 133 div_val &= 0x3f; 134 135 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) { 136 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); 137 reg &= CPU_DIVCLK_MASK(cpu_num); 138 reg |= div_val << (cpu_num * 8); 139 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg); 140 } 141 } else { 142 /* Core rev Z1 */ 143 div_val = 0x01; 144 145 if (mp_ncpus > 1) { 146 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0); 147 reg &= CPU_DIVCLK_MASK(3); 148 reg |= div_val << 24; 149 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0, reg); 150 } 151 152 for (cpu_num = 2; cpu_num < mp_ncpus; cpu_num++ ) { 153 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); 154 reg &= CPU_DIVCLK_MASK(cpu_num); 155 reg |= div_val << (cpu_num * 8); 156 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg); 157 } 158 } 159 160 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0); 161 reg |= ((0x1 << (mp_ncpus - 1)) - 1) << 21; 162 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); 163 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0); 164 reg |= 0x01000000; 165 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); 166 167 DELAY(100); 168 reg &= ~(0xf << 21); 169 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); 170 DELAY(100); 171 172 bus_space_write_4(fdtbus_bs_tag, MV_BASE, CPU_RESUME_CONTROL, 0); 173 174 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) 175 bus_space_write_4(fdtbus_bs_tag, CPU_PMU(cpu_num), CPU_PMU_BOOT, 176 pmap_kextract((vm_offset_t)mpentry)); 177 178 cpu_idcache_wbinv_all(); 179 180 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) 181 bus_space_write_4(fdtbus_bs_tag, MP, MP_SW_RESET(cpu_num), 0); 182 183 /* XXX: Temporary workaround for hangup after releasing AP's */ 184 wmb(); 185 DELAY(10); 186 187 armadaxp_init_coher_fabric(); 188 } 189 190 void 191 platform_ipi_send(cpuset_t cpus, u_int ipi) 192 { 193 194 pic_ipi_send(cpus, ipi); 195 } 196