1 /*- 2 * Copyright (c) 2011 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/lock.h> 33 #include <sys/mutex.h> 34 #include <sys/smp.h> 35 36 #include <vm/vm.h> 37 #include <vm/vm_kern.h> 38 #include <vm/vm_extern.h> 39 #include <vm/pmap.h> 40 41 #include <dev/fdt/fdt_common.h> 42 43 #include <machine/cpu.h> 44 #include <machine/smp.h> 45 #include <machine/fdt.h> 46 #include <machine/armreg.h> 47 48 #include <arm/mv/mvwin.h> 49 50 #define MV_AXP_CPU_DIVCLK_BASE (MV_BASE + 0x18700) 51 #define CPU_DIVCLK_CTRL0 0x00 52 #define CPU_DIVCLK_CTRL2_RATIO_FULL0 0x08 53 #define CPU_DIVCLK_CTRL2_RATIO_FULL1 0x0c 54 #define CPU_DIVCLK_MASK(x) (~(0xff << (8 * (x)))) 55 56 #define CPU_PMU(x) (MV_BASE + 0x22100 + (0x100 * (x))) 57 #define CPU_PMU_BOOT 0x24 58 59 #define MP (MV_BASE + 0x20800) 60 #define MP_SW_RESET(x) ((x) * 8) 61 62 #define CPU_RESUME_CONTROL (0x20988) 63 64 void armadaxp_init_coher_fabric(void); 65 int platform_get_ncpus(void); 66 67 /* Coherency Fabric registers */ 68 static uint32_t 69 read_cpu_clkdiv(uint32_t reg) 70 { 71 72 return (bus_space_read_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg)); 73 } 74 75 static void 76 write_cpu_clkdiv(uint32_t reg, uint32_t val) 77 { 78 79 bus_space_write_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg, val); 80 } 81 82 void 83 platform_mp_setmaxid(void) 84 { 85 86 mp_ncpus = platform_get_ncpus(); 87 mp_maxid = mp_ncpus - 1; 88 } 89 90 void mptramp(void); 91 void mptramp_end(void); 92 extern vm_offset_t mptramp_pmu_boot; 93 94 void 95 platform_mp_start_ap(void) 96 { 97 uint32_t reg, *src, *dst, cpu_num, div_val, cputype; 98 vm_offset_t pmu_boot_off; 99 /* 100 * Initialization procedure depends on core revision, 101 * in this step CHIP ID is checked to choose proper procedure 102 */ 103 cputype = cpu_ident(); 104 cputype &= CPU_ID_CPU_MASK; 105 106 /* 107 * Set the PA of CPU0 Boot Address Redirect register used in 108 * mptramp according to the actual SoC registers' base address. 109 */ 110 pmu_boot_off = (CPU_PMU(0) - MV_BASE) + CPU_PMU_BOOT; 111 mptramp_pmu_boot = fdt_immr_pa + pmu_boot_off; 112 dst = pmap_mapdev(0xffff0000, PAGE_SIZE); 113 for (src = (uint32_t *)mptramp; src < (uint32_t *)mptramp_end; 114 src++, dst++) { 115 *dst = *src; 116 } 117 pmap_unmapdev((vm_offset_t)dst, PAGE_SIZE); 118 if (cputype == CPU_ID_MV88SV584X_V7) { 119 /* Core rev A0 */ 120 div_val = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); 121 div_val &= 0x3f; 122 123 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) { 124 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); 125 reg &= CPU_DIVCLK_MASK(cpu_num); 126 reg |= div_val << (cpu_num * 8); 127 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg); 128 } 129 } else { 130 /* Core rev Z1 */ 131 div_val = 0x01; 132 133 if (mp_ncpus > 1) { 134 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0); 135 reg &= CPU_DIVCLK_MASK(3); 136 reg |= div_val << 24; 137 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0, reg); 138 } 139 140 for (cpu_num = 2; cpu_num < mp_ncpus; cpu_num++ ) { 141 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); 142 reg &= CPU_DIVCLK_MASK(cpu_num); 143 reg |= div_val << (cpu_num * 8); 144 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg); 145 } 146 } 147 148 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0); 149 reg |= ((0x1 << (mp_ncpus - 1)) - 1) << 21; 150 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); 151 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0); 152 reg |= 0x01000000; 153 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); 154 155 DELAY(100); 156 reg &= ~(0xf << 21); 157 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); 158 DELAY(100); 159 160 bus_space_write_4(fdtbus_bs_tag, MV_BASE, CPU_RESUME_CONTROL, 0); 161 162 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) 163 bus_space_write_4(fdtbus_bs_tag, CPU_PMU(cpu_num), CPU_PMU_BOOT, 164 pmap_kextract((vm_offset_t)mpentry)); 165 166 dcache_wbinv_poc_all(); 167 168 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) 169 bus_space_write_4(fdtbus_bs_tag, MP, MP_SW_RESET(cpu_num), 0); 170 171 /* XXX: Temporary workaround for hangup after releasing AP's */ 172 wmb(); 173 DELAY(10); 174 175 armadaxp_init_coher_fabric(); 176 } 177