1 /*- 2 * Copyright (c) 2011 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 #include <sys/lock.h> 33 #include <sys/mutex.h> 34 #include <sys/smp.h> 35 36 #include <vm/vm.h> 37 #include <vm/vm_kern.h> 38 #include <vm/vm_extern.h> 39 #include <vm/pmap.h> 40 41 #include <dev/fdt/fdt_common.h> 42 43 #include <machine/smp.h> 44 #include <machine/fdt.h> 45 #include <machine/armreg.h> 46 47 #include <arm/mv/mvwin.h> 48 49 #define MV_AXP_CPU_DIVCLK_BASE (MV_BASE + 0x18700) 50 #define CPU_DIVCLK_CTRL0 0x00 51 #define CPU_DIVCLK_CTRL2_RATIO_FULL0 0x08 52 #define CPU_DIVCLK_CTRL2_RATIO_FULL1 0x0c 53 #define CPU_DIVCLK_MASK(x) (~(0xff << (8 * (x)))) 54 55 #define CPU_PMU(x) (MV_BASE + 0x22100 + (0x100 * (x))) 56 #define CPU_PMU_BOOT 0x24 57 58 #define MP (MV_BASE + 0x20800) 59 #define MP_SW_RESET(x) ((x) * 8) 60 61 #define CPU_RESUME_CONTROL (0x20988) 62 63 void armadaxp_init_coher_fabric(void); 64 int platform_get_ncpus(void); 65 66 /* Coherency Fabric registers */ 67 static uint32_t 68 read_cpu_clkdiv(uint32_t reg) 69 { 70 71 return (bus_space_read_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg)); 72 } 73 74 static void 75 write_cpu_clkdiv(uint32_t reg, uint32_t val) 76 { 77 78 bus_space_write_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg, val); 79 } 80 81 void 82 platform_mp_setmaxid(void) 83 { 84 85 mp_ncpus = platform_get_ncpus(); 86 mp_maxid = mp_ncpus - 1; 87 } 88 89 int 90 platform_mp_probe(void) 91 { 92 93 return (mp_ncpus > 1); 94 } 95 96 void 97 platform_mp_init_secondary(void) 98 { 99 } 100 101 void mptramp(void); 102 void mptramp_end(void); 103 extern vm_offset_t mptramp_pmu_boot; 104 105 void 106 platform_mp_start_ap(void) 107 { 108 uint32_t reg, *src, *dst, cpu_num, div_val, cputype; 109 vm_offset_t pmu_boot_off; 110 /* 111 * Initialization procedure depends on core revision, 112 * in this step CHIP ID is checked to choose proper procedure 113 */ 114 cputype = cpu_ident(); 115 cputype &= CPU_ID_CPU_MASK; 116 117 /* 118 * Set the PA of CPU0 Boot Address Redirect register used in 119 * mptramp according to the actual SoC registers' base address. 120 */ 121 pmu_boot_off = (CPU_PMU(0) - MV_BASE) + CPU_PMU_BOOT; 122 mptramp_pmu_boot = fdt_immr_pa + pmu_boot_off; 123 dst = pmap_mapdev(0xffff0000, PAGE_SIZE); 124 for (src = (uint32_t *)mptramp; src < (uint32_t *)mptramp_end; 125 src++, dst++) { 126 *dst = *src; 127 } 128 pmap_unmapdev((vm_offset_t)dst, PAGE_SIZE); 129 if (cputype == CPU_ID_MV88SV584X_V7) { 130 /* Core rev A0 */ 131 div_val = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); 132 div_val &= 0x3f; 133 134 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) { 135 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); 136 reg &= CPU_DIVCLK_MASK(cpu_num); 137 reg |= div_val << (cpu_num * 8); 138 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg); 139 } 140 } else { 141 /* Core rev Z1 */ 142 div_val = 0x01; 143 144 if (mp_ncpus > 1) { 145 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0); 146 reg &= CPU_DIVCLK_MASK(3); 147 reg |= div_val << 24; 148 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0, reg); 149 } 150 151 for (cpu_num = 2; cpu_num < mp_ncpus; cpu_num++ ) { 152 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); 153 reg &= CPU_DIVCLK_MASK(cpu_num); 154 reg |= div_val << (cpu_num * 8); 155 write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg); 156 } 157 } 158 159 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0); 160 reg |= ((0x1 << (mp_ncpus - 1)) - 1) << 21; 161 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); 162 reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0); 163 reg |= 0x01000000; 164 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); 165 166 DELAY(100); 167 reg &= ~(0xf << 21); 168 write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); 169 DELAY(100); 170 171 bus_space_write_4(fdtbus_bs_tag, MV_BASE, CPU_RESUME_CONTROL, 0); 172 173 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) 174 bus_space_write_4(fdtbus_bs_tag, CPU_PMU(cpu_num), CPU_PMU_BOOT, 175 pmap_kextract((vm_offset_t)mpentry)); 176 177 cpu_idcache_wbinv_all(); 178 179 for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) 180 bus_space_write_4(fdtbus_bs_tag, MP, MP_SW_RESET(cpu_num), 0); 181 182 /* XXX: Temporary workaround for hangup after releasing AP's */ 183 wmb(); 184 DELAY(10); 185 186 armadaxp_init_coher_fabric(); 187 } 188 189 void 190 platform_ipi_send(cpuset_t cpus, u_int ipi) 191 { 192 193 pic_ipi_send(cpus, ipi); 194 } 195