1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 Semihalf. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * From: FreeBSD: src/sys/arm/mv/kirkwood/sheevaplug.c,v 1.2 2010/06/13 13:28:53 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 35 #include <machine/armreg.h> 36 #include <machine/bus.h> 37 #include <machine/cpu.h> 38 39 #include <arm/mv/mvwin.h> 40 #include <arm/mv/mvreg.h> 41 #include <arm/mv/mvvar.h> 42 43 #include <dev/ofw/openfirm.h> 44 45 #include <machine/fdt.h> 46 47 #define CPU_FREQ_FIELD(sar) (((0x01 & (sar >> 52)) << 3) | \ 48 (0x07 & (sar >> 21))) 49 #define FAB_FREQ_FIELD(sar) (((0x01 & (sar >> 51)) << 4) | \ 50 (0x0F & (sar >> 24))) 51 52 static uint32_t count_l2clk(void); 53 void armadaxp_l2_init(void); 54 void armadaxp_init_coher_fabric(void); 55 int platform_get_ncpus(void); 56 static uint64_t get_sar_value_armadaxp(void); 57 58 #define ARMADAXP_L2_BASE (MV_BASE + 0x8000) 59 #define ARMADAXP_L2_CTRL 0x100 60 #define L2_ENABLE (1 << 0) 61 #define ARMADAXP_L2_AUX_CTRL 0x104 62 #define L2_WBWT_MODE_MASK (3 << 0) 63 #define L2_WBWT_MODE_PAGE 0 64 #define L2_WBWT_MODE_WB 1 65 #define L2_WBWT_MODE_WT 2 66 #define L2_REP_STRAT_MASK (3 << 27) 67 #define L2_REP_STRAT_LSFR (1 << 27) 68 #define L2_REP_STRAT_SEMIPLRU (3 << 27) 69 70 #define ARMADAXP_L2_CNTR_CTRL 0x200 71 #define ARMADAXP_L2_CNTR_CONF(x) (0x204 + (x) * 0xc) 72 #define ARMADAXP_L2_CNTR2_VAL_LOW (0x208 + (x) * 0xc) 73 #define ARMADAXP_L2_CNTR2_VAL_HI (0x20c + (x) * 0xc) 74 75 #define ARMADAXP_L2_INT_CAUSE 0x220 76 77 #define ARMADAXP_L2_SYNC_BARRIER 0x700 78 #define ARMADAXP_L2_INV_WAY 0x778 79 #define ARMADAXP_L2_CLEAN_WAY 0x7BC 80 #define ARMADAXP_L2_FLUSH_PHYS 0x7F0 81 #define ARMADAXP_L2_FLUSH_WAY 0x7FC 82 83 #define MV_COHERENCY_FABRIC_BASE (MV_MBUS_BRIDGE_BASE + 0x200) 84 #define COHER_FABRIC_CTRL 0x00 85 #define COHER_FABRIC_CONF 0x04 86 #define COHER_FABRIC_CFU 0x28 87 #define COHER_FABRIC_CIB_CTRL 0x80 88 89 struct vco_freq_ratio { 90 uint8_t vco_cpu; /* VCO to CLK0(CPU) clock ratio */ 91 uint8_t vco_l2c; /* VCO to NB(L2 cache) clock ratio */ 92 uint8_t vco_hcl; /* VCO to HCLK(DDR controller) clock ratio */ 93 uint8_t vco_ddr; /* VCO to DR(DDR memory) clock ratio */ 94 }; 95 96 static struct vco_freq_ratio freq_conf_table[] = { 97 /*00*/ { 1, 1, 4, 2 }, 98 /*01*/ { 1, 2, 2, 2 }, 99 /*02*/ { 2, 2, 6, 3 }, 100 /*03*/ { 2, 2, 3, 3 }, 101 /*04*/ { 1, 2, 3, 3 }, 102 /*05*/ { 1, 2, 4, 2 }, 103 /*06*/ { 1, 1, 2, 2 }, 104 /*07*/ { 2, 3, 6, 6 }, 105 /*08*/ { 2, 3, 5, 5 }, 106 /*09*/ { 1, 2, 6, 3 }, 107 /*10*/ { 2, 4, 10, 5 }, 108 /*11*/ { 1, 3, 6, 6 }, 109 /*12*/ { 1, 2, 5, 5 }, 110 /*13*/ { 1, 3, 6, 3 }, 111 /*14*/ { 1, 2, 5, 5 }, 112 /*15*/ { 2, 2, 5, 5 }, 113 /*16*/ { 1, 1, 3, 3 }, 114 /*17*/ { 2, 5, 10, 10 }, 115 /*18*/ { 1, 3, 8, 4 }, 116 /*19*/ { 1, 1, 2, 1 }, 117 /*20*/ { 2, 3, 6, 3 }, 118 /*21*/ { 1, 2, 8, 4 }, 119 /*22*/ { 2, 5, 10, 5 } 120 }; 121 122 static uint16_t cpu_clock_table[] = { 123 1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000, 600, 667, 800, 1600, 124 2133, 2200, 2400 }; 125 126 static uint64_t 127 get_sar_value_armadaxp(void) 128 { 129 uint32_t sar_low, sar_high; 130 131 sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 132 SAMPLE_AT_RESET_HI); 133 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 134 SAMPLE_AT_RESET_LO); 135 return (((uint64_t)sar_high << 32) | sar_low); 136 } 137 138 uint32_t 139 get_tclk_armadaxp(void) 140 { 141 uint32_t cputype; 142 143 cputype = cp15_midr_get(); 144 cputype &= CPU_ID_CPU_MASK; 145 146 if (cputype == CPU_ID_MV88SV584X_V7) 147 return (TCLK_250MHZ); 148 else 149 return (TCLK_200MHZ); 150 } 151 152 uint32_t 153 get_cpu_freq_armadaxp(void) 154 { 155 156 return (0); 157 } 158 159 static uint32_t 160 count_l2clk(void) 161 { 162 uint64_t sar_reg; 163 uint32_t freq_vco, freq_l2clk; 164 uint8_t sar_cpu_freq, sar_fab_freq, array_size; 165 166 /* Get value of the SAR register and process it */ 167 sar_reg = get_sar_value_armadaxp(); 168 sar_cpu_freq = CPU_FREQ_FIELD(sar_reg); 169 sar_fab_freq = FAB_FREQ_FIELD(sar_reg); 170 171 /* Check if CPU frequency field has correct value */ 172 array_size = nitems(cpu_clock_table); 173 if (sar_cpu_freq >= array_size) 174 panic("Reserved value in cpu frequency configuration field: " 175 "%d", sar_cpu_freq); 176 177 /* Check if fabric frequency field has correct value */ 178 array_size = nitems(freq_conf_table); 179 if (sar_fab_freq >= array_size) 180 panic("Reserved value in fabric frequency configuration field: " 181 "%d", sar_fab_freq); 182 183 /* Get CPU clock frequency */ 184 freq_vco = cpu_clock_table[sar_cpu_freq] * 185 freq_conf_table[sar_fab_freq].vco_cpu; 186 187 /* Get L2CLK clock frequency */ 188 freq_l2clk = freq_vco / freq_conf_table[sar_fab_freq].vco_l2c; 189 190 /* Round L2CLK value to integer MHz */ 191 if (((freq_vco % freq_conf_table[sar_fab_freq].vco_l2c) * 10 / 192 freq_conf_table[sar_fab_freq].vco_l2c) >= 5) 193 freq_l2clk++; 194 195 return (freq_l2clk * 1000000); 196 } 197 198 uint32_t 199 get_l2clk(void) 200 { 201 static uint32_t l2clk_freq = 0; 202 203 /* If get_l2clk is called first time get L2CLK value from register */ 204 if (l2clk_freq == 0) 205 l2clk_freq = count_l2clk(); 206 207 return (l2clk_freq); 208 } 209 210 static uint32_t 211 read_coher_fabric(uint32_t reg) 212 { 213 214 return (bus_space_read_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg)); 215 } 216 217 static void 218 write_coher_fabric(uint32_t reg, uint32_t val) 219 { 220 221 bus_space_write_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg, val); 222 } 223 224 int 225 platform_get_ncpus(void) 226 { 227 #if !defined(SMP) 228 return (1); 229 #else 230 return ((read_coher_fabric(COHER_FABRIC_CONF) & 0xf) + 1); 231 #endif 232 } 233 234 void 235 armadaxp_init_coher_fabric(void) 236 { 237 uint32_t val, cpus, mask; 238 239 cpus = platform_get_ncpus(); 240 mask = (1 << cpus) - 1; 241 val = read_coher_fabric(COHER_FABRIC_CTRL); 242 val |= (mask << 24); 243 write_coher_fabric(COHER_FABRIC_CTRL, val); 244 245 val = read_coher_fabric(COHER_FABRIC_CONF); 246 val |= (mask << 24); 247 val |= (1 << 15); 248 write_coher_fabric(COHER_FABRIC_CONF, val); 249 } 250 251 #define ALL_WAYS 0xffffffff 252 253 /* L2 cache configuration registers */ 254 static uint32_t 255 read_l2_cache(uint32_t reg) 256 { 257 258 return (bus_space_read_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg)); 259 } 260 261 static void 262 write_l2_cache(uint32_t reg, uint32_t val) 263 { 264 265 bus_space_write_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg, val); 266 } 267 268 static void 269 armadaxp_l2_idcache_inv_all(void) 270 { 271 write_l2_cache(ARMADAXP_L2_INV_WAY, ALL_WAYS); 272 } 273 274 void 275 armadaxp_l2_init(void) 276 { 277 u_int32_t reg; 278 279 /* Set L2 policy */ 280 reg = read_l2_cache(ARMADAXP_L2_AUX_CTRL); 281 reg &= ~(L2_WBWT_MODE_MASK); 282 reg &= ~(L2_REP_STRAT_MASK); 283 reg |= L2_REP_STRAT_SEMIPLRU; 284 reg |= L2_WBWT_MODE_WT; 285 write_l2_cache(ARMADAXP_L2_AUX_CTRL, reg); 286 287 /* Invalidate l2 cache */ 288 armadaxp_l2_idcache_inv_all(); 289 290 /* Clear pending L2 interrupts */ 291 write_l2_cache(ARMADAXP_L2_INT_CAUSE, 0x1ff); 292 293 /* Enable l2 cache */ 294 reg = read_l2_cache(ARMADAXP_L2_CTRL); 295 write_l2_cache(ARMADAXP_L2_CTRL, reg | L2_ENABLE); 296 297 /* 298 * For debug purposes 299 * Configure and enable counter 300 */ 301 write_l2_cache(ARMADAXP_L2_CNTR_CONF(0), 0xf0000 | (4 << 2)); 302 write_l2_cache(ARMADAXP_L2_CNTR_CONF(1), 0xf0000 | (2 << 2)); 303 write_l2_cache(ARMADAXP_L2_CNTR_CTRL, 0x303); 304 305 /* 306 * Enable Cache maintenance operation propagation in coherency fabric 307 * Change point of coherency and point of unification to DRAM. 308 */ 309 reg = read_coher_fabric(COHER_FABRIC_CFU); 310 reg |= (1 << 17) | (1 << 18); 311 write_coher_fabric(COHER_FABRIC_CFU, reg); 312 313 /* Coherent IO Bridge initialization */ 314 reg = read_coher_fabric(COHER_FABRIC_CIB_CTRL); 315 reg &= ~(7 << 16); 316 reg |= (7 << 16); 317 write_coher_fabric(COHER_FABRIC_CIB_CTRL, reg); 318 } 319