1 /*- 2 * Copyright (c) 2011 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * From: FreeBSD: src/sys/arm/mv/kirkwood/sheevaplug.c,v 1.2 2010/06/13 13:28:53 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 36 #include <machine/bus.h> 37 #include <machine/armreg.h> 38 39 #include <arm/mv/mvwin.h> 40 #include <arm/mv/mvreg.h> 41 #include <arm/mv/mvvar.h> 42 43 #include <dev/fdt/fdt_common.h> 44 #include <dev/ofw/openfirm.h> 45 46 #include <machine/fdt.h> 47 48 #define CPU_FREQ_FIELD(sar) (((0x01 & (sar >> 52)) << 3) | \ 49 (0x07 & (sar >> 21))) 50 #define FAB_FREQ_FIELD(sar) (((0x01 & (sar >> 51)) << 4) | \ 51 (0x0F & (sar >> 24))) 52 53 static uint32_t count_l2clk(void); 54 void armadaxp_l2_init(void); 55 void armadaxp_init_coher_fabric(void); 56 int platform_get_ncpus(void); 57 58 #define ARMADAXP_L2_BASE (MV_BASE + 0x8000) 59 #define ARMADAXP_L2_CTRL 0x100 60 #define L2_ENABLE (1 << 0) 61 #define ARMADAXP_L2_AUX_CTRL 0x104 62 #define L2_WBWT_MODE_MASK (3 << 0) 63 #define L2_WBWT_MODE_PAGE 0 64 #define L2_WBWT_MODE_WB 1 65 #define L2_WBWT_MODE_WT 2 66 #define L2_REP_STRAT_MASK (3 << 27) 67 #define L2_REP_STRAT_LSFR (1 << 27) 68 #define L2_REP_STRAT_SEMIPLRU (3 << 27) 69 70 #define ARMADAXP_L2_CNTR_CTRL 0x200 71 #define ARMADAXP_L2_CNTR_CONF(x) (0x204 + (x) * 0xc) 72 #define ARMADAXP_L2_CNTR2_VAL_LOW (0x208 + (x) * 0xc) 73 #define ARMADAXP_L2_CNTR2_VAL_HI (0x20c + (x) * 0xc) 74 75 #define ARMADAXP_L2_INT_CAUSE 0x220 76 77 #define ARMADAXP_L2_SYNC_BARRIER 0x700 78 #define ARMADAXP_L2_INV_WAY 0x778 79 #define ARMADAXP_L2_CLEAN_WAY 0x7BC 80 #define ARMADAXP_L2_FLUSH_PHYS 0x7F0 81 #define ARMADAXP_L2_FLUSH_WAY 0x7FC 82 83 #define MV_COHERENCY_FABRIC_BASE (MV_MBUS_BRIDGE_BASE + 0x200) 84 #define COHER_FABRIC_CTRL 0x00 85 #define COHER_FABRIC_CONF 0x04 86 #define COHER_FABRIC_CFU 0x28 87 #define COHER_FABRIC_CIB_CTRL 0x80 88 89 /* XXX Make gpio driver optional and remove it */ 90 struct resource_spec mv_gpio_res[] = { 91 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 92 { SYS_RES_IRQ, 0, RF_ACTIVE }, 93 { -1, 0 } 94 }; 95 96 struct vco_freq_ratio { 97 uint8_t vco_cpu; /* VCO to CLK0(CPU) clock ratio */ 98 uint8_t vco_l2c; /* VCO to NB(L2 cache) clock ratio */ 99 uint8_t vco_hcl; /* VCO to HCLK(DDR controller) clock ratio */ 100 uint8_t vco_ddr; /* VCO to DR(DDR memory) clock ratio */ 101 }; 102 103 static struct vco_freq_ratio freq_conf_table[] = { 104 /*00*/ { 1, 1, 4, 2 }, 105 /*01*/ { 1, 2, 2, 2 }, 106 /*02*/ { 2, 2, 6, 3 }, 107 /*03*/ { 2, 2, 3, 3 }, 108 /*04*/ { 1, 2, 3, 3 }, 109 /*05*/ { 1, 2, 4, 2 }, 110 /*06*/ { 1, 1, 2, 2 }, 111 /*07*/ { 2, 3, 6, 6 }, 112 /*08*/ { 2, 3, 5, 5 }, 113 /*09*/ { 1, 2, 6, 3 }, 114 /*10*/ { 2, 4, 10, 5 }, 115 /*11*/ { 1, 3, 6, 6 }, 116 /*12*/ { 1, 2, 5, 5 }, 117 /*13*/ { 1, 3, 6, 3 }, 118 /*14*/ { 1, 2, 5, 5 }, 119 /*15*/ { 2, 2, 5, 5 }, 120 /*16*/ { 1, 1, 3, 3 }, 121 /*17*/ { 2, 5, 10, 10 }, 122 /*18*/ { 1, 3, 8, 4 }, 123 /*19*/ { 1, 1, 2, 1 }, 124 /*20*/ { 2, 3, 6, 3 }, 125 /*21*/ { 1, 2, 8, 4 }, 126 /*22*/ { 2, 5, 10, 5 } 127 }; 128 129 static uint16_t cpu_clock_table[] = { 130 1000, 1066, 1200, 1333, 1500, 1666, 1800, 2000, 600, 667, 800, 1600, 131 2133, 2200, 2400 }; 132 133 uint32_t 134 get_tclk(void) 135 { 136 uint32_t cputype; 137 138 cputype = cpufunc_id(); 139 cputype &= CPU_ID_CPU_MASK; 140 141 if (cputype == CPU_ID_MV88SV584X_V7) 142 return (TCLK_250MHZ); 143 else 144 return (TCLK_200MHZ); 145 } 146 147 static uint32_t 148 count_l2clk(void) 149 { 150 uint64_t sar_reg; 151 uint32_t freq_vco, freq_l2clk; 152 uint8_t sar_cpu_freq, sar_fab_freq, array_size; 153 154 /* Get value of the SAR register and process it */ 155 sar_reg = get_sar_value(); 156 sar_cpu_freq = CPU_FREQ_FIELD(sar_reg); 157 sar_fab_freq = FAB_FREQ_FIELD(sar_reg); 158 159 /* Check if CPU frequency field has correct value */ 160 array_size = sizeof(cpu_clock_table) / sizeof(cpu_clock_table[0]); 161 if (sar_cpu_freq >= array_size) 162 panic("Reserved value in cpu frequency configuration field: " 163 "%d", sar_cpu_freq); 164 165 /* Check if fabric frequency field has correct value */ 166 array_size = sizeof(freq_conf_table) / sizeof(freq_conf_table[0]); 167 if (sar_fab_freq >= array_size) 168 panic("Reserved value in fabric frequency configuration field: " 169 "%d", sar_fab_freq); 170 171 /* Get CPU clock frequency */ 172 freq_vco = cpu_clock_table[sar_cpu_freq] * 173 freq_conf_table[sar_fab_freq].vco_cpu; 174 175 /* Get L2CLK clock frequency */ 176 freq_l2clk = freq_vco / freq_conf_table[sar_fab_freq].vco_l2c; 177 178 /* Round L2CLK value to integer MHz */ 179 if (((freq_vco % freq_conf_table[sar_fab_freq].vco_l2c) * 10 / 180 freq_conf_table[sar_fab_freq].vco_l2c) >= 5) 181 freq_l2clk++; 182 183 return (freq_l2clk * 1000000); 184 } 185 186 uint32_t 187 get_l2clk(void) 188 { 189 static uint32_t l2clk_freq = 0; 190 191 /* If get_l2clk is called first time get L2CLK value from register */ 192 if (l2clk_freq == 0) 193 l2clk_freq = count_l2clk(); 194 195 return (l2clk_freq); 196 } 197 198 static uint32_t 199 read_coher_fabric(uint32_t reg) 200 { 201 202 return (bus_space_read_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg)); 203 } 204 205 static void 206 write_coher_fabric(uint32_t reg, uint32_t val) 207 { 208 209 bus_space_write_4(fdtbus_bs_tag, MV_COHERENCY_FABRIC_BASE, reg, val); 210 } 211 212 int 213 platform_get_ncpus(void) 214 { 215 #if !defined(SMP) 216 return (1); 217 #else 218 return ((read_coher_fabric(COHER_FABRIC_CONF) & 0xf) + 1); 219 #endif 220 } 221 222 void 223 armadaxp_init_coher_fabric(void) 224 { 225 uint32_t val, cpus, mask; 226 227 cpus = platform_get_ncpus(); 228 mask = (1 << cpus) - 1; 229 val = read_coher_fabric(COHER_FABRIC_CTRL); 230 val |= (mask << 24); 231 write_coher_fabric(COHER_FABRIC_CTRL, val); 232 233 val = read_coher_fabric(COHER_FABRIC_CONF); 234 val |= (mask << 24); 235 val |= (1 << 15); 236 write_coher_fabric(COHER_FABRIC_CONF, val); 237 } 238 239 #define ALL_WAYS 0xffffffff 240 241 /* L2 cache configuration registers */ 242 static uint32_t 243 read_l2_cache(uint32_t reg) 244 { 245 246 return (bus_space_read_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg)); 247 } 248 249 static void 250 write_l2_cache(uint32_t reg, uint32_t val) 251 { 252 253 bus_space_write_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg, val); 254 } 255 256 static void 257 armadaxp_l2_idcache_inv_all(void) 258 { 259 write_l2_cache(ARMADAXP_L2_INV_WAY, ALL_WAYS); 260 } 261 262 void 263 armadaxp_l2_init(void) 264 { 265 u_int32_t reg; 266 267 /* Set L2 policy */ 268 reg = read_l2_cache(ARMADAXP_L2_AUX_CTRL); 269 reg &= ~(L2_WBWT_MODE_MASK); 270 reg &= ~(L2_REP_STRAT_MASK); 271 reg |= L2_REP_STRAT_SEMIPLRU; 272 reg |= L2_WBWT_MODE_WT; 273 write_l2_cache(ARMADAXP_L2_AUX_CTRL, reg); 274 275 /* Invalidate l2 cache */ 276 armadaxp_l2_idcache_inv_all(); 277 278 /* Clear pending L2 interrupts */ 279 write_l2_cache(ARMADAXP_L2_INT_CAUSE, 0x1ff); 280 281 /* Enable l2 cache */ 282 reg = read_l2_cache(ARMADAXP_L2_CTRL); 283 write_l2_cache(ARMADAXP_L2_CTRL, reg | L2_ENABLE); 284 285 /* 286 * For debug purposes 287 * Configure and enable counter 288 */ 289 write_l2_cache(ARMADAXP_L2_CNTR_CONF(0), 0xf0000 | (4 << 2)); 290 write_l2_cache(ARMADAXP_L2_CNTR_CONF(1), 0xf0000 | (2 << 2)); 291 write_l2_cache(ARMADAXP_L2_CNTR_CTRL, 0x303); 292 293 /* 294 * Enable Cache maintenance operation propagation in coherency fabric 295 * Change point of coherency and point of unification to DRAM. 296 */ 297 reg = read_coher_fabric(COHER_FABRIC_CFU); 298 reg |= (1 << 17) | (1 << 18); 299 write_coher_fabric(COHER_FABRIC_CFU, reg); 300 301 /* Coherent IO Bridge initialization */ 302 reg = read_coher_fabric(COHER_FABRIC_CIB_CTRL); 303 reg &= ~(7 << 16); 304 reg |= (7 << 16); 305 write_coher_fabric(COHER_FABRIC_CIB_CTRL, reg); 306 } 307 308