1 /*- 2 * Copyright (c) 2015 Semihalf. 3 * Copyright (c) 2015 Stormshield. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/bus.h> 31 #include <sys/lock.h> 32 #include <sys/time.h> 33 #include <sys/proc.h> 34 #include <sys/conf.h> 35 #include <sys/rman.h> 36 #include <sys/clock.h> 37 #include <sys/systm.h> 38 #include <sys/mutex.h> 39 #include <sys/types.h> 40 #include <sys/kernel.h> 41 #include <sys/module.h> 42 #include <sys/resource.h> 43 44 #include <machine/bus.h> 45 #include <machine/resource.h> 46 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include "clock_if.h" 51 52 #define RTC_RES_US 1000000 53 #define HALF_OF_SEC_NS 500000000 54 55 #define RTC_STATUS 0x0 56 #define RTC_TIME 0xC 57 #define RTC_TEST_CONFIG 0x1C 58 #define RTC_IRQ_1_CONFIG 0x4 59 #define RTC_IRQ_2_CONFIG 0x8 60 #define RTC_ALARM_1 0x10 61 #define RTC_ALARM_2 0x14 62 #define RTC_CLOCK_CORR 0x18 63 64 #define RTC_NOMINAL_TIMING 0x2000 65 #define RTC_NOMINAL_TIMING_MASK 0x7fff 66 67 #define RTC_STATUS_ALARM1_MASK 0x1 68 #define RTC_STATUS_ALARM2_MASK 0x2 69 70 #define MV_RTC_LOCK(sc) mtx_lock_spin(&(sc)->mutex) 71 #define MV_RTC_UNLOCK(sc) mtx_unlock_spin(&(sc)->mutex) 72 73 #define A38X_RTC_BRIDGE_TIMING_CTRL 0x0 74 #define A38X_RTC_WRCLK_PERIOD_SHIFT 0 75 #define A38X_RTC_WRCLK_PERIOD_MASK 0x00000003FF 76 #define A38X_RTC_WRCLK_PERIOD_MAX 0x3FF 77 #define A38X_RTC_READ_OUTPUT_DELAY_SHIFT 26 78 #define A38X_RTC_READ_OUTPUT_DELAY_MASK 0x007C000000 79 #define A38X_RTC_READ_OUTPUT_DELAY_MAX 0x1F 80 81 #define A8K_RTC_BRIDGE_TIMING_CTRL0 0x0 82 #define A8K_RTC_WRCLK_PERIOD_SHIFT 0 83 #define A8K_RTC_WRCLK_PERIOD_MASK 0x000000FFFF 84 #define A8K_RTC_WRCLK_PERIOD_VAL 0x3FF 85 #define A8K_RTC_WRCLK_SETUP_SHIFT 16 86 #define A8K_RTC_WRCLK_SETUP_MASK 0x00FFFF0000 87 #define A8K_RTC_WRCLK_SETUP_VAL 29 88 #define A8K_RTC_BRIDGE_TIMING_CTRL1 0x4 89 #define A8K_RTC_READ_OUTPUT_DELAY_SHIFT 0 90 #define A8K_RTC_READ_OUTPUT_DELAY_MASK 0x000000FFFF 91 #define A8K_RTC_READ_OUTPUT_DELAY_VAL 0x3F 92 93 #define RTC_RES 0 94 #define RTC_SOC_RES 1 95 96 static struct resource_spec res_spec[] = { 97 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 98 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 99 { -1, 0 } 100 }; 101 102 struct mv_rtc_softc { 103 device_t dev; 104 struct resource *res[2]; 105 struct mtx mutex; 106 int rtc_type; 107 }; 108 109 static int mv_rtc_probe(device_t dev); 110 static int mv_rtc_attach(device_t dev); 111 static int mv_rtc_detach(device_t dev); 112 113 static int mv_rtc_gettime(device_t dev, struct timespec *ts); 114 static int mv_rtc_settime(device_t dev, struct timespec *ts); 115 116 static inline uint32_t mv_rtc_reg_read(struct mv_rtc_softc *sc, 117 bus_size_t off); 118 static inline int mv_rtc_reg_write(struct mv_rtc_softc *sc, bus_size_t off, 119 uint32_t val); 120 static inline void mv_rtc_configure_bus_a38x(struct mv_rtc_softc *sc); 121 static inline void mv_rtc_configure_bus_a8k(struct mv_rtc_softc *sc); 122 123 static device_method_t mv_rtc_methods[] = { 124 DEVMETHOD(device_probe, mv_rtc_probe), 125 DEVMETHOD(device_attach, mv_rtc_attach), 126 DEVMETHOD(device_detach, mv_rtc_detach), 127 128 DEVMETHOD(clock_gettime, mv_rtc_gettime), 129 DEVMETHOD(clock_settime, mv_rtc_settime), 130 131 { 0, 0 }, 132 }; 133 134 static driver_t mv_rtc_driver = { 135 "rtc", 136 mv_rtc_methods, 137 sizeof(struct mv_rtc_softc), 138 }; 139 140 #define RTC_A38X 1 141 #define RTC_A8K 2 142 143 static struct ofw_compat_data mv_rtc_compat[] = { 144 {"marvell,armada-380-rtc", RTC_A38X}, 145 {"marvell,armada-8k-rtc", RTC_A8K}, 146 {NULL, 0}, 147 }; 148 149 DRIVER_MODULE(a38x_rtc, simplebus, mv_rtc_driver, 0, 0); 150 151 static void 152 mv_rtc_reset(device_t dev) 153 { 154 struct mv_rtc_softc *sc; 155 156 sc = device_get_softc(dev); 157 158 /* Reset Test register */ 159 mv_rtc_reg_write(sc, RTC_TEST_CONFIG, 0); 160 DELAY(500000); 161 162 /* Reset Time register */ 163 mv_rtc_reg_write(sc, RTC_TIME, 0); 164 DELAY(62); 165 166 /* Reset Status register */ 167 mv_rtc_reg_write(sc, RTC_STATUS, (RTC_STATUS_ALARM1_MASK | RTC_STATUS_ALARM2_MASK)); 168 DELAY(62); 169 170 /* Turn off Int1 and Int2 sources & clear the Alarm count */ 171 mv_rtc_reg_write(sc, RTC_IRQ_1_CONFIG, 0); 172 mv_rtc_reg_write(sc, RTC_IRQ_2_CONFIG, 0); 173 mv_rtc_reg_write(sc, RTC_ALARM_1, 0); 174 mv_rtc_reg_write(sc, RTC_ALARM_2, 0); 175 176 /* Setup nominal register access timing */ 177 mv_rtc_reg_write(sc, RTC_CLOCK_CORR, RTC_NOMINAL_TIMING); 178 179 /* Reset Time register */ 180 mv_rtc_reg_write(sc, RTC_TIME, 0); 181 DELAY(10); 182 183 /* Reset Status register */ 184 mv_rtc_reg_write(sc, RTC_STATUS, (RTC_STATUS_ALARM1_MASK | RTC_STATUS_ALARM2_MASK)); 185 DELAY(50); 186 } 187 188 static int 189 mv_rtc_probe(device_t dev) 190 { 191 192 if (!ofw_bus_status_okay(dev)) 193 return (ENXIO); 194 195 if (!ofw_bus_search_compatible(dev, mv_rtc_compat)->ocd_data) 196 return (ENXIO); 197 198 device_set_desc(dev, "Marvell Integrated RTC"); 199 200 return (BUS_PROBE_DEFAULT); 201 } 202 203 static int 204 mv_rtc_attach(device_t dev) 205 { 206 struct mv_rtc_softc *sc; 207 int ret; 208 209 sc = device_get_softc(dev); 210 sc->dev = dev; 211 sc->rtc_type = ofw_bus_search_compatible(dev, mv_rtc_compat)->ocd_data; 212 213 mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN); 214 215 ret = bus_alloc_resources(dev, res_spec, sc->res); 216 if (ret != 0) { 217 device_printf(dev, "could not allocate resources\n"); 218 mtx_destroy(&sc->mutex); 219 return (ENXIO); 220 } 221 222 switch (sc->rtc_type) { 223 case RTC_A38X: 224 mv_rtc_configure_bus_a38x(sc); 225 break; 226 case RTC_A8K: 227 mv_rtc_configure_bus_a8k(sc); 228 break; 229 default: 230 panic("Unknown RTC type: %d", sc->rtc_type); 231 } 232 clock_register(dev, RTC_RES_US); 233 234 return (0); 235 } 236 237 static int 238 mv_rtc_detach(device_t dev) 239 { 240 struct mv_rtc_softc *sc; 241 242 sc = device_get_softc(dev); 243 244 mtx_destroy(&sc->mutex); 245 246 bus_release_resources(dev, res_spec, sc->res); 247 248 return (0); 249 } 250 251 static int 252 mv_rtc_gettime(device_t dev, struct timespec *ts) 253 { 254 struct mv_rtc_softc *sc; 255 uint32_t val, val_check; 256 257 sc = device_get_softc(dev); 258 259 MV_RTC_LOCK(sc); 260 /* 261 * According to HW Errata, if more than one second is detected 262 * between two time reads, then at least one of the reads gave 263 * an invalid value. 264 */ 265 do { 266 val = mv_rtc_reg_read(sc, RTC_TIME); 267 DELAY(100); 268 val_check = mv_rtc_reg_read(sc, RTC_TIME); 269 } while ((val_check - val) > 1); 270 271 MV_RTC_UNLOCK(sc); 272 273 ts->tv_sec = val_check; 274 /* RTC resolution is 1 sec */ 275 ts->tv_nsec = 0; 276 277 return (0); 278 } 279 280 static int 281 mv_rtc_settime(device_t dev, struct timespec *ts) 282 { 283 struct mv_rtc_softc *sc; 284 285 sc = device_get_softc(dev); 286 287 /* RTC resolution is 1 sec */ 288 if (ts->tv_nsec >= HALF_OF_SEC_NS) 289 ts->tv_sec++; 290 ts->tv_nsec = 0; 291 292 MV_RTC_LOCK(sc); 293 294 if ((mv_rtc_reg_read(sc, RTC_CLOCK_CORR) & RTC_NOMINAL_TIMING_MASK) != 295 RTC_NOMINAL_TIMING) { 296 /* RTC was not resetted yet */ 297 mv_rtc_reset(dev); 298 } 299 300 /* 301 * According to errata FE-3124064, Write to RTC TIME register 302 * may fail. As a workaround, before writing to RTC TIME register, 303 * issue a dummy write of 0x0 twice to RTC Status register. 304 */ 305 mv_rtc_reg_write(sc, RTC_STATUS, 0x0); 306 mv_rtc_reg_write(sc, RTC_STATUS, 0x0); 307 mv_rtc_reg_write(sc, RTC_TIME, ts->tv_sec); 308 MV_RTC_UNLOCK(sc); 309 310 return (0); 311 } 312 313 static inline uint32_t 314 mv_rtc_reg_read(struct mv_rtc_softc *sc, bus_size_t off) 315 { 316 317 return (bus_read_4(sc->res[RTC_RES], off)); 318 } 319 320 /* 321 * According to the datasheet, the OS should wait 5us after every 322 * register write to the RTC hard macro so that the required update 323 * can occur without holding off the system bus 324 */ 325 static inline int 326 mv_rtc_reg_write(struct mv_rtc_softc *sc, bus_size_t off, uint32_t val) 327 { 328 329 bus_write_4(sc->res[RTC_RES], off, val); 330 DELAY(5); 331 332 return (0); 333 } 334 335 static inline void 336 mv_rtc_configure_bus_a38x(struct mv_rtc_softc *sc) 337 { 338 int val; 339 340 val = bus_read_4(sc->res[RTC_SOC_RES], A38X_RTC_BRIDGE_TIMING_CTRL); 341 val &= ~(A38X_RTC_WRCLK_PERIOD_MASK | A38X_RTC_READ_OUTPUT_DELAY_MASK); 342 val |= A38X_RTC_WRCLK_PERIOD_MAX << A38X_RTC_WRCLK_PERIOD_SHIFT; 343 val |= A38X_RTC_READ_OUTPUT_DELAY_MAX << A38X_RTC_READ_OUTPUT_DELAY_SHIFT; 344 bus_write_4(sc->res[RTC_SOC_RES], A38X_RTC_BRIDGE_TIMING_CTRL, val); 345 } 346 347 static inline void 348 mv_rtc_configure_bus_a8k(struct mv_rtc_softc *sc) 349 { 350 int val; 351 352 val = bus_read_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL0); 353 val &= ~(A8K_RTC_WRCLK_PERIOD_MASK | A8K_RTC_WRCLK_SETUP_MASK); 354 val |= A8K_RTC_WRCLK_PERIOD_VAL << A8K_RTC_WRCLK_PERIOD_SHIFT; 355 val |= A8K_RTC_WRCLK_SETUP_VAL << A8K_RTC_WRCLK_SETUP_SHIFT; 356 bus_write_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL1, val); 357 358 val = bus_read_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL0); 359 val &= ~A8K_RTC_READ_OUTPUT_DELAY_MASK; 360 val |= A8K_RTC_READ_OUTPUT_DELAY_VAL << A8K_RTC_READ_OUTPUT_DELAY_SHIFT; 361 bus_write_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL1, val); 362 } 363