1 /*- 2 * Copyright (c) 2015 Semihalf. 3 * Copyright (c) 2015 Stormshield. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/lock.h> 34 #include <sys/time.h> 35 #include <sys/proc.h> 36 #include <sys/conf.h> 37 #include <sys/rman.h> 38 #include <sys/clock.h> 39 #include <sys/systm.h> 40 #include <sys/mutex.h> 41 #include <sys/types.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/resource.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include "clock_if.h" 53 54 #define RTC_RES_US 1000000 55 #define HALF_OF_SEC_NS 500000000 56 57 #define RTC_STATUS 0x0 58 #define RTC_TIME 0xC 59 #define RTC_TEST_CONFIG 0x1C 60 #define RTC_IRQ_1_CONFIG 0x4 61 #define RTC_IRQ_2_CONFIG 0x8 62 #define RTC_ALARM_1 0x10 63 #define RTC_ALARM_2 0x14 64 #define RTC_CLOCK_CORR 0x18 65 66 #define RTC_NOMINAL_TIMING 0x2000 67 #define RTC_NOMINAL_TIMING_MASK 0x7fff 68 69 #define RTC_STATUS_ALARM1_MASK 0x1 70 #define RTC_STATUS_ALARM2_MASK 0x2 71 72 #define MV_RTC_LOCK(sc) mtx_lock_spin(&(sc)->mutex) 73 #define MV_RTC_UNLOCK(sc) mtx_unlock_spin(&(sc)->mutex) 74 75 #define A38X_RTC_BRIDGE_TIMING_CTRL 0x0 76 #define A38X_RTC_WRCLK_PERIOD_SHIFT 0 77 #define A38X_RTC_WRCLK_PERIOD_MASK 0x00000003FF 78 #define A38X_RTC_WRCLK_PERIOD_MAX 0x3FF 79 #define A38X_RTC_READ_OUTPUT_DELAY_SHIFT 26 80 #define A38X_RTC_READ_OUTPUT_DELAY_MASK 0x007C000000 81 #define A38X_RTC_READ_OUTPUT_DELAY_MAX 0x1F 82 83 #define A8K_RTC_BRIDGE_TIMING_CTRL0 0x0 84 #define A8K_RTC_WRCLK_PERIOD_SHIFT 0 85 #define A8K_RTC_WRCLK_PERIOD_MASK 0x000000FFFF 86 #define A8K_RTC_WRCLK_PERIOD_VAL 0x3FF 87 #define A8K_RTC_WRCLK_SETUP_SHIFT 16 88 #define A8K_RTC_WRCLK_SETUP_MASK 0x00FFFF0000 89 #define A8K_RTC_WRCLK_SETUP_VAL 29 90 #define A8K_RTC_BRIDGE_TIMING_CTRL1 0x4 91 #define A8K_RTC_READ_OUTPUT_DELAY_SHIFT 0 92 #define A8K_RTC_READ_OUTPUT_DELAY_MASK 0x000000FFFF 93 #define A8K_RTC_READ_OUTPUT_DELAY_VAL 0x3F 94 95 96 #define RTC_RES 0 97 #define RTC_SOC_RES 1 98 99 100 static struct resource_spec res_spec[] = { 101 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 102 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 103 { -1, 0 } 104 }; 105 106 struct mv_rtc_softc { 107 device_t dev; 108 struct resource *res[2]; 109 struct mtx mutex; 110 int rtc_type; 111 }; 112 113 static int mv_rtc_probe(device_t dev); 114 static int mv_rtc_attach(device_t dev); 115 static int mv_rtc_detach(device_t dev); 116 117 static int mv_rtc_gettime(device_t dev, struct timespec *ts); 118 static int mv_rtc_settime(device_t dev, struct timespec *ts); 119 120 static inline uint32_t mv_rtc_reg_read(struct mv_rtc_softc *sc, 121 bus_size_t off); 122 static inline int mv_rtc_reg_write(struct mv_rtc_softc *sc, bus_size_t off, 123 uint32_t val); 124 static inline void mv_rtc_configure_bus_a38x(struct mv_rtc_softc *sc); 125 static inline void mv_rtc_configure_bus_a8k(struct mv_rtc_softc *sc); 126 127 static device_method_t mv_rtc_methods[] = { 128 DEVMETHOD(device_probe, mv_rtc_probe), 129 DEVMETHOD(device_attach, mv_rtc_attach), 130 DEVMETHOD(device_detach, mv_rtc_detach), 131 132 DEVMETHOD(clock_gettime, mv_rtc_gettime), 133 DEVMETHOD(clock_settime, mv_rtc_settime), 134 135 { 0, 0 }, 136 }; 137 138 static driver_t mv_rtc_driver = { 139 "rtc", 140 mv_rtc_methods, 141 sizeof(struct mv_rtc_softc), 142 }; 143 144 #define RTC_A38X 1 145 #define RTC_A8K 2 146 147 static struct ofw_compat_data mv_rtc_compat[] = { 148 {"marvell,armada-380-rtc", RTC_A38X}, 149 {"marvell,armada-8k-rtc", RTC_A8K}, 150 {NULL, 0}, 151 }; 152 153 static devclass_t mv_rtc_devclass; 154 155 DRIVER_MODULE(a38x_rtc, simplebus, mv_rtc_driver, mv_rtc_devclass, 0, 0); 156 157 static void 158 mv_rtc_reset(device_t dev) 159 { 160 struct mv_rtc_softc *sc; 161 162 sc = device_get_softc(dev); 163 164 /* Reset Test register */ 165 mv_rtc_reg_write(sc, RTC_TEST_CONFIG, 0); 166 DELAY(500000); 167 168 /* Reset Time register */ 169 mv_rtc_reg_write(sc, RTC_TIME, 0); 170 DELAY(62); 171 172 /* Reset Status register */ 173 mv_rtc_reg_write(sc, RTC_STATUS, (RTC_STATUS_ALARM1_MASK | RTC_STATUS_ALARM2_MASK)); 174 DELAY(62); 175 176 /* Turn off Int1 and Int2 sources & clear the Alarm count */ 177 mv_rtc_reg_write(sc, RTC_IRQ_1_CONFIG, 0); 178 mv_rtc_reg_write(sc, RTC_IRQ_2_CONFIG, 0); 179 mv_rtc_reg_write(sc, RTC_ALARM_1, 0); 180 mv_rtc_reg_write(sc, RTC_ALARM_2, 0); 181 182 /* Setup nominal register access timing */ 183 mv_rtc_reg_write(sc, RTC_CLOCK_CORR, RTC_NOMINAL_TIMING); 184 185 /* Reset Time register */ 186 mv_rtc_reg_write(sc, RTC_TIME, 0); 187 DELAY(10); 188 189 /* Reset Status register */ 190 mv_rtc_reg_write(sc, RTC_STATUS, (RTC_STATUS_ALARM1_MASK | RTC_STATUS_ALARM2_MASK)); 191 DELAY(50); 192 } 193 194 static int 195 mv_rtc_probe(device_t dev) 196 { 197 198 if (!ofw_bus_status_okay(dev)) 199 return (ENXIO); 200 201 if (!ofw_bus_search_compatible(dev, mv_rtc_compat)->ocd_data) 202 return (ENXIO); 203 204 device_set_desc(dev, "Marvell Integrated RTC"); 205 206 return (BUS_PROBE_DEFAULT); 207 } 208 209 static int 210 mv_rtc_attach(device_t dev) 211 { 212 struct mv_rtc_softc *sc; 213 int unit, ret; 214 215 unit = device_get_unit(dev); 216 217 sc = device_get_softc(dev); 218 sc->dev = dev; 219 sc->rtc_type = ofw_bus_search_compatible(dev, mv_rtc_compat)->ocd_data; 220 221 mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN); 222 223 ret = bus_alloc_resources(dev, res_spec, sc->res); 224 if (ret != 0) { 225 device_printf(dev, "could not allocate resources\n"); 226 mtx_destroy(&sc->mutex); 227 return (ENXIO); 228 } 229 230 switch (sc->rtc_type) { 231 case RTC_A38X: 232 mv_rtc_configure_bus_a38x(sc); 233 break; 234 case RTC_A8K: 235 mv_rtc_configure_bus_a8k(sc); 236 break; 237 default: 238 panic("Unknown RTC type: %d", sc->rtc_type); 239 } 240 clock_register(dev, RTC_RES_US); 241 242 return (0); 243 } 244 245 static int 246 mv_rtc_detach(device_t dev) 247 { 248 struct mv_rtc_softc *sc; 249 250 sc = device_get_softc(dev); 251 252 mtx_destroy(&sc->mutex); 253 254 bus_release_resources(dev, res_spec, sc->res); 255 256 return (0); 257 } 258 259 static int 260 mv_rtc_gettime(device_t dev, struct timespec *ts) 261 { 262 struct mv_rtc_softc *sc; 263 uint32_t val, val_check; 264 265 sc = device_get_softc(dev); 266 267 MV_RTC_LOCK(sc); 268 /* 269 * According to HW Errata, if more than one second is detected 270 * between two time reads, then at least one of the reads gave 271 * an invalid value. 272 */ 273 do { 274 val = mv_rtc_reg_read(sc, RTC_TIME); 275 DELAY(100); 276 val_check = mv_rtc_reg_read(sc, RTC_TIME); 277 } while ((val_check - val) > 1); 278 279 MV_RTC_UNLOCK(sc); 280 281 ts->tv_sec = val_check; 282 /* RTC resolution is 1 sec */ 283 ts->tv_nsec = 0; 284 285 return (0); 286 } 287 288 static int 289 mv_rtc_settime(device_t dev, struct timespec *ts) 290 { 291 struct mv_rtc_softc *sc; 292 293 sc = device_get_softc(dev); 294 295 /* RTC resolution is 1 sec */ 296 if (ts->tv_nsec >= HALF_OF_SEC_NS) 297 ts->tv_sec++; 298 ts->tv_nsec = 0; 299 300 MV_RTC_LOCK(sc); 301 302 if ((mv_rtc_reg_read(sc, RTC_CLOCK_CORR) & RTC_NOMINAL_TIMING_MASK) != 303 RTC_NOMINAL_TIMING) { 304 /* RTC was not resetted yet */ 305 mv_rtc_reset(dev); 306 } 307 308 /* 309 * According to errata FE-3124064, Write to RTC TIME register 310 * may fail. As a workaround, before writing to RTC TIME register, 311 * issue a dummy write of 0x0 twice to RTC Status register. 312 */ 313 mv_rtc_reg_write(sc, RTC_STATUS, 0x0); 314 mv_rtc_reg_write(sc, RTC_STATUS, 0x0); 315 mv_rtc_reg_write(sc, RTC_TIME, ts->tv_sec); 316 MV_RTC_UNLOCK(sc); 317 318 return (0); 319 } 320 321 static inline uint32_t 322 mv_rtc_reg_read(struct mv_rtc_softc *sc, bus_size_t off) 323 { 324 325 return (bus_read_4(sc->res[RTC_RES], off)); 326 } 327 328 /* 329 * According to the datasheet, the OS should wait 5us after every 330 * register write to the RTC hard macro so that the required update 331 * can occur without holding off the system bus 332 */ 333 static inline int 334 mv_rtc_reg_write(struct mv_rtc_softc *sc, bus_size_t off, uint32_t val) 335 { 336 337 bus_write_4(sc->res[RTC_RES], off, val); 338 DELAY(5); 339 340 return (0); 341 } 342 343 static inline void 344 mv_rtc_configure_bus_a38x(struct mv_rtc_softc *sc) 345 { 346 int val; 347 348 val = bus_read_4(sc->res[RTC_SOC_RES], A38X_RTC_BRIDGE_TIMING_CTRL); 349 val &= ~(A38X_RTC_WRCLK_PERIOD_MASK | A38X_RTC_READ_OUTPUT_DELAY_MASK); 350 val |= A38X_RTC_WRCLK_PERIOD_MAX << A38X_RTC_WRCLK_PERIOD_SHIFT; 351 val |= A38X_RTC_READ_OUTPUT_DELAY_MAX << A38X_RTC_READ_OUTPUT_DELAY_SHIFT; 352 bus_write_4(sc->res[RTC_SOC_RES], A38X_RTC_BRIDGE_TIMING_CTRL, val); 353 } 354 355 static inline void 356 mv_rtc_configure_bus_a8k(struct mv_rtc_softc *sc) 357 { 358 int val; 359 360 val = bus_read_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL0); 361 val &= ~(A8K_RTC_WRCLK_PERIOD_MASK | A8K_RTC_WRCLK_SETUP_MASK); 362 val |= A8K_RTC_WRCLK_PERIOD_VAL << A8K_RTC_WRCLK_PERIOD_SHIFT; 363 val |= A8K_RTC_WRCLK_SETUP_VAL << A8K_RTC_WRCLK_SETUP_SHIFT; 364 bus_write_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL1, val); 365 366 val = bus_read_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL0); 367 val &= ~A8K_RTC_READ_OUTPUT_DELAY_MASK; 368 val |= A8K_RTC_READ_OUTPUT_DELAY_VAL << A8K_RTC_READ_OUTPUT_DELAY_SHIFT; 369 bus_write_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL1, val); 370 } 371