1 /*- 2 * Copyright (c) 2015 Semihalf. 3 * Copyright (c) 2015 Stormshield. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/bus.h> 30 #include <sys/lock.h> 31 #include <sys/time.h> 32 #include <sys/proc.h> 33 #include <sys/conf.h> 34 #include <sys/rman.h> 35 #include <sys/clock.h> 36 #include <sys/systm.h> 37 #include <sys/mutex.h> 38 #include <sys/types.h> 39 #include <sys/kernel.h> 40 #include <sys/module.h> 41 #include <sys/resource.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 46 #include <dev/ofw/ofw_bus.h> 47 #include <dev/ofw/ofw_bus_subr.h> 48 49 #include "clock_if.h" 50 51 #define RTC_RES_US 1000000 52 #define HALF_OF_SEC_NS 500000000 53 54 #define RTC_STATUS 0x0 55 #define RTC_TIME 0xC 56 #define RTC_TEST_CONFIG 0x1C 57 #define RTC_IRQ_1_CONFIG 0x4 58 #define RTC_IRQ_2_CONFIG 0x8 59 #define RTC_ALARM_1 0x10 60 #define RTC_ALARM_2 0x14 61 #define RTC_CLOCK_CORR 0x18 62 63 #define RTC_NOMINAL_TIMING 0x2000 64 #define RTC_NOMINAL_TIMING_MASK 0x7fff 65 66 #define RTC_STATUS_ALARM1_MASK 0x1 67 #define RTC_STATUS_ALARM2_MASK 0x2 68 69 #define MV_RTC_LOCK(sc) mtx_lock_spin(&(sc)->mutex) 70 #define MV_RTC_UNLOCK(sc) mtx_unlock_spin(&(sc)->mutex) 71 72 #define A38X_RTC_BRIDGE_TIMING_CTRL 0x0 73 #define A38X_RTC_WRCLK_PERIOD_SHIFT 0 74 #define A38X_RTC_WRCLK_PERIOD_MASK 0x00000003FF 75 #define A38X_RTC_WRCLK_PERIOD_MAX 0x3FF 76 #define A38X_RTC_READ_OUTPUT_DELAY_SHIFT 26 77 #define A38X_RTC_READ_OUTPUT_DELAY_MASK 0x007C000000 78 #define A38X_RTC_READ_OUTPUT_DELAY_MAX 0x1F 79 80 #define A8K_RTC_BRIDGE_TIMING_CTRL0 0x0 81 #define A8K_RTC_WRCLK_PERIOD_SHIFT 0 82 #define A8K_RTC_WRCLK_PERIOD_MASK 0x000000FFFF 83 #define A8K_RTC_WRCLK_PERIOD_VAL 0x3FF 84 #define A8K_RTC_WRCLK_SETUP_SHIFT 16 85 #define A8K_RTC_WRCLK_SETUP_MASK 0x00FFFF0000 86 #define A8K_RTC_WRCLK_SETUP_VAL 29 87 #define A8K_RTC_BRIDGE_TIMING_CTRL1 0x4 88 #define A8K_RTC_READ_OUTPUT_DELAY_SHIFT 0 89 #define A8K_RTC_READ_OUTPUT_DELAY_MASK 0x000000FFFF 90 #define A8K_RTC_READ_OUTPUT_DELAY_VAL 0x3F 91 92 #define RTC_RES 0 93 #define RTC_SOC_RES 1 94 95 static struct resource_spec res_spec[] = { 96 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 97 { SYS_RES_MEMORY, 1, RF_ACTIVE }, 98 { -1, 0 } 99 }; 100 101 struct mv_rtc_softc { 102 device_t dev; 103 struct resource *res[2]; 104 struct mtx mutex; 105 int rtc_type; 106 }; 107 108 static int mv_rtc_probe(device_t dev); 109 static int mv_rtc_attach(device_t dev); 110 static int mv_rtc_detach(device_t dev); 111 112 static int mv_rtc_gettime(device_t dev, struct timespec *ts); 113 static int mv_rtc_settime(device_t dev, struct timespec *ts); 114 115 static inline uint32_t mv_rtc_reg_read(struct mv_rtc_softc *sc, 116 bus_size_t off); 117 static inline int mv_rtc_reg_write(struct mv_rtc_softc *sc, bus_size_t off, 118 uint32_t val); 119 static inline void mv_rtc_configure_bus_a38x(struct mv_rtc_softc *sc); 120 static inline void mv_rtc_configure_bus_a8k(struct mv_rtc_softc *sc); 121 122 static device_method_t mv_rtc_methods[] = { 123 DEVMETHOD(device_probe, mv_rtc_probe), 124 DEVMETHOD(device_attach, mv_rtc_attach), 125 DEVMETHOD(device_detach, mv_rtc_detach), 126 127 DEVMETHOD(clock_gettime, mv_rtc_gettime), 128 DEVMETHOD(clock_settime, mv_rtc_settime), 129 130 { 0, 0 }, 131 }; 132 133 static driver_t mv_rtc_driver = { 134 "rtc", 135 mv_rtc_methods, 136 sizeof(struct mv_rtc_softc), 137 }; 138 139 #define RTC_A38X 1 140 #define RTC_A8K 2 141 142 static struct ofw_compat_data mv_rtc_compat[] = { 143 {"marvell,armada-380-rtc", RTC_A38X}, 144 {"marvell,armada-8k-rtc", RTC_A8K}, 145 {NULL, 0}, 146 }; 147 148 DRIVER_MODULE(a38x_rtc, simplebus, mv_rtc_driver, 0, 0); 149 150 static void 151 mv_rtc_reset(device_t dev) 152 { 153 struct mv_rtc_softc *sc; 154 155 sc = device_get_softc(dev); 156 157 /* Reset Test register */ 158 mv_rtc_reg_write(sc, RTC_TEST_CONFIG, 0); 159 DELAY(500000); 160 161 /* Reset Time register */ 162 mv_rtc_reg_write(sc, RTC_TIME, 0); 163 DELAY(62); 164 165 /* Reset Status register */ 166 mv_rtc_reg_write(sc, RTC_STATUS, (RTC_STATUS_ALARM1_MASK | RTC_STATUS_ALARM2_MASK)); 167 DELAY(62); 168 169 /* Turn off Int1 and Int2 sources & clear the Alarm count */ 170 mv_rtc_reg_write(sc, RTC_IRQ_1_CONFIG, 0); 171 mv_rtc_reg_write(sc, RTC_IRQ_2_CONFIG, 0); 172 mv_rtc_reg_write(sc, RTC_ALARM_1, 0); 173 mv_rtc_reg_write(sc, RTC_ALARM_2, 0); 174 175 /* Setup nominal register access timing */ 176 mv_rtc_reg_write(sc, RTC_CLOCK_CORR, RTC_NOMINAL_TIMING); 177 178 /* Reset Time register */ 179 mv_rtc_reg_write(sc, RTC_TIME, 0); 180 DELAY(10); 181 182 /* Reset Status register */ 183 mv_rtc_reg_write(sc, RTC_STATUS, (RTC_STATUS_ALARM1_MASK | RTC_STATUS_ALARM2_MASK)); 184 DELAY(50); 185 } 186 187 static int 188 mv_rtc_probe(device_t dev) 189 { 190 191 if (!ofw_bus_status_okay(dev)) 192 return (ENXIO); 193 194 if (!ofw_bus_search_compatible(dev, mv_rtc_compat)->ocd_data) 195 return (ENXIO); 196 197 device_set_desc(dev, "Marvell Integrated RTC"); 198 199 return (BUS_PROBE_DEFAULT); 200 } 201 202 static int 203 mv_rtc_attach(device_t dev) 204 { 205 struct mv_rtc_softc *sc; 206 int ret; 207 208 sc = device_get_softc(dev); 209 sc->dev = dev; 210 sc->rtc_type = ofw_bus_search_compatible(dev, mv_rtc_compat)->ocd_data; 211 212 mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN); 213 214 ret = bus_alloc_resources(dev, res_spec, sc->res); 215 if (ret != 0) { 216 device_printf(dev, "could not allocate resources\n"); 217 mtx_destroy(&sc->mutex); 218 return (ENXIO); 219 } 220 221 switch (sc->rtc_type) { 222 case RTC_A38X: 223 mv_rtc_configure_bus_a38x(sc); 224 break; 225 case RTC_A8K: 226 mv_rtc_configure_bus_a8k(sc); 227 break; 228 default: 229 panic("Unknown RTC type: %d", sc->rtc_type); 230 } 231 clock_register(dev, RTC_RES_US); 232 233 return (0); 234 } 235 236 static int 237 mv_rtc_detach(device_t dev) 238 { 239 struct mv_rtc_softc *sc; 240 241 sc = device_get_softc(dev); 242 243 mtx_destroy(&sc->mutex); 244 245 bus_release_resources(dev, res_spec, sc->res); 246 247 return (0); 248 } 249 250 static int 251 mv_rtc_gettime(device_t dev, struct timespec *ts) 252 { 253 struct mv_rtc_softc *sc; 254 uint32_t val, val_check; 255 256 sc = device_get_softc(dev); 257 258 MV_RTC_LOCK(sc); 259 /* 260 * According to HW Errata, if more than one second is detected 261 * between two time reads, then at least one of the reads gave 262 * an invalid value. 263 */ 264 do { 265 val = mv_rtc_reg_read(sc, RTC_TIME); 266 DELAY(100); 267 val_check = mv_rtc_reg_read(sc, RTC_TIME); 268 } while ((val_check - val) > 1); 269 270 MV_RTC_UNLOCK(sc); 271 272 ts->tv_sec = val_check; 273 /* RTC resolution is 1 sec */ 274 ts->tv_nsec = 0; 275 276 return (0); 277 } 278 279 static int 280 mv_rtc_settime(device_t dev, struct timespec *ts) 281 { 282 struct mv_rtc_softc *sc; 283 284 sc = device_get_softc(dev); 285 286 /* RTC resolution is 1 sec */ 287 if (ts->tv_nsec >= HALF_OF_SEC_NS) 288 ts->tv_sec++; 289 ts->tv_nsec = 0; 290 291 MV_RTC_LOCK(sc); 292 293 if ((mv_rtc_reg_read(sc, RTC_CLOCK_CORR) & RTC_NOMINAL_TIMING_MASK) != 294 RTC_NOMINAL_TIMING) { 295 /* RTC was not resetted yet */ 296 mv_rtc_reset(dev); 297 } 298 299 /* 300 * According to errata FE-3124064, Write to RTC TIME register 301 * may fail. As a workaround, before writing to RTC TIME register, 302 * issue a dummy write of 0x0 twice to RTC Status register. 303 */ 304 mv_rtc_reg_write(sc, RTC_STATUS, 0x0); 305 mv_rtc_reg_write(sc, RTC_STATUS, 0x0); 306 mv_rtc_reg_write(sc, RTC_TIME, ts->tv_sec); 307 MV_RTC_UNLOCK(sc); 308 309 return (0); 310 } 311 312 static inline uint32_t 313 mv_rtc_reg_read(struct mv_rtc_softc *sc, bus_size_t off) 314 { 315 316 return (bus_read_4(sc->res[RTC_RES], off)); 317 } 318 319 /* 320 * According to the datasheet, the OS should wait 5us after every 321 * register write to the RTC hard macro so that the required update 322 * can occur without holding off the system bus 323 */ 324 static inline int 325 mv_rtc_reg_write(struct mv_rtc_softc *sc, bus_size_t off, uint32_t val) 326 { 327 328 bus_write_4(sc->res[RTC_RES], off, val); 329 DELAY(5); 330 331 return (0); 332 } 333 334 static inline void 335 mv_rtc_configure_bus_a38x(struct mv_rtc_softc *sc) 336 { 337 int val; 338 339 val = bus_read_4(sc->res[RTC_SOC_RES], A38X_RTC_BRIDGE_TIMING_CTRL); 340 val &= ~(A38X_RTC_WRCLK_PERIOD_MASK | A38X_RTC_READ_OUTPUT_DELAY_MASK); 341 val |= A38X_RTC_WRCLK_PERIOD_MAX << A38X_RTC_WRCLK_PERIOD_SHIFT; 342 val |= A38X_RTC_READ_OUTPUT_DELAY_MAX << A38X_RTC_READ_OUTPUT_DELAY_SHIFT; 343 bus_write_4(sc->res[RTC_SOC_RES], A38X_RTC_BRIDGE_TIMING_CTRL, val); 344 } 345 346 static inline void 347 mv_rtc_configure_bus_a8k(struct mv_rtc_softc *sc) 348 { 349 int val; 350 351 val = bus_read_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL0); 352 val &= ~(A8K_RTC_WRCLK_PERIOD_MASK | A8K_RTC_WRCLK_SETUP_MASK); 353 val |= A8K_RTC_WRCLK_PERIOD_VAL << A8K_RTC_WRCLK_PERIOD_SHIFT; 354 val |= A8K_RTC_WRCLK_SETUP_VAL << A8K_RTC_WRCLK_SETUP_SHIFT; 355 bus_write_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL1, val); 356 357 val = bus_read_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL0); 358 val &= ~A8K_RTC_READ_OUTPUT_DELAY_MASK; 359 val |= A8K_RTC_READ_OUTPUT_DELAY_VAL << A8K_RTC_READ_OUTPUT_DELAY_SHIFT; 360 bus_write_4(sc->res[RTC_SOC_RES], A8K_RTC_BRIDGE_TIMING_CTRL1, val); 361 } 362