xref: /freebsd/sys/arm/mv/armada38x/armada38x_mp.c (revision 7fdf597e96a02165cfe22ff357b857d5fa15ed8a)
1 /*-
2  * Copyright (c) 2015 Semihalf.
3  * Copyright (c) 2015 Stormshield.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/bus.h>
31 #include <sys/smp.h>
32 
33 #include <machine/smp.h>
34 #include <machine/fdt.h>
35 #include <machine/intr.h>
36 #include <machine/platformvar.h>
37 
38 #include <dev/ofw/ofw_bus.h>
39 #include <dev/ofw/ofw_bus_subr.h>
40 
41 #include <arm/mv/mvreg.h>
42 
43 #include "pmsu.h"
44 
45 static int cpu_reset_deassert(void);
46 void mv_a38x_platform_mp_setmaxid(platform_t plate);
47 void mv_a38x_platform_mp_start_ap(platform_t plate);
48 
49 static int
50 cpu_reset_deassert(void)
51 {
52 	bus_space_handle_t vaddr;
53 	uint32_t reg;
54 	int rv;
55 
56 	rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_CPU_RESET_BASE,
57 	    MV_CPU_RESET_REGS_LEN, 0, &vaddr);
58 	if (rv != 0)
59 		return (rv);
60 
61 	/* CPU1 is held at reset by default - clear assert bit to release it */
62 	reg = bus_space_read_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1));
63 	reg &= ~CPU_RESET_ASSERT;
64 
65 	bus_space_write_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1), reg);
66 
67 	bus_space_unmap(fdtbus_bs_tag, vaddr, MV_CPU_RESET_REGS_LEN);
68 
69 	return (0);
70 }
71 
72 static int
73 platform_cnt_cpus(void)
74 {
75 	bus_space_handle_t vaddr_scu;
76 	phandle_t cpus_node, child;
77 	char device_type[16];
78 	int fdt_cpu_count = 0;
79 	int reg_cpu_count = 0;
80 	uint32_t val;
81 	int rv;
82 
83 	cpus_node = OF_finddevice("/cpus");
84 	if (cpus_node == -1) {
85 		/* Default is one core */
86 		mp_ncpus = 1;
87 		return (0);
88 	}
89 
90 	/* Get number of 'cpu' nodes from FDT */
91 	for (child = OF_child(cpus_node); child != 0; child = OF_peer(child)) {
92 		/* Check if child is a CPU */
93 		memset(device_type, 0, sizeof(device_type));
94 		rv = OF_getprop(child, "device_type", device_type,
95 		    sizeof(device_type) - 1);
96 		if (rv < 0)
97 			continue;
98 		if (strcmp(device_type, "cpu") != 0)
99 			continue;
100 
101 		fdt_cpu_count++;
102 	}
103 
104 	/* Get number of CPU cores from SCU register to cross-check with FDT */
105 	rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE,
106 	    MV_SCU_REGS_LEN, 0, &vaddr_scu);
107 	if (rv != 0) {
108 		/* Default is one core */
109 		mp_ncpus = 1;
110 		return (0);
111 	}
112 
113 	val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CONFIG);
114 	bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN);
115         reg_cpu_count = (val & SCU_CFG_REG_NCPU_MASK) + 1;
116 
117 	/* Set mp_ncpus to number of cpus in FDT unless SOC contains only one */
118 	mp_ncpus = min(reg_cpu_count, fdt_cpu_count);
119 	/* mp_ncpus must be at least 1 */
120 	mp_ncpus = max(1, mp_ncpus);
121 
122 	return (mp_ncpus);
123 }
124 
125 void
126 mv_a38x_platform_mp_setmaxid(platform_t plate)
127 {
128 
129 	/* Armada38x family supports maximum 2 cores */
130 	mp_ncpus = platform_cnt_cpus();
131 	mp_maxid = mp_ncpus - 1;
132 }
133 
134 void
135 mv_a38x_platform_mp_start_ap(platform_t plate)
136 {
137 	int rv;
138 
139 	/* Write secondary entry address to PMSU register */
140 	rv = pmsu_boot_secondary_cpu();
141 	if (rv != 0)
142 		return;
143 
144 	/* Release CPU1 from reset */
145 	cpu_reset_deassert();
146 }
147