1 /*- 2 * Copyright (c) 2015 Semihalf. 3 * Copyright (c) 2015 Stormshield. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 35 #include <machine/fdt.h> 36 37 #include <arm/mv/mvwin.h> 38 #include <arm/mv/mvreg.h> 39 #include <arm/mv/mvvar.h> 40 41 int armada38x_open_bootrom_win(void); 42 int armada38x_scu_enable(void); 43 int armada38x_win_set_iosync_barrier(void); 44 int armada38x_mbus_optimization(void); 45 46 uint32_t 47 get_tclk(void) 48 { 49 uint32_t sar; 50 51 /* 52 * On Armada38x TCLK can be configured to 250 MHz or 200 MHz. 53 * Current setting is read from Sample At Reset register. 54 */ 55 sar = (uint32_t)get_sar_value(); 56 sar = (sar & TCLK_MASK) >> TCLK_SHIFT; 57 if (sar == 0) 58 return (TCLK_250MHZ); 59 else 60 return (TCLK_200MHZ); 61 } 62 63 int 64 armada38x_win_set_iosync_barrier(void) 65 { 66 bus_space_handle_t vaddr_iowind; 67 int rv; 68 69 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE, 70 MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind); 71 if (rv != 0) 72 return (rv); 73 74 /* Set Sync Barrier flags for all Mbus internal units */ 75 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, MV_SYNC_BARRIER_CTRL, 76 MV_SYNC_BARRIER_CTRL_ALL); 77 78 bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, 79 MV_CPU_SUBSYS_REGS_LEN, BUS_SPACE_BARRIER_WRITE); 80 bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN); 81 82 return (rv); 83 } 84 85 int 86 armada38x_open_bootrom_win(void) 87 { 88 bus_space_handle_t vaddr_iowind; 89 uint32_t val; 90 int rv; 91 92 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE, 93 MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind); 94 if (rv != 0) 95 return (rv); 96 97 val = (MV_BOOTROM_WIN_SIZE & IO_WIN_SIZE_MASK) << IO_WIN_SIZE_SHIFT; 98 val |= (MBUS_BOOTROM_ATTR & IO_WIN_ATTR_MASK) << IO_WIN_ATTR_SHIFT; 99 val |= (MBUS_BOOTROM_TGT_ID & IO_WIN_TGT_MASK) << IO_WIN_TGT_SHIFT; 100 /* Enable window and Sync Barrier */ 101 val |= (0x1 & IO_WIN_SYNC_MASK) << IO_WIN_SYNC_SHIFT; 102 val |= (0x1 & IO_WIN_ENA_MASK) << IO_WIN_ENA_SHIFT; 103 104 /* Configure IO Window Control Register */ 105 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_CTRL_OFFSET, 106 val); 107 /* Configure IO Window Base Register */ 108 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_BASE_OFFSET, 109 MV_BOOTROM_MEM_ADDR); 110 111 bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_CPU_SUBSYS_REGS_LEN, 112 BUS_SPACE_BARRIER_WRITE); 113 bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN); 114 115 return (rv); 116 } 117 118 int 119 armada38x_mbus_optimization(void) 120 { 121 bus_space_handle_t vaddr_iowind; 122 int rv; 123 124 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_CTRL_BASE, 125 MV_MBUS_CTRL_REGS_LEN, 0, &vaddr_iowind); 126 if (rv != 0) 127 return (rv); 128 129 /* 130 * MBUS Units Priority Control Register - Prioritize XOR, 131 * PCIe and GbEs (ID=4,6,3,7,8) DRAM access 132 * GbE is High and others are Medium. 133 */ 134 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0, 0x19180); 135 136 /* 137 * Fabric Units Priority Control Register - 138 * Prioritize CPUs requests. 139 */ 140 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x4, 0x3000A); 141 142 /* 143 * MBUS Units Prefetch Control Register - 144 * Pre-fetch enable for all IO masters. 145 */ 146 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x8, 0xFFFF); 147 148 /* 149 * Fabric Units Prefetch Control Register - 150 * Enable the CPUs Instruction and Data prefetch. 151 */ 152 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0xc, 0x303); 153 154 bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_MBUS_CTRL_REGS_LEN, 155 BUS_SPACE_BARRIER_WRITE); 156 157 bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_MBUS_CTRL_REGS_LEN); 158 159 return (rv); 160 } 161 162 int 163 armada38x_scu_enable(void) 164 { 165 bus_space_handle_t vaddr_scu; 166 int rv; 167 uint32_t val; 168 169 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE, 170 MV_SCU_REGS_LEN, 0, &vaddr_scu); 171 if (rv != 0) 172 return (rv); 173 174 /* Enable SCU */ 175 val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CTRL); 176 if (!(val & MV_SCU_ENABLE)) { 177 /* Enable SCU Speculative linefills to L2 */ 178 val |= MV_SCU_SL_L2_ENABLE; 179 180 bus_space_write_4(fdtbus_bs_tag, vaddr_scu, 0, 181 val | MV_SCU_ENABLE); 182 } 183 184 bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN); 185 return (0); 186 } 187