1 /*- 2 * Copyright (c) 2015 Semihalf. 3 * Copyright (c) 2015 Stormshield. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/param.h> 30 #include <sys/sysctl.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 34 #include <machine/fdt.h> 35 36 #include <arm/mv/mvwin.h> 37 #include <arm/mv/mvreg.h> 38 #include <arm/mv/mvvar.h> 39 40 int armada38x_open_bootrom_win(void); 41 int armada38x_scu_enable(void); 42 int armada38x_win_set_iosync_barrier(void); 43 int armada38x_mbus_optimization(void); 44 static uint64_t get_sar_value_armada38x(void); 45 46 static int hw_clockrate; 47 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 48 &hw_clockrate, 0, "CPU instruction clock rate"); 49 50 static uint64_t 51 get_sar_value_armada38x(void) 52 { 53 uint32_t sar_low, sar_high; 54 55 sar_high = 0; 56 sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, 57 SAMPLE_AT_RESET_ARMADA38X); 58 return (((uint64_t)sar_high << 32) | sar_low); 59 } 60 61 uint32_t 62 get_tclk_armada38x(void) 63 { 64 uint32_t sar; 65 66 /* 67 * On Armada38x TCLK can be configured to 250 MHz or 200 MHz. 68 * Current setting is read from Sample At Reset register. 69 */ 70 sar = (uint32_t)get_sar_value_armada38x(); 71 sar = (sar & TCLK_MASK_ARMADA38X) >> TCLK_SHIFT_ARMADA38X; 72 if (sar == 0) 73 return (TCLK_250MHZ); 74 else 75 return (TCLK_200MHZ); 76 } 77 78 uint32_t 79 get_cpu_freq_armada38x(void) 80 { 81 uint32_t sar; 82 83 static const uint32_t cpu_frequencies[] = { 84 0, 0, 0, 0, 85 1066, 0, 0, 0, 86 1332, 0, 0, 0, 87 1600, 0, 0, 0, 88 1866, 0, 0, 2000 89 }; 90 91 sar = (uint32_t)get_sar_value_armada38x(); 92 sar = (sar & A38X_CPU_DDR_CLK_MASK) >> A38X_CPU_DDR_CLK_SHIFT; 93 if (sar >= nitems(cpu_frequencies)) 94 return (0); 95 96 hw_clockrate = cpu_frequencies[sar]; 97 98 return (hw_clockrate * 1000 * 1000); 99 } 100 101 int 102 armada38x_win_set_iosync_barrier(void) 103 { 104 bus_space_handle_t vaddr_iowind; 105 int rv; 106 107 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE, 108 MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind); 109 if (rv != 0) 110 return (rv); 111 112 /* Set Sync Barrier flags for all Mbus internal units */ 113 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, MV_SYNC_BARRIER_CTRL, 114 MV_SYNC_BARRIER_CTRL_ALL); 115 116 bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, 117 MV_CPU_SUBSYS_REGS_LEN, BUS_SPACE_BARRIER_WRITE); 118 bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN); 119 120 return (rv); 121 } 122 123 int 124 armada38x_open_bootrom_win(void) 125 { 126 bus_space_handle_t vaddr_iowind; 127 uint32_t val; 128 int rv; 129 130 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE, 131 MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind); 132 if (rv != 0) 133 return (rv); 134 135 val = (MV_BOOTROM_WIN_SIZE & IO_WIN_SIZE_MASK) << IO_WIN_SIZE_SHIFT; 136 val |= (MBUS_BOOTROM_ATTR & IO_WIN_ATTR_MASK) << IO_WIN_ATTR_SHIFT; 137 val |= (MBUS_BOOTROM_TGT_ID & IO_WIN_TGT_MASK) << IO_WIN_TGT_SHIFT; 138 /* Enable window and Sync Barrier */ 139 val |= (0x1 & IO_WIN_SYNC_MASK) << IO_WIN_SYNC_SHIFT; 140 val |= (0x1 & IO_WIN_ENA_MASK) << IO_WIN_ENA_SHIFT; 141 142 /* Configure IO Window Control Register */ 143 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_CTRL_OFFSET, 144 val); 145 /* Configure IO Window Base Register */ 146 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_BASE_OFFSET, 147 MV_BOOTROM_MEM_ADDR); 148 149 bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_CPU_SUBSYS_REGS_LEN, 150 BUS_SPACE_BARRIER_WRITE); 151 bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN); 152 153 return (rv); 154 } 155 156 int 157 armada38x_mbus_optimization(void) 158 { 159 bus_space_handle_t vaddr_iowind; 160 int rv; 161 162 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_CTRL_BASE, 163 MV_MBUS_CTRL_REGS_LEN, 0, &vaddr_iowind); 164 if (rv != 0) 165 return (rv); 166 167 /* 168 * MBUS Units Priority Control Register - Prioritize XOR, 169 * PCIe and GbEs (ID=4,6,3,7,8) DRAM access 170 * GbE is High and others are Medium. 171 */ 172 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0, 0x19180); 173 174 /* 175 * Fabric Units Priority Control Register - 176 * Prioritize CPUs requests. 177 */ 178 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x4, 0x3000A); 179 180 /* 181 * MBUS Units Prefetch Control Register - 182 * Pre-fetch enable for all IO masters. 183 */ 184 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x8, 0xFFFF); 185 186 /* 187 * Fabric Units Prefetch Control Register - 188 * Enable the CPUs Instruction and Data prefetch. 189 */ 190 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0xc, 0x303); 191 192 bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_MBUS_CTRL_REGS_LEN, 193 BUS_SPACE_BARRIER_WRITE); 194 195 bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_MBUS_CTRL_REGS_LEN); 196 197 return (rv); 198 } 199 200 int 201 armada38x_scu_enable(void) 202 { 203 bus_space_handle_t vaddr_scu; 204 int rv; 205 uint32_t val; 206 207 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE, 208 MV_SCU_REGS_LEN, 0, &vaddr_scu); 209 if (rv != 0) 210 return (rv); 211 212 /* Enable SCU */ 213 val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CTRL); 214 if (!(val & MV_SCU_ENABLE)) { 215 /* Enable SCU Speculative linefills to L2 */ 216 val |= MV_SCU_SL_L2_ENABLE; 217 218 bus_space_write_4(fdtbus_bs_tag, vaddr_scu, 0, 219 val | MV_SCU_ENABLE); 220 } 221 222 bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN); 223 return (0); 224 } 225