1 /*- 2 * Copyright (c) 2015 Semihalf. 3 * Copyright (c) 2015 Stormshield. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/param.h> 32 #include <sys/sysctl.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 36 #include <machine/fdt.h> 37 38 #include <arm/mv/mvwin.h> 39 #include <arm/mv/mvreg.h> 40 #include <arm/mv/mvvar.h> 41 42 int armada38x_open_bootrom_win(void); 43 int armada38x_scu_enable(void); 44 int armada38x_win_set_iosync_barrier(void); 45 int armada38x_mbus_optimization(void); 46 47 static int hw_clockrate; 48 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 49 &hw_clockrate, 0, "CPU instruction clock rate"); 50 51 uint32_t 52 get_tclk(void) 53 { 54 uint32_t sar; 55 56 /* 57 * On Armada38x TCLK can be configured to 250 MHz or 200 MHz. 58 * Current setting is read from Sample At Reset register. 59 */ 60 sar = (uint32_t)get_sar_value(); 61 sar = (sar & TCLK_MASK) >> TCLK_SHIFT; 62 if (sar == 0) 63 return (TCLK_250MHZ); 64 else 65 return (TCLK_200MHZ); 66 } 67 68 uint32_t 69 get_cpu_freq(void) 70 { 71 uint32_t sar; 72 73 static const uint32_t cpu_frequencies[] = { 74 0, 0, 0, 0, 75 1066, 0, 0, 0, 76 1332, 0, 0, 0, 77 1600, 0, 0, 0, 78 1866, 0, 0, 2000 79 }; 80 81 sar = (uint32_t)get_sar_value(); 82 sar = (sar & A38X_CPU_DDR_CLK_MASK) >> A38X_CPU_DDR_CLK_SHIFT; 83 if (sar >= nitems(cpu_frequencies)) 84 return (0); 85 86 hw_clockrate = cpu_frequencies[sar]; 87 88 return (hw_clockrate * 1000 * 1000); 89 } 90 91 int 92 armada38x_win_set_iosync_barrier(void) 93 { 94 bus_space_handle_t vaddr_iowind; 95 int rv; 96 97 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE, 98 MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind); 99 if (rv != 0) 100 return (rv); 101 102 /* Set Sync Barrier flags for all Mbus internal units */ 103 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, MV_SYNC_BARRIER_CTRL, 104 MV_SYNC_BARRIER_CTRL_ALL); 105 106 bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, 107 MV_CPU_SUBSYS_REGS_LEN, BUS_SPACE_BARRIER_WRITE); 108 bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN); 109 110 return (rv); 111 } 112 113 int 114 armada38x_open_bootrom_win(void) 115 { 116 bus_space_handle_t vaddr_iowind; 117 uint32_t val; 118 int rv; 119 120 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE, 121 MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind); 122 if (rv != 0) 123 return (rv); 124 125 val = (MV_BOOTROM_WIN_SIZE & IO_WIN_SIZE_MASK) << IO_WIN_SIZE_SHIFT; 126 val |= (MBUS_BOOTROM_ATTR & IO_WIN_ATTR_MASK) << IO_WIN_ATTR_SHIFT; 127 val |= (MBUS_BOOTROM_TGT_ID & IO_WIN_TGT_MASK) << IO_WIN_TGT_SHIFT; 128 /* Enable window and Sync Barrier */ 129 val |= (0x1 & IO_WIN_SYNC_MASK) << IO_WIN_SYNC_SHIFT; 130 val |= (0x1 & IO_WIN_ENA_MASK) << IO_WIN_ENA_SHIFT; 131 132 /* Configure IO Window Control Register */ 133 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_CTRL_OFFSET, 134 val); 135 /* Configure IO Window Base Register */ 136 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_BASE_OFFSET, 137 MV_BOOTROM_MEM_ADDR); 138 139 bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_CPU_SUBSYS_REGS_LEN, 140 BUS_SPACE_BARRIER_WRITE); 141 bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN); 142 143 return (rv); 144 } 145 146 int 147 armada38x_mbus_optimization(void) 148 { 149 bus_space_handle_t vaddr_iowind; 150 int rv; 151 152 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_CTRL_BASE, 153 MV_MBUS_CTRL_REGS_LEN, 0, &vaddr_iowind); 154 if (rv != 0) 155 return (rv); 156 157 /* 158 * MBUS Units Priority Control Register - Prioritize XOR, 159 * PCIe and GbEs (ID=4,6,3,7,8) DRAM access 160 * GbE is High and others are Medium. 161 */ 162 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0, 0x19180); 163 164 /* 165 * Fabric Units Priority Control Register - 166 * Prioritize CPUs requests. 167 */ 168 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x4, 0x3000A); 169 170 /* 171 * MBUS Units Prefetch Control Register - 172 * Pre-fetch enable for all IO masters. 173 */ 174 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x8, 0xFFFF); 175 176 /* 177 * Fabric Units Prefetch Control Register - 178 * Enable the CPUs Instruction and Data prefetch. 179 */ 180 bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0xc, 0x303); 181 182 bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_MBUS_CTRL_REGS_LEN, 183 BUS_SPACE_BARRIER_WRITE); 184 185 bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_MBUS_CTRL_REGS_LEN); 186 187 return (rv); 188 } 189 190 int 191 armada38x_scu_enable(void) 192 { 193 bus_space_handle_t vaddr_scu; 194 int rv; 195 uint32_t val; 196 197 rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE, 198 MV_SCU_REGS_LEN, 0, &vaddr_scu); 199 if (rv != 0) 200 return (rv); 201 202 /* Enable SCU */ 203 val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CTRL); 204 if (!(val & MV_SCU_ENABLE)) { 205 /* Enable SCU Speculative linefills to L2 */ 206 val |= MV_SCU_SL_L2_ENABLE; 207 208 bus_space_write_4(fdtbus_bs_tag, vaddr_scu, 0, 209 val | MV_SCU_ENABLE); 210 } 211 212 bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN); 213 return (0); 214 } 215