1 /*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 4 * All rights reserved. 5 * 6 * Adapted to Marvell SoC by Semihalf. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1 29 */ 30 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/eventhandler.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/malloc.h> 38 #include <sys/rman.h> 39 #include <sys/kdb.h> 40 #include <sys/timeet.h> 41 #include <sys/timetc.h> 42 #include <sys/watchdog.h> 43 #include <machine/bus.h> 44 #include <machine/cpu.h> 45 46 #include <arm/mv/mvreg.h> 47 #include <arm/mv/mvvar.h> 48 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #define INITIAL_TIMECOUNTER (0xffffffff) 53 #define MAX_WATCHDOG_TICKS (0xffffffff) 54 #define WD_RST_OUT_EN 0x00000002 55 56 #define MV_CLOCK_SRC_ARMV7 25000000 /* Timers' 25MHz mode */ 57 58 struct mv_wdt_config { 59 uint32_t wdt_timer; 60 void (*wdt_enable)(void); 61 void (*wdt_disable)(void); 62 unsigned int wdt_clock_src; 63 }; 64 65 static void mv_wdt_enable_armv5(void); 66 static void mv_wdt_enable_armada_38x(void); 67 static void mv_wdt_enable_armada_xp(void); 68 static inline void mv_wdt_enable_armada_38x_xp_helper(void); 69 70 static void mv_wdt_disable_armv5(void); 71 static void mv_wdt_disable_armada_38x(void); 72 static void mv_wdt_disable_armada_xp(void); 73 74 static struct mv_wdt_config mv_wdt_armada_38x_config = { 75 .wdt_timer = 4, 76 .wdt_enable = &mv_wdt_enable_armada_38x, 77 .wdt_disable = &mv_wdt_disable_armada_38x, 78 .wdt_clock_src = MV_CLOCK_SRC_ARMV7, 79 }; 80 81 static struct mv_wdt_config mv_wdt_armada_xp_config = { 82 .wdt_timer = 2, 83 .wdt_enable = &mv_wdt_enable_armada_xp, 84 .wdt_disable = &mv_wdt_disable_armada_xp, 85 .wdt_clock_src = MV_CLOCK_SRC_ARMV7, 86 }; 87 88 static struct mv_wdt_config mv_wdt_armv5_config = { 89 .wdt_timer = 2, 90 .wdt_enable = &mv_wdt_enable_armv5, 91 .wdt_disable = &mv_wdt_disable_armv5, 92 .wdt_clock_src = 0, 93 }; 94 95 struct mv_wdt_softc { 96 struct resource * wdt_res; 97 struct mtx wdt_mtx; 98 struct mv_wdt_config * wdt_config; 99 }; 100 101 static struct resource_spec mv_wdt_spec[] = { 102 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 103 { -1, 0 } 104 }; 105 106 static struct ofw_compat_data mv_wdt_compat[] = { 107 {"marvell,armada-380-wdt", (uintptr_t)&mv_wdt_armada_38x_config}, 108 {"marvell,armada-xp-wdt", (uintptr_t)&mv_wdt_armada_xp_config}, 109 {"marvell,orion-wdt", (uintptr_t)&mv_wdt_armv5_config}, 110 {NULL, (uintptr_t)NULL} 111 }; 112 113 static struct mv_wdt_softc *wdt_softc = NULL; 114 int timers_initialized = 0; 115 116 static int mv_wdt_probe(device_t); 117 static int mv_wdt_attach(device_t); 118 119 static uint32_t mv_get_timer_control(void); 120 static void mv_set_timer_control(uint32_t); 121 static void mv_set_timer(uint32_t, uint32_t); 122 123 static void mv_watchdog_event(void *, unsigned int, int *); 124 125 static device_method_t mv_wdt_methods[] = { 126 DEVMETHOD(device_probe, mv_wdt_probe), 127 DEVMETHOD(device_attach, mv_wdt_attach), 128 { 0, 0 } 129 }; 130 131 static driver_t mv_wdt_driver = { 132 "wdt", 133 mv_wdt_methods, 134 sizeof(struct mv_wdt_softc), 135 }; 136 137 DRIVER_MODULE(wdt, simplebus, mv_wdt_driver, 0, 0); 138 139 static int 140 mv_wdt_probe(device_t dev) 141 { 142 143 if (!ofw_bus_status_okay(dev)) 144 return (ENXIO); 145 146 if (!ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data) 147 return (ENXIO); 148 149 device_set_desc(dev, "Marvell Watchdog Timer"); 150 return (0); 151 } 152 153 static int 154 mv_wdt_attach(device_t dev) 155 { 156 struct mv_wdt_softc *sc; 157 int error; 158 159 if (wdt_softc != NULL) 160 return (ENXIO); 161 162 sc = device_get_softc(dev); 163 wdt_softc = sc; 164 165 error = bus_alloc_resources(dev, mv_wdt_spec, &sc->wdt_res); 166 if (error) { 167 device_printf(dev, "could not allocate resources\n"); 168 return (ENXIO); 169 } 170 171 mtx_init(&sc->wdt_mtx, "watchdog", NULL, MTX_DEF); 172 173 sc->wdt_config = (struct mv_wdt_config *) 174 ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data; 175 176 if (sc->wdt_config->wdt_clock_src == 0) 177 sc->wdt_config->wdt_clock_src = get_tclk(); 178 179 if (wdt_softc->wdt_config->wdt_disable != NULL) 180 wdt_softc->wdt_config->wdt_disable(); 181 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0); 182 183 return (0); 184 } 185 186 static __inline uint32_t 187 mv_get_timer_control(void) 188 { 189 190 return (bus_read_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL)); 191 } 192 193 static __inline void 194 mv_set_timer_control(uint32_t val) 195 { 196 197 bus_write_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL, val); 198 } 199 200 static __inline void 201 mv_set_timer(uint32_t timer, uint32_t val) 202 { 203 204 bus_write_4(wdt_softc->wdt_res, CPU_TIMER0 + timer * 0x8, val); 205 } 206 static void 207 mv_wdt_enable_armv5(void) 208 { 209 uint32_t val, irq_cause, irq_mask; 210 211 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 212 irq_cause &= IRQ_TIMER_WD_CLR; 213 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 214 215 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 216 irq_mask |= IRQ_TIMER_WD_MASK; 217 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 218 219 val = read_cpu_ctrl(RSTOUTn_MASK); 220 val |= WD_RST_OUT_EN; 221 write_cpu_ctrl(RSTOUTn_MASK, val); 222 223 val = mv_get_timer_control(); 224 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO; 225 mv_set_timer_control(val); 226 } 227 228 static inline void 229 mv_wdt_enable_armada_38x_xp_helper(void) 230 { 231 uint32_t val, irq_cause; 232 233 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 234 irq_cause &= IRQ_TIMER_WD_CLR; 235 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 236 237 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 238 val |= (WD_GLOBAL_MASK | WD_CPU0_MASK); 239 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 240 241 val = read_cpu_misc(RSTOUTn_MASK_ARMV7); 242 val &= ~RSTOUTn_MASK_WD; 243 write_cpu_misc(RSTOUTn_MASK_ARMV7, val); 244 } 245 246 static void 247 mv_wdt_enable_armada_38x(void) 248 { 249 uint32_t val, irq_cause; 250 251 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 252 irq_cause &= IRQ_TIMER_WD_CLR; 253 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 254 255 mv_wdt_enable_armada_38x_xp_helper(); 256 257 val = mv_get_timer_control(); 258 val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN; 259 mv_set_timer_control(val); 260 } 261 262 static void 263 mv_wdt_enable_armada_xp(void) 264 { 265 uint32_t val, irq_cause; 266 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE_ARMADAXP); 267 irq_cause &= IRQ_TIMER_WD_CLR_ARMADAXP; 268 write_cpu_ctrl(BRIDGE_IRQ_CAUSE_ARMADAXP, irq_cause); 269 270 mv_wdt_enable_armada_38x_xp_helper(); 271 272 val = mv_get_timer_control(); 273 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN; 274 mv_set_timer_control(val); 275 } 276 277 static void 278 mv_wdt_disable_armv5(void) 279 { 280 uint32_t val, irq_cause, irq_mask; 281 282 val = mv_get_timer_control(); 283 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); 284 mv_set_timer_control(val); 285 286 val = read_cpu_ctrl(RSTOUTn_MASK); 287 val &= ~WD_RST_OUT_EN; 288 write_cpu_ctrl(RSTOUTn_MASK, val); 289 290 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 291 irq_mask &= ~(IRQ_TIMER_WD_MASK); 292 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 293 294 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 295 irq_cause &= IRQ_TIMER_WD_CLR; 296 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 297 } 298 299 static __inline void 300 mv_wdt_disable_armada_38x_xp_helper(void) 301 { 302 uint32_t val; 303 304 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 305 val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK); 306 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 307 308 val = read_cpu_misc(RSTOUTn_MASK_ARMV7); 309 val |= RSTOUTn_MASK_WD; 310 write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD); 311 } 312 313 static void 314 mv_wdt_disable_armada_38x(void) 315 { 316 uint32_t val; 317 318 val = mv_get_timer_control(); 319 val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO); 320 mv_set_timer_control(val); 321 322 mv_wdt_disable_armada_38x_xp_helper(); 323 } 324 325 static void 326 mv_wdt_disable_armada_xp(void) 327 { 328 uint32_t val; 329 330 val = mv_get_timer_control(); 331 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); 332 mv_set_timer_control(val); 333 334 mv_wdt_disable_armada_38x_xp_helper(); 335 } 336 337 /* 338 * Watchdog event handler. 339 */ 340 static void 341 mv_watchdog_event(void *arg, unsigned int cmd, int *error) 342 { 343 struct mv_wdt_softc *sc; 344 uint64_t ns; 345 uint64_t ticks; 346 347 sc = arg; 348 mtx_lock(&sc->wdt_mtx); 349 if (cmd == 0) { 350 if (wdt_softc->wdt_config->wdt_disable != NULL) 351 wdt_softc->wdt_config->wdt_disable(); 352 } else { 353 /* 354 * Watchdog timeout is in nanosecs, calculation according to 355 * watchdog(9) 356 */ 357 ns = (uint64_t)1 << (cmd & WD_INTERVAL); 358 ticks = (uint64_t)(ns * sc->wdt_config->wdt_clock_src) / 1000000000; 359 if (ticks > MAX_WATCHDOG_TICKS) { 360 if (wdt_softc->wdt_config->wdt_disable != NULL) 361 wdt_softc->wdt_config->wdt_disable(); 362 } 363 else { 364 mv_set_timer(wdt_softc->wdt_config->wdt_timer, ticks); 365 if (wdt_softc->wdt_config->wdt_enable != NULL) 366 wdt_softc->wdt_config->wdt_enable(); 367 *error = 0; 368 } 369 } 370 mtx_unlock(&sc->wdt_mtx); 371 } 372