1 /*- 2 * Copyright (c) 2006 Benno Rice. 3 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. 4 * All rights reserved. 5 * 6 * Adapted to Marvell SoC by Semihalf. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/bus.h> 37 #include <sys/eventhandler.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/malloc.h> 41 #include <sys/rman.h> 42 #include <sys/kdb.h> 43 #include <sys/timeet.h> 44 #include <sys/timetc.h> 45 #include <sys/watchdog.h> 46 #include <machine/bus.h> 47 #include <machine/cpu.h> 48 49 #include <arm/mv/mvreg.h> 50 #include <arm/mv/mvvar.h> 51 52 #include <dev/ofw/ofw_bus.h> 53 #include <dev/ofw/ofw_bus_subr.h> 54 55 #define INITIAL_TIMECOUNTER (0xffffffff) 56 #define MAX_WATCHDOG_TICKS (0xffffffff) 57 #define WD_RST_OUT_EN 0x00000002 58 59 #define MV_CLOCK_SRC_ARMV7 25000000 /* Timers' 25MHz mode */ 60 61 struct mv_wdt_config { 62 enum soc_family wdt_soc; 63 uint32_t wdt_timer; 64 void (*wdt_enable)(void); 65 void (*wdt_disable)(void); 66 unsigned int wdt_clock_src; 67 }; 68 69 static void mv_wdt_enable_armv5(void); 70 static void mv_wdt_enable_armada_38x(void); 71 static void mv_wdt_enable_armada_xp(void); 72 73 static void mv_wdt_disable_armv5(void); 74 static void mv_wdt_disable_armada_38x(void); 75 static void mv_wdt_disable_armada_xp(void); 76 77 static struct mv_wdt_config mv_wdt_armada_38x_config = { 78 .wdt_soc = MV_SOC_ARMADA_38X, 79 .wdt_timer = 4, 80 .wdt_enable = &mv_wdt_enable_armada_38x, 81 .wdt_disable = &mv_wdt_disable_armada_38x, 82 .wdt_clock_src = MV_CLOCK_SRC_ARMV7, 83 }; 84 85 static struct mv_wdt_config mv_wdt_armada_xp_config = { 86 .wdt_soc = MV_SOC_ARMADA_XP, 87 .wdt_timer = 2, 88 .wdt_enable = &mv_wdt_enable_armada_xp, 89 .wdt_disable = &mv_wdt_disable_armada_xp, 90 .wdt_clock_src = MV_CLOCK_SRC_ARMV7, 91 }; 92 93 static struct mv_wdt_config mv_wdt_armv5_config = { 94 .wdt_soc = MV_SOC_ARMV5, 95 .wdt_timer = 2, 96 .wdt_enable = &mv_wdt_enable_armv5, 97 .wdt_disable = &mv_wdt_disable_armv5, 98 .wdt_clock_src = 0, 99 }; 100 101 struct mv_wdt_softc { 102 struct resource * wdt_res; 103 struct mtx wdt_mtx; 104 struct mv_wdt_config * wdt_config; 105 }; 106 107 static struct resource_spec mv_wdt_spec[] = { 108 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 109 { -1, 0 } 110 }; 111 112 static struct ofw_compat_data mv_wdt_compat[] = { 113 {"marvell,armada-380-wdt", (uintptr_t)&mv_wdt_armada_38x_config}, 114 {"marvell,armada-xp-wdt", (uintptr_t)&mv_wdt_armada_xp_config}, 115 {"marvell,orion-wdt", (uintptr_t)&mv_wdt_armv5_config}, 116 {NULL, (uintptr_t)NULL} 117 }; 118 119 static struct mv_wdt_softc *wdt_softc = NULL; 120 int timers_initialized = 0; 121 122 static int mv_wdt_probe(device_t); 123 static int mv_wdt_attach(device_t); 124 125 static uint32_t mv_get_timer_control(void); 126 static void mv_set_timer_control(uint32_t); 127 static void mv_set_timer(uint32_t, uint32_t); 128 129 static void mv_watchdog_event(void *, unsigned int, int *); 130 131 static device_method_t mv_wdt_methods[] = { 132 DEVMETHOD(device_probe, mv_wdt_probe), 133 DEVMETHOD(device_attach, mv_wdt_attach), 134 135 { 0, 0 } 136 }; 137 138 static driver_t mv_wdt_driver = { 139 "wdt", 140 mv_wdt_methods, 141 sizeof(struct mv_wdt_softc), 142 }; 143 144 static devclass_t mv_wdt_devclass; 145 146 DRIVER_MODULE(wdt, simplebus, mv_wdt_driver, mv_wdt_devclass, 0, 0); 147 static int 148 mv_wdt_probe(device_t dev) 149 { 150 151 if (!ofw_bus_status_okay(dev)) 152 return (ENXIO); 153 154 if (!ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data) 155 return (ENXIO); 156 157 device_set_desc(dev, "Marvell Watchdog Timer"); 158 return (0); 159 } 160 161 static int 162 mv_wdt_attach(device_t dev) 163 { 164 struct mv_wdt_softc *sc; 165 int error; 166 167 if (wdt_softc != NULL) 168 return (ENXIO); 169 170 sc = device_get_softc(dev); 171 wdt_softc = sc; 172 173 error = bus_alloc_resources(dev, mv_wdt_spec, &sc->wdt_res); 174 if (error) { 175 device_printf(dev, "could not allocate resources\n"); 176 return (ENXIO); 177 } 178 179 mtx_init(&sc->wdt_mtx, "watchdog", NULL, MTX_DEF); 180 181 sc->wdt_config = (struct mv_wdt_config *) 182 ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data; 183 184 if (sc->wdt_config->wdt_clock_src == 0) 185 sc->wdt_config->wdt_clock_src = get_tclk(); 186 187 if (wdt_softc->wdt_config->wdt_disable != NULL) 188 wdt_softc->wdt_config->wdt_disable(); 189 EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0); 190 191 return (0); 192 } 193 194 static __inline uint32_t 195 mv_get_timer_control(void) 196 { 197 198 return (bus_read_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL)); 199 } 200 201 static __inline void 202 mv_set_timer_control(uint32_t val) 203 { 204 205 bus_write_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL, val); 206 } 207 208 static __inline void 209 mv_set_timer(uint32_t timer, uint32_t val) 210 { 211 212 bus_write_4(wdt_softc->wdt_res, CPU_TIMER0 + timer * 0x8, val); 213 } 214 static void 215 mv_wdt_enable_armv5(void) 216 { 217 uint32_t val, irq_cause, irq_mask; 218 219 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 220 irq_cause &= IRQ_TIMER_WD_CLR; 221 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 222 223 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 224 irq_mask |= IRQ_TIMER_WD_MASK; 225 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 226 227 val = read_cpu_ctrl(RSTOUTn_MASK); 228 val |= WD_RST_OUT_EN; 229 write_cpu_ctrl(RSTOUTn_MASK, val); 230 231 val = mv_get_timer_control(); 232 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO; 233 mv_set_timer_control(val); 234 } 235 236 static inline void 237 mv_wdt_enable_armada_38x_xp_helper() 238 { 239 uint32_t val, irq_cause; 240 241 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 242 irq_cause &= IRQ_TIMER_WD_CLR; 243 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 244 245 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 246 val |= (WD_GLOBAL_MASK | WD_CPU0_MASK); 247 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 248 249 val = read_cpu_misc(RSTOUTn_MASK_ARMV7); 250 val &= ~RSTOUTn_MASK_WD; 251 write_cpu_misc(RSTOUTn_MASK_ARMV7, val); 252 } 253 254 static void 255 mv_wdt_enable_armada_38x(void) 256 { 257 uint32_t val, irq_cause; 258 259 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 260 irq_cause &= IRQ_TIMER_WD_CLR; 261 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 262 263 mv_wdt_enable_armada_38x_xp_helper(); 264 265 val = mv_get_timer_control(); 266 val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN; 267 mv_set_timer_control(val); 268 } 269 270 static void 271 mv_wdt_enable_armada_xp(void) 272 { 273 uint32_t val, irq_cause; 274 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE_ARMADAXP); 275 irq_cause &= IRQ_TIMER_WD_CLR_ARMADAXP; 276 write_cpu_ctrl(BRIDGE_IRQ_CAUSE_ARMADAXP, irq_cause); 277 278 mv_wdt_enable_armada_38x_xp_helper(); 279 280 val = mv_get_timer_control(); 281 val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN; 282 mv_set_timer_control(val); 283 } 284 285 static void 286 mv_wdt_disable_armv5(void) 287 { 288 uint32_t val, irq_cause, irq_mask; 289 290 val = mv_get_timer_control(); 291 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); 292 mv_set_timer_control(val); 293 294 val = read_cpu_ctrl(RSTOUTn_MASK); 295 val &= ~WD_RST_OUT_EN; 296 write_cpu_ctrl(RSTOUTn_MASK, val); 297 298 irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); 299 irq_mask &= ~(IRQ_TIMER_WD_MASK); 300 write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); 301 302 irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); 303 irq_cause &= IRQ_TIMER_WD_CLR; 304 write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); 305 } 306 307 static __inline void 308 mv_wdt_disable_armada_38x_xp_helper(void) 309 { 310 uint32_t val; 311 312 val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); 313 val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK); 314 write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); 315 316 val = read_cpu_misc(RSTOUTn_MASK_ARMV7); 317 val |= RSTOUTn_MASK_WD; 318 write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD); 319 } 320 321 static void 322 mv_wdt_disable_armada_38x(void) 323 { 324 uint32_t val; 325 326 val = mv_get_timer_control(); 327 val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO); 328 mv_set_timer_control(val); 329 330 mv_wdt_disable_armada_38x_xp_helper(); 331 } 332 333 static void 334 mv_wdt_disable_armada_xp(void) 335 { 336 uint32_t val; 337 338 val = mv_get_timer_control(); 339 val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); 340 mv_set_timer_control(val); 341 342 mv_wdt_disable_armada_38x_xp_helper(); 343 } 344 345 /* 346 * Watchdog event handler. 347 */ 348 static void 349 mv_watchdog_event(void *arg, unsigned int cmd, int *error) 350 { 351 struct mv_wdt_softc *sc; 352 uint64_t ns; 353 uint64_t ticks; 354 355 sc = arg; 356 mtx_lock(&sc->wdt_mtx); 357 if (cmd == 0) { 358 if (wdt_softc->wdt_config->wdt_disable != NULL) 359 wdt_softc->wdt_config->wdt_disable(); 360 } else { 361 /* 362 * Watchdog timeout is in nanosecs, calculation according to 363 * watchdog(9) 364 */ 365 ns = (uint64_t)1 << (cmd & WD_INTERVAL); 366 ticks = (uint64_t)(ns * sc->wdt_config->wdt_clock_src) / 1000000000; 367 if (ticks > MAX_WATCHDOG_TICKS) { 368 if (wdt_softc->wdt_config->wdt_disable != NULL) 369 wdt_softc->wdt_config->wdt_disable(); 370 } 371 else { 372 mv_set_timer(wdt_softc->wdt_config->wdt_timer, ticks); 373 if (wdt_softc->wdt_config->wdt_enable != NULL) 374 wdt_softc->wdt_config->wdt_enable(); 375 *error = 0; 376 } 377 } 378 mtx_unlock(&sc->wdt_mtx); 379 } 380