xref: /freebsd/sys/arm/mv/a37x0_iic.c (revision db33c6f3ae9d1231087710068ee4ea5398aacca7)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2018, 2019 Rubicon Communications, LLC (Netgate)
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  */
28 #include <sys/cdefs.h>
29 /*
30  * Driver for Armada 37x0 i2c controller.
31  */
32 
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/lock.h>
37 #include <sys/module.h>
38 #include <sys/mutex.h>
39 #include <sys/bus.h>
40 #include <machine/resource.h>
41 #include <machine/bus.h>
42 #include <sys/rman.h>
43 #include <sys/sysctl.h>
44 
45 #include <dev/iicbus/iicbus.h>
46 #include <dev/iicbus/iiconf.h>
47 #include <dev/ofw/ofw_bus.h>
48 #include <dev/ofw/ofw_bus_subr.h>
49 
50 #include <arm/mv/a37x0_iicreg.h>
51 
52 #include "iicbus_if.h"
53 
54 struct a37x0_iic_softc {
55 	boolean_t		sc_fast_mode;
56 	bus_space_tag_t		sc_bst;
57 	bus_space_handle_t	sc_bsh;
58 	device_t		sc_dev;
59 	device_t		sc_iicbus;
60 	struct mtx		sc_mtx;
61 	struct resource		*sc_mem_res;
62 	struct resource		*sc_irq_res;
63 	void			*sc_intrhand;
64 };
65 
66 #define	A37X0_IIC_WRITE(_sc, _off, _val)			\
67     bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val)
68 #define	A37X0_IIC_READ(_sc, _off)				\
69     bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off)
70 #define	A37X0_IIC_LOCK(_sc)	mtx_lock(&(_sc)->sc_mtx)
71 #define	A37X0_IIC_UNLOCK(_sc)	mtx_unlock(&(_sc)->sc_mtx)
72 
73 static struct ofw_compat_data compat_data[] = {
74 	{ "marvell,armada-3700-i2c",	1 },
75 	{ NULL,				0 }
76 };
77 
78 #undef A37x0_IIC_DEBUG
79 
80 static void a37x0_iic_intr(void *);
81 static int a37x0_iic_detach(device_t);
82 
83 static void
84 a37x0_iic_rmw(struct a37x0_iic_softc *sc, uint32_t off, uint32_t mask,
85     uint32_t value)
86 {
87 	uint32_t reg;
88 
89 	mtx_assert(&sc->sc_mtx, MA_OWNED);
90 	reg = A37X0_IIC_READ(sc, off);
91 	reg &= ~mask;
92 	reg |= value;
93 	A37X0_IIC_WRITE(sc, off, reg);
94 }
95 
96 static int
97 a37x0_iic_wait_clear(struct a37x0_iic_softc *sc, uint32_t mask)
98 {
99 	int timeout;
100 	uint32_t status;
101 
102 	mtx_assert(&sc->sc_mtx, MA_OWNED);
103 	timeout = 1000;
104 	do {
105 		DELAY(10);
106 		status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
107 		if (--timeout == 0)
108 			return (0);
109 	} while ((status & mask) != 0);
110 
111 	return (1);
112 }
113 
114 static int
115 a37x0_iic_wait_set(struct a37x0_iic_softc *sc, uint32_t mask)
116 {
117 	int timeout;
118 	uint32_t status;
119 
120 	mtx_assert(&sc->sc_mtx, MA_OWNED);
121 	timeout = 1000;
122 	do {
123 		DELAY(10);
124 		status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
125 		if (--timeout == 0)
126 			return (0);
127 	} while ((status & mask) != mask);
128 
129 	return (1);
130 }
131 
132 #ifdef A37x0_IIC_DEBUG
133 static void
134 a37x0_iic_regdump(struct a37x0_iic_softc *sc)
135 {
136 
137 	mtx_assert(&sc->sc_mtx, MA_OWNED);
138 	printf("%s: IBMR: %#x\n", __func__, A37X0_IIC_READ(sc, A37X0_IIC_IBMR));
139 	printf("%s: ICR: %#x\n", __func__, A37X0_IIC_READ(sc, A37X0_IIC_ICR));
140 	printf("%s: ISR: %#x\n", __func__, A37X0_IIC_READ(sc, A37X0_IIC_ISR));
141 }
142 #endif
143 
144 static void
145 a37x0_iic_reset(struct a37x0_iic_softc *sc)
146 {
147 	uint32_t mode, reg;
148 
149 	mtx_assert(&sc->sc_mtx, MA_OWNED);
150 
151 	/* Disable the controller. */
152 	reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
153 	mode = reg & ICR_MODE_MASK;
154 	A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg & ~ICR_IUE);
155 	A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_UR);
156 	DELAY(100);
157 	A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg & ~ICR_IUE);
158 
159 	/* Enable the controller. */
160 	reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
161 	reg |= mode | ICR_IUE | ICR_GCD | ICR_SCLE;
162 	A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg);
163 #ifdef A37x0_IIC_DEBUG
164 	a37x0_iic_regdump(sc);
165 #endif
166 }
167 
168 static int
169 a37x0_iic_probe(device_t dev)
170 {
171 
172 	if (!ofw_bus_status_okay(dev))
173 		return (ENXIO);
174 
175 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
176 		return (ENXIO);
177 
178 	device_set_desc(dev, "Marvell Armada 37x0 IIC controller");
179 
180 	return (BUS_PROBE_DEFAULT);
181 }
182 
183 static int
184 a37x0_iic_attach(device_t dev)
185 {
186 	int rid;
187 	phandle_t node;
188 	struct a37x0_iic_softc *sc;
189 
190 	sc = device_get_softc(dev);
191 	sc->sc_dev = dev;
192 
193 	rid = 0;
194 	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
195 	    RF_ACTIVE);
196 	if (!sc->sc_mem_res) {
197 		device_printf(dev, "cannot allocate memory window\n");
198 		return (ENXIO);
199 	}
200 
201 	sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
202 	sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
203 
204 	rid = 0;
205 	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
206 	    RF_ACTIVE | RF_SHAREABLE);
207 	if (!sc->sc_irq_res) {
208 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
209 		device_printf(dev, "cannot allocate interrupt\n");
210 		return (ENXIO);
211 	}
212 
213 	/* Hook up our interrupt handler. */
214 	if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
215 	    NULL, a37x0_iic_intr, sc, &sc->sc_intrhand)) {
216 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
217 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
218 		device_printf(dev, "cannot setup the interrupt handler\n");
219 		return (ENXIO);
220 	}
221 
222 	mtx_init(&sc->sc_mtx, "a37x0_iic", NULL, MTX_DEF);
223 
224 	node = ofw_bus_get_node(dev);
225 	if (OF_hasprop(node, "mrvl,i2c-fast-mode"))
226 		sc->sc_fast_mode = true;
227 
228 	/* Enable the controller. */
229 	A37X0_IIC_LOCK(sc);
230 	a37x0_iic_reset(sc);
231 	A37X0_IIC_UNLOCK(sc);
232 
233 	sc->sc_iicbus = device_add_child(dev, "iicbus", DEVICE_UNIT_ANY);
234 	if (sc->sc_iicbus == NULL) {
235 		a37x0_iic_detach(dev);
236 		return (ENXIO);
237 	}
238 
239 	/* Probe and attach the iicbus. */
240 	bus_attach_children(dev);
241 	return (0);
242 }
243 
244 static int
245 a37x0_iic_detach(device_t dev)
246 {
247 	struct a37x0_iic_softc *sc;
248 
249 	bus_generic_detach(dev);
250 
251 	sc = device_get_softc(dev);
252 	if (sc->sc_iicbus != NULL)
253 		device_delete_child(dev, sc->sc_iicbus);
254 	mtx_destroy(&sc->sc_mtx);
255 	if (sc->sc_intrhand)
256 		bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
257 	if (sc->sc_irq_res)
258 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
259 	if (sc->sc_mem_res)
260 		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
261 
262 	return (0);
263 }
264 
265 static void
266 a37x0_iic_intr(void *arg)
267 {
268 	struct a37x0_iic_softc *sc;
269 	uint32_t status;
270 
271 	/* Not used, the interrupts are not enabled. */
272 	sc = (struct a37x0_iic_softc *)arg;
273 	A37X0_IIC_LOCK(sc);
274 	status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
275 #ifdef A37x0_IIC_DEBUG
276 	a37x0_iic_regdump(sc);
277 #endif
278 
279 	/* Clear pending interrrupts. */
280 	A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, status);
281 	A37X0_IIC_UNLOCK(sc);
282 }
283 
284 static int
285 a37x0_iic_stop(device_t dev)
286 {
287 	struct a37x0_iic_softc *sc;
288 	uint32_t reg;
289 
290 	sc = device_get_softc(dev);
291 	A37X0_IIC_LOCK(sc);
292 	/* Clear the STOP condition. */
293 	reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
294 	if (reg & (ICR_ACKNAK | ICR_STOP)) {
295 		reg &= ~(ICR_START | ICR_ACKNAK | ICR_STOP);
296 		A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg);
297 	}
298 	/* Clear interrupts. */
299 	reg = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
300 	A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, reg);
301 	A37X0_IIC_UNLOCK(sc);
302 
303 	return (IIC_NOERR);
304 }
305 
306 static int
307 a37x0_iic_start(device_t dev, u_char slave, int timeout)
308 {
309 	int rv;
310 	struct a37x0_iic_softc *sc;
311 	uint32_t reg, status;
312 
313 	sc = device_get_softc(dev);
314 	A37X0_IIC_LOCK(sc);
315 
316 	/* Wait for the bus to be free before start a transaction. */
317 	if (a37x0_iic_wait_clear(sc, ISR_IBB) == 0) {
318 		A37X0_IIC_UNLOCK(sc);
319 		return (IIC_ETIMEOUT);
320 	}
321 
322 	/* Write the slave address. */
323 	A37X0_IIC_WRITE(sc, A37X0_IIC_IDBR, slave);
324 
325 	/* Send Start condition (with slave address). */
326 	reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
327 	reg &= ~(ICR_STOP | ICR_ACKNAK);
328 	A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_START | ICR_TB);
329 
330 	rv = IIC_NOERR;
331 	if (a37x0_iic_wait_set(sc, ISR_ITE) == 0)
332 		rv = IIC_ETIMEOUT;
333 	if (rv == IIC_NOERR) {
334 		status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
335 		A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, status | ISR_ITE);
336 		if (a37x0_iic_wait_clear(sc, ISR_ACKNAK) == 0)
337 			rv = IIC_ENOACK;
338 	}
339 
340 	A37X0_IIC_UNLOCK(sc);
341 	if (rv != IIC_NOERR)
342 		a37x0_iic_stop(dev);
343 
344 	return (rv);
345 }
346 
347 static int
348 a37x0_iic_bus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
349 {
350 	struct a37x0_iic_softc *sc;
351 	uint32_t busfreq;
352 
353 	sc = device_get_softc(dev);
354 	A37X0_IIC_LOCK(sc);
355 	a37x0_iic_reset(sc);
356 	if (sc->sc_iicbus == NULL)
357 		busfreq = 100000;
358 	else
359 		busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
360 	a37x0_iic_rmw(sc, A37X0_IIC_ICR, ICR_MODE_MASK,
361 	    (busfreq > 100000) ? ICR_FAST_MODE : 0);
362 	A37X0_IIC_UNLOCK(sc);
363 
364 	return (IIC_ENOADDR);
365 }
366 
367 static int
368 a37x0_iic_read(device_t dev, char *buf, int len, int *read, int last, int delay)
369 {
370 	int rv;
371 	struct a37x0_iic_softc *sc;
372 	uint32_t reg, status;
373 
374 	sc = device_get_softc(dev);
375 	A37X0_IIC_LOCK(sc);
376 	reg = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
377 	if ((reg & (ISR_UB | ISR_IBB)) != ISR_UB) {
378 		A37X0_IIC_UNLOCK(sc);
379 		return (IIC_EBUSERR);
380 	}
381 
382 	*read = 0;
383 	rv = IIC_NOERR;
384 	while (*read < len) {
385 		reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
386 		reg &= ~(ICR_START | ICR_STOP | ICR_ACKNAK);
387 		if (*read == len - 1)
388 			reg |= ICR_ACKNAK | ICR_STOP;
389 		A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_TB);
390 		if (a37x0_iic_wait_set(sc, ISR_IRF) == 0) {
391 			rv = IIC_ETIMEOUT;
392 			break;
393 		}
394 		*buf++ = A37X0_IIC_READ(sc, A37X0_IIC_IDBR);
395 		(*read)++;
396 		status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
397 		A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, status | ISR_IRF);
398 	}
399 	A37X0_IIC_UNLOCK(sc);
400 
401 	return (rv);
402 }
403 
404 static int
405 a37x0_iic_write(device_t dev, const char *buf, int len, int *sent, int timeout)
406 {
407 	int rv;
408 	struct a37x0_iic_softc *sc;
409 	uint32_t reg, status;
410 
411 	sc = device_get_softc(dev);
412 	A37X0_IIC_LOCK(sc);
413 	reg = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
414 	if ((reg & (ISR_UB | ISR_IBB)) != ISR_UB) {
415 		A37X0_IIC_UNLOCK(sc);
416 		return (IIC_EBUSERR);
417 	}
418 
419 	rv = IIC_NOERR;
420 	*sent = 0;
421 	while (*sent < len) {
422 		A37X0_IIC_WRITE(sc, A37X0_IIC_IDBR, *buf++);
423 		reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
424 		reg &= ~(ICR_START | ICR_STOP | ICR_ACKNAK);
425 		if (*sent == len - 1)
426 			reg |= ICR_STOP;
427 		A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_TB);
428 		if (a37x0_iic_wait_set(sc, ISR_ITE) == 0) {
429 			rv = IIC_ETIMEOUT;
430 			break;
431 		}
432 		(*sent)++;
433 		status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
434 		A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, status | ISR_ITE);
435 		if (a37x0_iic_wait_clear(sc, ISR_ACKNAK) == 0) {
436 			rv = IIC_ENOACK;
437 			break;
438 		}
439 	}
440 	A37X0_IIC_UNLOCK(sc);
441 
442 	return (rv);
443 }
444 
445 static phandle_t
446 a37x0_iic_get_node(device_t bus, device_t dev)
447 {
448 
449 	return (ofw_bus_get_node(bus));
450 }
451 
452 static device_method_t a37x0_iic_methods[] = {
453 	/* Device interface */
454 	DEVMETHOD(device_probe,		a37x0_iic_probe),
455 	DEVMETHOD(device_attach,	a37x0_iic_attach),
456 	DEVMETHOD(device_detach,	a37x0_iic_detach),
457 
458 	/* iicbus interface */
459 	DEVMETHOD(iicbus_reset,		a37x0_iic_bus_reset),
460 	DEVMETHOD(iicbus_callback,	iicbus_null_callback),
461 	DEVMETHOD(iicbus_transfer,	iicbus_transfer_gen),
462 	DEVMETHOD(iicbus_repeated_start,	a37x0_iic_start),
463 	DEVMETHOD(iicbus_start,		a37x0_iic_start),
464 	DEVMETHOD(iicbus_stop,		a37x0_iic_stop),
465 	DEVMETHOD(iicbus_read,		a37x0_iic_read),
466 	DEVMETHOD(iicbus_write,		a37x0_iic_write),
467 
468 	/* ofw_bus interface */
469 	DEVMETHOD(ofw_bus_get_node,	a37x0_iic_get_node),
470 
471 	DEVMETHOD_END
472 };
473 
474 static driver_t a37x0_iic_driver = {
475 	"iichb",
476 	a37x0_iic_methods,
477 	sizeof(struct a37x0_iic_softc),
478 };
479 
480 DRIVER_MODULE(iicbus, a37x0_iic, iicbus_driver, 0, 0);
481 DRIVER_MODULE(a37x0_iic, simplebus, a37x0_iic_driver, 0, 0);
482