1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018, 2019 Rubicon Communications, LLC (Netgate) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 #include <sys/cdefs.h> 29 /* 30 * Driver for Armada 37x0 i2c controller. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/lock.h> 37 #include <sys/module.h> 38 #include <sys/mutex.h> 39 #include <sys/bus.h> 40 #include <machine/resource.h> 41 #include <machine/bus.h> 42 #include <sys/rman.h> 43 #include <sys/sysctl.h> 44 45 #include <dev/iicbus/iicbus.h> 46 #include <dev/iicbus/iiconf.h> 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include <arm/mv/a37x0_iicreg.h> 51 52 #include "iicbus_if.h" 53 54 struct a37x0_iic_softc { 55 boolean_t sc_fast_mode; 56 bus_space_tag_t sc_bst; 57 bus_space_handle_t sc_bsh; 58 device_t sc_dev; 59 device_t sc_iicbus; 60 struct mtx sc_mtx; 61 struct resource *sc_mem_res; 62 struct resource *sc_irq_res; 63 void *sc_intrhand; 64 }; 65 66 #define A37X0_IIC_WRITE(_sc, _off, _val) \ 67 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val) 68 #define A37X0_IIC_READ(_sc, _off) \ 69 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off) 70 #define A37X0_IIC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 71 #define A37X0_IIC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 72 73 static struct ofw_compat_data compat_data[] = { 74 { "marvell,armada-3700-i2c", 1 }, 75 { NULL, 0 } 76 }; 77 78 #undef A37x0_IIC_DEBUG 79 80 static void a37x0_iic_intr(void *); 81 static int a37x0_iic_detach(device_t); 82 83 static void 84 a37x0_iic_rmw(struct a37x0_iic_softc *sc, uint32_t off, uint32_t mask, 85 uint32_t value) 86 { 87 uint32_t reg; 88 89 mtx_assert(&sc->sc_mtx, MA_OWNED); 90 reg = A37X0_IIC_READ(sc, off); 91 reg &= ~mask; 92 reg |= value; 93 A37X0_IIC_WRITE(sc, off, reg); 94 } 95 96 static int 97 a37x0_iic_wait_clear(struct a37x0_iic_softc *sc, uint32_t mask) 98 { 99 int timeout; 100 uint32_t status; 101 102 mtx_assert(&sc->sc_mtx, MA_OWNED); 103 timeout = 1000; 104 do { 105 DELAY(10); 106 status = A37X0_IIC_READ(sc, A37X0_IIC_ISR); 107 if (--timeout == 0) 108 return (0); 109 } while ((status & mask) != 0); 110 111 return (1); 112 } 113 114 static int 115 a37x0_iic_wait_set(struct a37x0_iic_softc *sc, uint32_t mask) 116 { 117 int timeout; 118 uint32_t status; 119 120 mtx_assert(&sc->sc_mtx, MA_OWNED); 121 timeout = 1000; 122 do { 123 DELAY(10); 124 status = A37X0_IIC_READ(sc, A37X0_IIC_ISR); 125 if (--timeout == 0) 126 return (0); 127 } while ((status & mask) != mask); 128 129 return (1); 130 } 131 132 #ifdef A37x0_IIC_DEBUG 133 static void 134 a37x0_iic_regdump(struct a37x0_iic_softc *sc) 135 { 136 137 mtx_assert(&sc->sc_mtx, MA_OWNED); 138 printf("%s: IBMR: %#x\n", __func__, A37X0_IIC_READ(sc, A37X0_IIC_IBMR)); 139 printf("%s: ICR: %#x\n", __func__, A37X0_IIC_READ(sc, A37X0_IIC_ICR)); 140 printf("%s: ISR: %#x\n", __func__, A37X0_IIC_READ(sc, A37X0_IIC_ISR)); 141 } 142 #endif 143 144 static void 145 a37x0_iic_reset(struct a37x0_iic_softc *sc) 146 { 147 uint32_t mode, reg; 148 149 mtx_assert(&sc->sc_mtx, MA_OWNED); 150 151 /* Disable the controller. */ 152 reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR); 153 mode = reg & ICR_MODE_MASK; 154 A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg & ~ICR_IUE); 155 A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_UR); 156 DELAY(100); 157 A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg & ~ICR_IUE); 158 159 /* Enable the controller. */ 160 reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR); 161 reg |= mode | ICR_IUE | ICR_GCD | ICR_SCLE; 162 A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg); 163 #ifdef A37x0_IIC_DEBUG 164 a37x0_iic_regdump(sc); 165 #endif 166 } 167 168 static int 169 a37x0_iic_probe(device_t dev) 170 { 171 172 if (!ofw_bus_status_okay(dev)) 173 return (ENXIO); 174 175 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 176 return (ENXIO); 177 178 device_set_desc(dev, "Marvell Armada 37x0 IIC controller"); 179 180 return (BUS_PROBE_DEFAULT); 181 } 182 183 static int 184 a37x0_iic_attach(device_t dev) 185 { 186 int rid; 187 phandle_t node; 188 struct a37x0_iic_softc *sc; 189 190 sc = device_get_softc(dev); 191 sc->sc_dev = dev; 192 193 rid = 0; 194 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 195 RF_ACTIVE); 196 if (!sc->sc_mem_res) { 197 device_printf(dev, "cannot allocate memory window\n"); 198 return (ENXIO); 199 } 200 201 sc->sc_bst = rman_get_bustag(sc->sc_mem_res); 202 sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); 203 204 rid = 0; 205 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 206 RF_ACTIVE | RF_SHAREABLE); 207 if (!sc->sc_irq_res) { 208 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 209 device_printf(dev, "cannot allocate interrupt\n"); 210 return (ENXIO); 211 } 212 213 /* Hook up our interrupt handler. */ 214 if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 215 NULL, a37x0_iic_intr, sc, &sc->sc_intrhand)) { 216 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 217 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 218 device_printf(dev, "cannot setup the interrupt handler\n"); 219 return (ENXIO); 220 } 221 222 mtx_init(&sc->sc_mtx, "a37x0_iic", NULL, MTX_DEF); 223 224 node = ofw_bus_get_node(dev); 225 if (OF_hasprop(node, "mrvl,i2c-fast-mode")) 226 sc->sc_fast_mode = true; 227 228 /* Enable the controller. */ 229 A37X0_IIC_LOCK(sc); 230 a37x0_iic_reset(sc); 231 A37X0_IIC_UNLOCK(sc); 232 233 sc->sc_iicbus = device_add_child(dev, "iicbus", -1); 234 if (sc->sc_iicbus == NULL) { 235 a37x0_iic_detach(dev); 236 return (ENXIO); 237 } 238 239 /* Probe and attach the iicbus. */ 240 return (bus_generic_attach(dev)); 241 } 242 243 static int 244 a37x0_iic_detach(device_t dev) 245 { 246 struct a37x0_iic_softc *sc; 247 248 bus_generic_detach(dev); 249 250 sc = device_get_softc(dev); 251 if (sc->sc_iicbus != NULL) 252 device_delete_child(dev, sc->sc_iicbus); 253 mtx_destroy(&sc->sc_mtx); 254 if (sc->sc_intrhand) 255 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); 256 if (sc->sc_irq_res) 257 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 258 if (sc->sc_mem_res) 259 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 260 261 return (0); 262 } 263 264 static void 265 a37x0_iic_intr(void *arg) 266 { 267 struct a37x0_iic_softc *sc; 268 uint32_t status; 269 270 /* Not used, the interrupts are not enabled. */ 271 sc = (struct a37x0_iic_softc *)arg; 272 A37X0_IIC_LOCK(sc); 273 status = A37X0_IIC_READ(sc, A37X0_IIC_ISR); 274 #ifdef A37x0_IIC_DEBUG 275 a37x0_iic_regdump(sc); 276 #endif 277 278 /* Clear pending interrrupts. */ 279 A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, status); 280 A37X0_IIC_UNLOCK(sc); 281 } 282 283 static int 284 a37x0_iic_stop(device_t dev) 285 { 286 struct a37x0_iic_softc *sc; 287 uint32_t reg; 288 289 sc = device_get_softc(dev); 290 A37X0_IIC_LOCK(sc); 291 /* Clear the STOP condition. */ 292 reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR); 293 if (reg & (ICR_ACKNAK | ICR_STOP)) { 294 reg &= ~(ICR_START | ICR_ACKNAK | ICR_STOP); 295 A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg); 296 } 297 /* Clear interrupts. */ 298 reg = A37X0_IIC_READ(sc, A37X0_IIC_ISR); 299 A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, reg); 300 A37X0_IIC_UNLOCK(sc); 301 302 return (IIC_NOERR); 303 } 304 305 static int 306 a37x0_iic_start(device_t dev, u_char slave, int timeout) 307 { 308 int rv; 309 struct a37x0_iic_softc *sc; 310 uint32_t reg, status; 311 312 sc = device_get_softc(dev); 313 A37X0_IIC_LOCK(sc); 314 315 /* Wait for the bus to be free before start a transaction. */ 316 if (a37x0_iic_wait_clear(sc, ISR_IBB) == 0) { 317 A37X0_IIC_UNLOCK(sc); 318 return (IIC_ETIMEOUT); 319 } 320 321 /* Write the slave address. */ 322 A37X0_IIC_WRITE(sc, A37X0_IIC_IDBR, slave); 323 324 /* Send Start condition (with slave address). */ 325 reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR); 326 reg &= ~(ICR_STOP | ICR_ACKNAK); 327 A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_START | ICR_TB); 328 329 rv = IIC_NOERR; 330 if (a37x0_iic_wait_set(sc, ISR_ITE) == 0) 331 rv = IIC_ETIMEOUT; 332 if (rv == IIC_NOERR) { 333 status = A37X0_IIC_READ(sc, A37X0_IIC_ISR); 334 A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, status | ISR_ITE); 335 if (a37x0_iic_wait_clear(sc, ISR_ACKNAK) == 0) 336 rv = IIC_ENOACK; 337 } 338 339 A37X0_IIC_UNLOCK(sc); 340 if (rv != IIC_NOERR) 341 a37x0_iic_stop(dev); 342 343 return (rv); 344 } 345 346 static int 347 a37x0_iic_bus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 348 { 349 struct a37x0_iic_softc *sc; 350 uint32_t busfreq; 351 352 sc = device_get_softc(dev); 353 A37X0_IIC_LOCK(sc); 354 a37x0_iic_reset(sc); 355 if (sc->sc_iicbus == NULL) 356 busfreq = 100000; 357 else 358 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed); 359 a37x0_iic_rmw(sc, A37X0_IIC_ICR, ICR_MODE_MASK, 360 (busfreq > 100000) ? ICR_FAST_MODE : 0); 361 A37X0_IIC_UNLOCK(sc); 362 363 return (IIC_ENOADDR); 364 } 365 366 static int 367 a37x0_iic_read(device_t dev, char *buf, int len, int *read, int last, int delay) 368 { 369 int rv; 370 struct a37x0_iic_softc *sc; 371 uint32_t reg, status; 372 373 sc = device_get_softc(dev); 374 A37X0_IIC_LOCK(sc); 375 reg = A37X0_IIC_READ(sc, A37X0_IIC_ISR); 376 if ((reg & (ISR_UB | ISR_IBB)) != ISR_UB) { 377 A37X0_IIC_UNLOCK(sc); 378 return (IIC_EBUSERR); 379 } 380 381 *read = 0; 382 rv = IIC_NOERR; 383 while (*read < len) { 384 reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR); 385 reg &= ~(ICR_START | ICR_STOP | ICR_ACKNAK); 386 if (*read == len - 1) 387 reg |= ICR_ACKNAK | ICR_STOP; 388 A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_TB); 389 if (a37x0_iic_wait_set(sc, ISR_IRF) == 0) { 390 rv = IIC_ETIMEOUT; 391 break; 392 } 393 *buf++ = A37X0_IIC_READ(sc, A37X0_IIC_IDBR); 394 (*read)++; 395 status = A37X0_IIC_READ(sc, A37X0_IIC_ISR); 396 A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, status | ISR_IRF); 397 } 398 A37X0_IIC_UNLOCK(sc); 399 400 return (rv); 401 } 402 403 static int 404 a37x0_iic_write(device_t dev, const char *buf, int len, int *sent, int timeout) 405 { 406 int rv; 407 struct a37x0_iic_softc *sc; 408 uint32_t reg, status; 409 410 sc = device_get_softc(dev); 411 A37X0_IIC_LOCK(sc); 412 reg = A37X0_IIC_READ(sc, A37X0_IIC_ISR); 413 if ((reg & (ISR_UB | ISR_IBB)) != ISR_UB) { 414 A37X0_IIC_UNLOCK(sc); 415 return (IIC_EBUSERR); 416 } 417 418 rv = IIC_NOERR; 419 *sent = 0; 420 while (*sent < len) { 421 A37X0_IIC_WRITE(sc, A37X0_IIC_IDBR, *buf++); 422 reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR); 423 reg &= ~(ICR_START | ICR_STOP | ICR_ACKNAK); 424 if (*sent == len - 1) 425 reg |= ICR_STOP; 426 A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_TB); 427 if (a37x0_iic_wait_set(sc, ISR_ITE) == 0) { 428 rv = IIC_ETIMEOUT; 429 break; 430 } 431 (*sent)++; 432 status = A37X0_IIC_READ(sc, A37X0_IIC_ISR); 433 A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, status | ISR_ITE); 434 if (a37x0_iic_wait_clear(sc, ISR_ACKNAK) == 0) { 435 rv = IIC_ENOACK; 436 break; 437 } 438 } 439 A37X0_IIC_UNLOCK(sc); 440 441 return (rv); 442 } 443 444 static phandle_t 445 a37x0_iic_get_node(device_t bus, device_t dev) 446 { 447 448 return (ofw_bus_get_node(bus)); 449 } 450 451 static device_method_t a37x0_iic_methods[] = { 452 /* Device interface */ 453 DEVMETHOD(device_probe, a37x0_iic_probe), 454 DEVMETHOD(device_attach, a37x0_iic_attach), 455 DEVMETHOD(device_detach, a37x0_iic_detach), 456 457 /* iicbus interface */ 458 DEVMETHOD(iicbus_reset, a37x0_iic_bus_reset), 459 DEVMETHOD(iicbus_callback, iicbus_null_callback), 460 DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), 461 DEVMETHOD(iicbus_repeated_start, a37x0_iic_start), 462 DEVMETHOD(iicbus_start, a37x0_iic_start), 463 DEVMETHOD(iicbus_stop, a37x0_iic_stop), 464 DEVMETHOD(iicbus_read, a37x0_iic_read), 465 DEVMETHOD(iicbus_write, a37x0_iic_write), 466 467 /* ofw_bus interface */ 468 DEVMETHOD(ofw_bus_get_node, a37x0_iic_get_node), 469 470 DEVMETHOD_END 471 }; 472 473 static driver_t a37x0_iic_driver = { 474 "iichb", 475 a37x0_iic_methods, 476 sizeof(struct a37x0_iic_softc), 477 }; 478 479 DRIVER_MODULE(iicbus, a37x0_iic, iicbus_driver, 0, 0); 480 DRIVER_MODULE(a37x0_iic, simplebus, a37x0_iic_driver, 0, 0); 481