1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018-2019, Rubicon Communications, LLC (Netgate) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 36 #include <sys/gpio.h> 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/rman.h> 40 41 #include <machine/bus.h> 42 #include <machine/resource.h> 43 44 #include <dev/gpio/gpiobusvar.h> 45 #include <dev/ofw/ofw_bus.h> 46 #include <dev/ofw/ofw_bus_subr.h> 47 48 #include "gpio_if.h" 49 #include "syscon_if.h" 50 51 struct a37x0_gpio_softc { 52 device_t sc_busdev; 53 int sc_type; 54 uint32_t sc_max_pins; 55 uint32_t sc_npins; 56 struct syscon *syscon; 57 }; 58 59 /* Memory regions. */ 60 #define A37X0_GPIO 0 61 #define A37X0_INTR 1 62 63 /* North Bridge / South Bridge. */ 64 #define A37X0_NB_GPIO 1 65 #define A37X0_SB_GPIO 2 66 67 #define A37X0_GPIO_WRITE(_sc, _off, _val) \ 68 SYSCON_WRITE_4((_sc)->syscon, (_off), (_val)) 69 #define A37X0_GPIO_READ(_sc, _off) \ 70 SYSCON_READ_4((_sc)->syscon, (_off)) 71 72 #define A37X0_GPIO_BIT(_p) (1U << ((_p) % 32)) 73 #define A37X0_GPIO_OUT_EN(_p) (0x0 + ((_p) / 32) * 4) 74 #define A37X0_GPIO_LATCH(_p) (0x8 + ((_p) / 32) * 4) 75 #define A37X0_GPIO_INPUT(_p) (0x10 + ((_p) / 32) * 4) 76 #define A37X0_GPIO_OUTPUT(_p) (0x18 + ((_p) / 32) * 4) 77 #define A37X0_GPIO_SEL 0x30 78 79 static struct ofw_compat_data compat_data[] = { 80 { "marvell,armada3710-nb-pinctrl", A37X0_NB_GPIO }, 81 { "marvell,armada3710-sb-pinctrl", A37X0_SB_GPIO }, 82 { NULL, 0 } 83 }; 84 85 static phandle_t 86 a37x0_gpio_get_node(device_t bus, device_t dev) 87 { 88 89 return (ofw_bus_get_node(bus)); 90 } 91 92 static device_t 93 a37x0_gpio_get_bus(device_t dev) 94 { 95 struct a37x0_gpio_softc *sc; 96 97 sc = device_get_softc(dev); 98 99 return (sc->sc_busdev); 100 } 101 102 static int 103 a37x0_gpio_pin_max(device_t dev, int *maxpin) 104 { 105 struct a37x0_gpio_softc *sc; 106 107 sc = device_get_softc(dev); 108 *maxpin = sc->sc_npins - 1; 109 110 return (0); 111 } 112 113 static int 114 a37x0_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 115 { 116 struct a37x0_gpio_softc *sc; 117 118 sc = device_get_softc(dev); 119 if (pin >= sc->sc_npins) 120 return (EINVAL); 121 snprintf(name, GPIOMAXNAME, "pin %d", pin); 122 123 return (0); 124 } 125 126 static int 127 a37x0_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 128 { 129 struct a37x0_gpio_softc *sc; 130 131 sc = device_get_softc(dev); 132 if (pin >= sc->sc_npins) 133 return (EINVAL); 134 *caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 135 136 return (0); 137 } 138 139 static int 140 a37x0_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 141 { 142 struct a37x0_gpio_softc *sc; 143 uint32_t reg; 144 145 sc = device_get_softc(dev); 146 if (pin >= sc->sc_npins) 147 return (EINVAL); 148 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin)); 149 if ((reg & A37X0_GPIO_BIT(pin)) != 0) 150 *flags = GPIO_PIN_OUTPUT; 151 else 152 *flags = GPIO_PIN_INPUT; 153 154 return (0); 155 } 156 157 static int 158 a37x0_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 159 { 160 struct a37x0_gpio_softc *sc; 161 uint32_t reg; 162 163 sc = device_get_softc(dev); 164 if (pin >= sc->sc_npins) 165 return (EINVAL); 166 167 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin)); 168 if (flags & GPIO_PIN_OUTPUT) 169 reg |= A37X0_GPIO_BIT(pin); 170 else 171 reg &= ~A37X0_GPIO_BIT(pin); 172 A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUT_EN(pin), reg); 173 174 return (0); 175 } 176 177 static int 178 a37x0_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 179 { 180 struct a37x0_gpio_softc *sc; 181 uint32_t reg; 182 183 sc = device_get_softc(dev); 184 if (pin >= sc->sc_npins) 185 return (EINVAL); 186 187 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin)); 188 if ((reg & A37X0_GPIO_BIT(pin)) != 0) 189 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin)); 190 else 191 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_INPUT(pin)); 192 *val = ((reg & A37X0_GPIO_BIT(pin)) != 0) ? 1 : 0; 193 194 return (0); 195 } 196 197 static int 198 a37x0_gpio_pin_set(device_t dev, uint32_t pin, unsigned int val) 199 { 200 struct a37x0_gpio_softc *sc; 201 uint32_t reg; 202 203 sc = device_get_softc(dev); 204 if (pin >= sc->sc_npins) 205 return (EINVAL); 206 207 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin)); 208 if (val != 0) 209 reg |= A37X0_GPIO_BIT(pin); 210 else 211 reg &= ~A37X0_GPIO_BIT(pin); 212 A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg); 213 214 return (0); 215 } 216 217 static int 218 a37x0_gpio_pin_toggle(device_t dev, uint32_t pin) 219 { 220 struct a37x0_gpio_softc *sc; 221 uint32_t reg; 222 223 sc = device_get_softc(dev); 224 if (pin >= sc->sc_npins) 225 return (EINVAL); 226 227 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin)); 228 if ((reg & A37X0_GPIO_BIT(pin)) == 0) 229 return (EINVAL); 230 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin)); 231 reg ^= A37X0_GPIO_BIT(pin); 232 A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg); 233 234 return (0); 235 } 236 237 static int 238 a37x0_gpio_probe(device_t dev) 239 { 240 const char *desc; 241 struct a37x0_gpio_softc *sc; 242 243 if (!OF_hasprop(ofw_bus_get_node(dev), "gpio-controller")) 244 return (ENXIO); 245 246 sc = device_get_softc(dev); 247 sc->sc_type = ofw_bus_search_compatible( 248 device_get_parent(dev), compat_data)->ocd_data; 249 switch (sc->sc_type) { 250 case A37X0_NB_GPIO: 251 sc->sc_max_pins = 36; 252 desc = "Armada 37x0 North Bridge GPIO Controller"; 253 break; 254 case A37X0_SB_GPIO: 255 sc->sc_max_pins = 30; 256 desc = "Armada 37x0 South Bridge GPIO Controller"; 257 break; 258 default: 259 return (ENXIO); 260 } 261 device_set_desc(dev, desc); 262 263 return (BUS_PROBE_DEFAULT); 264 } 265 266 static int 267 a37x0_gpio_attach(device_t dev) 268 { 269 int err, ncells; 270 pcell_t *ranges; 271 struct a37x0_gpio_softc *sc; 272 273 sc = device_get_softc(dev); 274 275 err = syscon_get_handle_default(dev, &sc->syscon); 276 if (err != 0) { 277 device_printf(dev, "Cannot get syscon handle from parent\n"); 278 return (ENXIO); 279 } 280 281 /* Read and verify the "gpio-ranges" property. */ 282 ncells = OF_getencprop_alloc(ofw_bus_get_node(dev), "gpio-ranges", 283 (void **)&ranges); 284 if (ncells == -1) 285 return (ENXIO); 286 if (ncells != sizeof(*ranges) * 4 || ranges[1] != 0 || ranges[2] != 0) { 287 OF_prop_free(ranges); 288 return (ENXIO); 289 } 290 sc->sc_npins = ranges[3]; 291 OF_prop_free(ranges); 292 293 /* Check the number of pins in the DTS vs HW capabilities. */ 294 if (sc->sc_npins > sc->sc_max_pins) 295 return (ENXIO); 296 297 sc->sc_busdev = gpiobus_attach_bus(dev); 298 if (sc->sc_busdev == NULL) 299 return (ENXIO); 300 301 return (0); 302 } 303 304 static int 305 a37x0_gpio_detach(device_t dev) 306 { 307 308 return (EBUSY); 309 } 310 311 static device_method_t a37x0_gpio_methods[] = { 312 /* Device interface */ 313 DEVMETHOD(device_probe, a37x0_gpio_probe), 314 DEVMETHOD(device_attach, a37x0_gpio_attach), 315 DEVMETHOD(device_detach, a37x0_gpio_detach), 316 317 /* GPIO interface */ 318 DEVMETHOD(gpio_get_bus, a37x0_gpio_get_bus), 319 DEVMETHOD(gpio_pin_max, a37x0_gpio_pin_max), 320 DEVMETHOD(gpio_pin_getname, a37x0_gpio_pin_getname), 321 DEVMETHOD(gpio_pin_getcaps, a37x0_gpio_pin_getcaps), 322 DEVMETHOD(gpio_pin_getflags, a37x0_gpio_pin_getflags), 323 DEVMETHOD(gpio_pin_setflags, a37x0_gpio_pin_setflags), 324 DEVMETHOD(gpio_pin_get, a37x0_gpio_pin_get), 325 DEVMETHOD(gpio_pin_set, a37x0_gpio_pin_set), 326 DEVMETHOD(gpio_pin_toggle, a37x0_gpio_pin_toggle), 327 328 /* ofw_bus interface */ 329 DEVMETHOD(ofw_bus_get_node, a37x0_gpio_get_node), 330 331 DEVMETHOD_END 332 }; 333 334 static driver_t a37x0_gpio_driver = { 335 "gpio", 336 a37x0_gpio_methods, 337 sizeof(struct a37x0_gpio_softc), 338 }; 339 340 EARLY_DRIVER_MODULE(a37x0_gpio, simple_mfd, a37x0_gpio_driver, 0, 0, 341 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); 342