1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018-2019, Rubicon Communications, LLC (Netgate) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/param.h> 30 #include <sys/systm.h> 31 #include <sys/bus.h> 32 33 #include <sys/gpio.h> 34 #include <sys/kernel.h> 35 #include <sys/module.h> 36 #include <sys/rman.h> 37 38 #include <machine/bus.h> 39 #include <machine/resource.h> 40 41 #include <dev/gpio/gpiobusvar.h> 42 #include <dev/ofw/ofw_bus.h> 43 #include <dev/ofw/ofw_bus_subr.h> 44 45 #include "gpio_if.h" 46 #include "syscon_if.h" 47 48 struct a37x0_gpio_softc { 49 device_t sc_busdev; 50 int sc_type; 51 uint32_t sc_max_pins; 52 uint32_t sc_npins; 53 struct syscon *syscon; 54 }; 55 56 /* Memory regions. */ 57 #define A37X0_GPIO 0 58 #define A37X0_INTR 1 59 60 /* North Bridge / South Bridge. */ 61 #define A37X0_NB_GPIO 1 62 #define A37X0_SB_GPIO 2 63 64 #define A37X0_GPIO_WRITE(_sc, _off, _val) \ 65 SYSCON_WRITE_4((_sc)->syscon, (_off), (_val)) 66 #define A37X0_GPIO_READ(_sc, _off) \ 67 SYSCON_READ_4((_sc)->syscon, (_off)) 68 69 #define A37X0_GPIO_BIT(_p) (1U << ((_p) % 32)) 70 #define A37X0_GPIO_OUT_EN(_p) (0x0 + ((_p) / 32) * 4) 71 #define A37X0_GPIO_LATCH(_p) (0x8 + ((_p) / 32) * 4) 72 #define A37X0_GPIO_INPUT(_p) (0x10 + ((_p) / 32) * 4) 73 #define A37X0_GPIO_OUTPUT(_p) (0x18 + ((_p) / 32) * 4) 74 #define A37X0_GPIO_SEL 0x30 75 76 static struct ofw_compat_data compat_data[] = { 77 { "marvell,armada3710-nb-pinctrl", A37X0_NB_GPIO }, 78 { "marvell,armada3710-sb-pinctrl", A37X0_SB_GPIO }, 79 { NULL, 0 } 80 }; 81 82 static phandle_t 83 a37x0_gpio_get_node(device_t bus, device_t dev) 84 { 85 86 return (ofw_bus_get_node(bus)); 87 } 88 89 static device_t 90 a37x0_gpio_get_bus(device_t dev) 91 { 92 struct a37x0_gpio_softc *sc; 93 94 sc = device_get_softc(dev); 95 96 return (sc->sc_busdev); 97 } 98 99 static int 100 a37x0_gpio_pin_max(device_t dev, int *maxpin) 101 { 102 struct a37x0_gpio_softc *sc; 103 104 sc = device_get_softc(dev); 105 *maxpin = sc->sc_npins - 1; 106 107 return (0); 108 } 109 110 static int 111 a37x0_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 112 { 113 struct a37x0_gpio_softc *sc; 114 115 sc = device_get_softc(dev); 116 if (pin >= sc->sc_npins) 117 return (EINVAL); 118 snprintf(name, GPIOMAXNAME, "pin %d", pin); 119 120 return (0); 121 } 122 123 static int 124 a37x0_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 125 { 126 struct a37x0_gpio_softc *sc; 127 128 sc = device_get_softc(dev); 129 if (pin >= sc->sc_npins) 130 return (EINVAL); 131 *caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; 132 133 return (0); 134 } 135 136 static int 137 a37x0_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 138 { 139 struct a37x0_gpio_softc *sc; 140 uint32_t reg; 141 142 sc = device_get_softc(dev); 143 if (pin >= sc->sc_npins) 144 return (EINVAL); 145 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin)); 146 if ((reg & A37X0_GPIO_BIT(pin)) != 0) 147 *flags = GPIO_PIN_OUTPUT; 148 else 149 *flags = GPIO_PIN_INPUT; 150 151 return (0); 152 } 153 154 static int 155 a37x0_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 156 { 157 struct a37x0_gpio_softc *sc; 158 uint32_t reg; 159 160 sc = device_get_softc(dev); 161 if (pin >= sc->sc_npins) 162 return (EINVAL); 163 164 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin)); 165 if (flags & GPIO_PIN_OUTPUT) 166 reg |= A37X0_GPIO_BIT(pin); 167 else 168 reg &= ~A37X0_GPIO_BIT(pin); 169 A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUT_EN(pin), reg); 170 171 return (0); 172 } 173 174 static int 175 a37x0_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 176 { 177 struct a37x0_gpio_softc *sc; 178 uint32_t reg; 179 180 sc = device_get_softc(dev); 181 if (pin >= sc->sc_npins) 182 return (EINVAL); 183 184 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin)); 185 if ((reg & A37X0_GPIO_BIT(pin)) != 0) 186 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin)); 187 else 188 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_INPUT(pin)); 189 *val = ((reg & A37X0_GPIO_BIT(pin)) != 0) ? 1 : 0; 190 191 return (0); 192 } 193 194 static int 195 a37x0_gpio_pin_set(device_t dev, uint32_t pin, unsigned int val) 196 { 197 struct a37x0_gpio_softc *sc; 198 uint32_t reg; 199 200 sc = device_get_softc(dev); 201 if (pin >= sc->sc_npins) 202 return (EINVAL); 203 204 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin)); 205 if (val != 0) 206 reg |= A37X0_GPIO_BIT(pin); 207 else 208 reg &= ~A37X0_GPIO_BIT(pin); 209 A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg); 210 211 return (0); 212 } 213 214 static int 215 a37x0_gpio_pin_toggle(device_t dev, uint32_t pin) 216 { 217 struct a37x0_gpio_softc *sc; 218 uint32_t reg; 219 220 sc = device_get_softc(dev); 221 if (pin >= sc->sc_npins) 222 return (EINVAL); 223 224 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin)); 225 if ((reg & A37X0_GPIO_BIT(pin)) == 0) 226 return (EINVAL); 227 reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin)); 228 reg ^= A37X0_GPIO_BIT(pin); 229 A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg); 230 231 return (0); 232 } 233 234 static int 235 a37x0_gpio_probe(device_t dev) 236 { 237 const char *desc; 238 struct a37x0_gpio_softc *sc; 239 240 if (!OF_hasprop(ofw_bus_get_node(dev), "gpio-controller")) 241 return (ENXIO); 242 243 sc = device_get_softc(dev); 244 sc->sc_type = ofw_bus_search_compatible( 245 device_get_parent(dev), compat_data)->ocd_data; 246 switch (sc->sc_type) { 247 case A37X0_NB_GPIO: 248 sc->sc_max_pins = 36; 249 desc = "Armada 37x0 North Bridge GPIO Controller"; 250 break; 251 case A37X0_SB_GPIO: 252 sc->sc_max_pins = 30; 253 desc = "Armada 37x0 South Bridge GPIO Controller"; 254 break; 255 default: 256 return (ENXIO); 257 } 258 device_set_desc(dev, desc); 259 260 return (BUS_PROBE_DEFAULT); 261 } 262 263 static int 264 a37x0_gpio_attach(device_t dev) 265 { 266 int err, ncells; 267 pcell_t *ranges; 268 struct a37x0_gpio_softc *sc; 269 270 sc = device_get_softc(dev); 271 272 err = syscon_get_handle_default(dev, &sc->syscon); 273 if (err != 0) { 274 device_printf(dev, "Cannot get syscon handle from parent\n"); 275 return (ENXIO); 276 } 277 278 /* Read and verify the "gpio-ranges" property. */ 279 ncells = OF_getencprop_alloc(ofw_bus_get_node(dev), "gpio-ranges", 280 (void **)&ranges); 281 if (ncells == -1) 282 return (ENXIO); 283 if (ncells != sizeof(*ranges) * 4 || ranges[1] != 0 || ranges[2] != 0) { 284 OF_prop_free(ranges); 285 return (ENXIO); 286 } 287 sc->sc_npins = ranges[3]; 288 OF_prop_free(ranges); 289 290 /* Check the number of pins in the DTS vs HW capabilities. */ 291 if (sc->sc_npins > sc->sc_max_pins) 292 return (ENXIO); 293 294 sc->sc_busdev = gpiobus_attach_bus(dev); 295 if (sc->sc_busdev == NULL) 296 return (ENXIO); 297 298 return (0); 299 } 300 301 static int 302 a37x0_gpio_detach(device_t dev) 303 { 304 305 return (EBUSY); 306 } 307 308 static device_method_t a37x0_gpio_methods[] = { 309 /* Device interface */ 310 DEVMETHOD(device_probe, a37x0_gpio_probe), 311 DEVMETHOD(device_attach, a37x0_gpio_attach), 312 DEVMETHOD(device_detach, a37x0_gpio_detach), 313 314 /* GPIO interface */ 315 DEVMETHOD(gpio_get_bus, a37x0_gpio_get_bus), 316 DEVMETHOD(gpio_pin_max, a37x0_gpio_pin_max), 317 DEVMETHOD(gpio_pin_getname, a37x0_gpio_pin_getname), 318 DEVMETHOD(gpio_pin_getcaps, a37x0_gpio_pin_getcaps), 319 DEVMETHOD(gpio_pin_getflags, a37x0_gpio_pin_getflags), 320 DEVMETHOD(gpio_pin_setflags, a37x0_gpio_pin_setflags), 321 DEVMETHOD(gpio_pin_get, a37x0_gpio_pin_get), 322 DEVMETHOD(gpio_pin_set, a37x0_gpio_pin_set), 323 DEVMETHOD(gpio_pin_toggle, a37x0_gpio_pin_toggle), 324 325 /* ofw_bus interface */ 326 DEVMETHOD(ofw_bus_get_node, a37x0_gpio_get_node), 327 328 DEVMETHOD_END 329 }; 330 331 static driver_t a37x0_gpio_driver = { 332 "gpio", 333 a37x0_gpio_methods, 334 sizeof(struct a37x0_gpio_softc), 335 }; 336 337 EARLY_DRIVER_MODULE(a37x0_gpio, simple_mfd, a37x0_gpio_driver, 0, 0, 338 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); 339