xref: /freebsd/sys/arm/include/vfp.h (revision 3416500aef140042c64bc149cb1ec6620483bc44)
1 /*
2  * Copyright (c) 2012 Mark Tinguely
3  *
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  * $FreeBSD$
27  */
28 
29 
30 #ifndef _MACHINE__VFP_H_
31 #define _MACHINE__VFP_H_
32 
33 /* fpsid, fpscr, fpexc are defined in the newer gas */
34 #define	VFPSID			cr0
35 #define	VFPSCR			cr1
36 #define	VMVFR1			cr6
37 #define	VMVFR0			cr7
38 #define	VFPEXC			cr8
39 #define	VFPINST			cr9	/* vfp 1 and 2 except instruction */
40 #define	VFPINST2		cr10 	/* vfp 2? */
41 
42 /* VFPSID */
43 #define	VFPSID_IMPLEMENTOR_OFF	24
44 #define	VFPSID_IMPLEMENTOR_MASK	(0xff000000)
45 #define	VFPSID_HARDSOFT_IMP	(0x00800000)
46 #define	VFPSID_SINGLE_PREC	20	 /* version 1 and 2 */
47 #define	VFPSID_SUBVERSION_OFF	16
48 #define	VFPSID_SUBVERSION2_MASK	(0x000f0000)	 /* version 1 and 2 */
49 #define	VFPSID_SUBVERSION3_MASK	(0x007f0000)	 /* version 3 */
50 #define	VFP_ARCH1		0x0
51 #define	VFP_ARCH2		0x1
52 #define	VFP_ARCH3		0x2
53 #define	VFPSID_PARTNUMBER_OFF	8
54 #define	VFPSID_PARTNUMBER_MASK	(0x0000ff00)
55 #define	VFPSID_VARIANT_OFF	4
56 #define	VFPSID_VARIANT_MASK	(0x000000f0)
57 #define	VFPSID_REVISION_MASK	0x0f
58 
59 /* VFPSCR */
60 #define	VFPSCR_CC_N		(0x80000000)	/* comparison less than */
61 #define	VFPSCR_CC_Z		(0x40000000)	/* comparison equal */
62 #define	VFPSCR_CC_C		(0x20000000)	/* comparison = > unordered */
63 #define	VFPSCR_CC_V		(0x10000000)	/* comparison unordered */
64 #define	VFPSCR_QC		(0x08000000)	/* saturation cululative */
65 #define	VFPSCR_DN		(0x02000000)	/* default NaN enable */
66 #define	VFPSCR_FZ		(0x01000000)	/* flush to zero enabled */
67 
68 #define	VFPSCR_RMODE_OFF	22		/* rounding mode offset */
69 #define	VFPSCR_RMODE_MASK	(0x00c00000)	/* rounding mode mask */
70 #define	VFPSCR_RMODE_RN		(0x00000000)	/* round nearest */
71 #define	VFPSCR_RMODE_RPI	(0x00400000)	/* round to plus infinity */
72 #define	VFPSCR_RMODE_RNI	(0x00800000)	/* round to neg infinity */
73 #define	VFPSCR_RMODE_RM		(0x00c00000)	/* round to zero */
74 
75 #define	VFPSCR_STRIDE_OFF	20		/* vector stride -1 */
76 #define	VFPSCR_STRIDE_MASK	(0x00300000)
77 #define	VFPSCR_LEN_OFF		16		/* vector length -1 */
78 #define	VFPSCR_LEN_MASK		(0x00070000)
79 #define	VFPSCR_IDE		(0x00008000)	/* input subnormal exc enable */
80 #define	VFPSCR_IXE		(0x00001000)	/* inexact exception enable */
81 #define	VFPSCR_UFE		(0x00000800)	/* underflow exception enable */
82 #define	VFPSCR_OFE		(0x00000400)	/* overflow exception enable */
83 #define	VFPSCR_DNZ		(0x00000200)	/* div by zero exception en */
84 #define	VFPSCR_IOE		(0x00000100)	/* invalid op exec enable */
85 #define	VFPSCR_IDC		(0x00000080)	/* input subnormal cumul */
86 #define	VFPSCR_IXC		(0x00000010)	/* Inexact cumulative flag */
87 #define	VFPSCR_UFC		(0x00000008)	/* underflow cumulative flag */
88 #define	VFPSCR_OFC		(0x00000004)	/* overflow cumulative flag */
89 #define	VFPSCR_DZC		(0x00000002)	/* division by zero flag */
90 #define	VFPSCR_IOC		(0x00000001)	/* invalid operation cumul */
91 
92 /* VFPEXC */
93 #define	VFPEXC_EX 		(0x80000000)	/* exception v1 v2 */
94 #define	VFPEXC_EN		(0x40000000)	/* vfp enable */
95 #define	VFPEXC_DEX		(0x20000000)	/* Synchronous exception */
96 #define	VFPEXC_FP2V		(0x10000000)	/* FPINST2 valid */
97 #define	VFPEXC_INV		(0x00000080)	/* Input exception */
98 #define	VFPEXC_UFC		(0x00000008)	/* Underflow exception */
99 #define	VFPEXC_OFC		(0x00000004)	/* Overflow exception */
100 #define	VFPEXC_IOC		(0x00000001)	/* Invlaid operation */
101 
102 /* version 3 registers */
103 /* VMVFR0 */
104 #define	VMVFR0_RM_OFF		28
105 #define	VMVFR0_RM_MASK 		(0xf0000000)	/* VFP rounding modes */
106 
107 #define	VMVFR0_SV_OFF		24
108 #define	VMVFR0_SV_MASK		(0x0f000000)	/* VFP short vector supp */
109 #define	VMVFR0_SR_OFF		20
110 #define	VMVFR0_SR		(0x00f00000)	/* VFP hw sqrt supp */
111 #define	VMVFR0_D_OFF		16
112 #define	VMVFR0_D_MASK		(0x000f0000)	/* VFP divide supp */
113 #define	VMVFR0_TE_OFF		12
114 #define	VMVFR0_TE_MASK		(0x0000f000)	/* VFP trap exception supp */
115 #define	VMVFR0_DP_OFF		8
116 #define	VMVFR0_DP_MASK		(0x00000f00)	/* VFP double prec support */
117 #define	VMVFR0_SP_OFF		4
118 #define	VMVFR0_SP_MASK		(0x000000f0)	/* VFP single prec support */
119 #define	VMVFR0_RB_MASK		(0x0000000f)	/* VFP 64 bit media support */
120 
121 /* VMVFR1 */
122 #define	VMVFR1_SP_OFF		16
123 #define	VMVFR1_SP_MASK 		(0x000f0000)	/* Neon single prec support */
124 #define VMVFR1_I_OFF		12
125 #define	VMVFR1_I_MASK		(0x0000f000)	/* Neon integer support */
126 #define VMVFR1_LS_OFF		8
127 #define	VMVFR1_LS_MASK		(0x00000f00)	/* Neon ld/st instr support */
128 #define VMVFR1_DN_OFF		4
129 #define	VMVFR1_DN_MASK		(0x000000f0)	/* Neon prop NaN support */
130 #define	VMVFR1_FZ_MASK		(0x0000000f)	/* Neon denormal arith supp */
131 
132 #define COPROC10		(0x3 << 20)
133 #define COPROC11		(0x3 << 22)
134 
135 #ifndef LOCORE
136 struct vfp_state {
137 	uint64_t reg[32];
138 	uint32_t fpscr;
139 	uint32_t fpexec;
140 	uint32_t fpinst;
141 	uint32_t fpinst2;
142 };
143 
144 #ifdef _KERNEL
145 void    vfp_init(void);
146 void    vfp_store(struct vfp_state *, boolean_t);
147 void    vfp_discard(struct thread *);
148 #endif	/* _KERNEL */
149 #endif	/* LOCORE */
150 
151 #endif
152