1 /* $NetBSD: pte.h,v 1.1 2001/11/23 17:39:04 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Mark Brinicombe. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the RiscBSD team. 18 * 4. The name "RiscBSD" nor the name of the author may be used to 19 * endorse or promote products derived from this software without specific 20 * prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 */ 36 37 #ifndef _MACHINE_PTE_H_ 38 #define _MACHINE_PTE_H_ 39 40 #define PDSHIFT 20 /* LOG2(NBPDR) */ 41 #define NBPD (1 << PDSHIFT) /* bytes/page dir */ 42 #define NPTEPD (NBPD / PAGE_SIZE) 43 44 #ifndef LOCORE 45 typedef uint32_t pd_entry_t; /* page directory entry */ 46 typedef uint32_t pt_entry_t; /* page table entry */ 47 #endif 48 49 #define PD_MASK 0xfff00000 /* page directory address bits */ 50 #define PT_MASK 0x000ff000 /* page table address bits */ 51 52 #define PG_FRAME 0xfffff000 53 54 /* The PT_SIZE definition is misleading... A page table is only 0x400 55 * bytes long. But since VM mapping can only be done to 0x1000 a single 56 * 1KB blocks cannot be steered to a va by itself. Therefore the 57 * pages tables are allocated in blocks of 4. i.e. if a 1 KB block 58 * was allocated for a PT then the other 3KB would also get mapped 59 * whenever the 1KB was mapped. 60 */ 61 62 #define PT_RSIZE 0x0400 /* Real page table size */ 63 #define PT_SIZE 0x1000 64 #define PD_SIZE 0x4000 65 66 /* Access permissions for L1 sections and L2 pages */ 67 #define AP_KR 0x00 68 #define AP_KRW 0x01 69 #define AP_KRWUR 0x02 70 #define AP_KRWURW 0x03 71 72 #define AP_W 0x01 73 #define AP_U 0x02 74 75 /* Physical bits in a pte */ 76 #define PT_B 0x04 /* Phys - Buffered (write) */ 77 #define PT_C 0x08 /* Phys - Cacheable */ 78 #define PT_U 0x10 /* Phys - Updateable */ 79 80 #ifndef LOCORE 81 extern pt_entry_t pte_cache_mode; 82 83 #define PT_CACHEABLE (pte_cache_mode) 84 #endif 85 86 /* Page R/M attributes (in pmseg.attrs). */ 87 #define PT_M 0x01 /* Virt - Modified */ 88 #define PT_H 0x02 /* Virt - Handled (Used) */ 89 /* Mapping wired/writeable/cacheable attributes (in pv_flags). */ 90 #define PT_W 0x04 /* Virt - Wired */ 91 #define PT_Wr 0x08 /* Virt / Phys Write */ 92 #define PT_NC 0x10 /* Cacheing disabled (multi-mapped page) */ 93 94 /* access permissions for L2 pages (all sub pages have the same perms) */ 95 #define PT_AP(x) ((x << 10) | (x << 8) | (x << 6) | (x << 4)) 96 97 /* shift for access permissions in a L1 section mapping */ 98 #define AP_SECTION_SHIFT 10 99 100 /* Page table types and masks */ 101 #define L1_PAGE 0x01 /* L1 page table mapping */ 102 #define L1_SECTION 0x02 /* L1 section mapping */ 103 #define L1_FPAGE 0x03 /* L1 fine page mapping */ 104 #define L1_MASK 0x03 /* Mask for L1 entry type */ 105 #define L2_LPAGE 0x01 /* L2 large page (64KB) */ 106 #define L2_SPAGE 0x02 /* L2 small page (4KB) */ 107 #define L2_MASK 0x03 /* Mask for L2 entry type */ 108 #define L2_INVAL 0x00 /* L2 invalid type */ 109 110 /* PTE construction macros */ 111 #define L2_LPTE(p, a, f) ((p) | PT_AP(a) | L2_LPAGE | (f)) 112 #define L2_SPTE(p, a, f) ((p) | PT_AP(a) | L2_SPAGE | (f)) 113 #define L2_PTE(p, a) L2_SPTE((p), (a), PT_CACHEABLE) 114 #define L2_PTE_NC(p, a) L2_SPTE((p), (a), PT_B) 115 #define L2_PTE_NC_NB(p, a) L2_SPTE((p), (a), 0) 116 #define L1_SECPTE(p, a, f) ((p) | ((a) << AP_SECTION_SHIFT) | (f) \ 117 | L1_SECTION | PT_U) 118 119 #define L1_PTE(p) ((p) | 0x00 | L1_PAGE | PT_U) 120 #define L1_SEC(p, c) L1_SECPTE((p), AP_KRW, (c)) 121 122 #define L1_SEC_SIZE (1 << PDSHIFT) 123 #define L2_LPAGE_SIZE (NBPG * 16) 124 125 /* Domain types */ 126 #define DOMAIN_FAULT 0x00 127 #define DOMAIN_CLIENT 0x01 128 #define DOMAIN_RESERVED 0x02 129 #define DOMAIN_MANAGER 0x03 130 131 /* L1 and L2 address masks */ 132 #define L1_ADDR_MASK 0xfffffc00 133 #define L2_ADDR_MASK 0xfffff000 134 135 /* 136 * The ARM MMU architecture was introduced with ARM v3 (previous ARM 137 * architecture versions used an optional off-CPU memory controller 138 * to perform address translation). 139 * 140 * The ARM MMU consists of a TLB and translation table walking logic. 141 * There is typically one TLB per memory interface (or, put another 142 * way, one TLB per software-visible cache). 143 * 144 * The ARM MMU is capable of mapping memory in the following chunks: 145 * 146 * 1M Sections (L1 table) 147 * 148 * 64K Large Pages (L2 table) 149 * 150 * 4K Small Pages (L2 table) 151 * 152 * 1K Tiny Pages (L2 table) 153 * 154 * There are two types of L2 tables: Coarse Tables and Fine Tables. 155 * Coarse Tables can map Large and Small Pages. Fine Tables can 156 * map Tiny Pages. 157 * 158 * Coarse Tables can define 4 Subpages within Large and Small pages. 159 * Subpages define different permissions for each Subpage within 160 * a Page. 161 * 162 * Coarse Tables are 1K in length. Fine tables are 4K in length. 163 * 164 * The Translation Table Base register holds the pointer to the 165 * L1 Table. The L1 Table is a 16K contiguous chunk of memory 166 * aligned to a 16K boundary. Each entry in the L1 Table maps 167 * 1M of virtual address space, either via a Section mapping or 168 * via an L2 Table. 169 * 170 * In addition, the Fast Context Switching Extension (FCSE) is available 171 * on some ARM v4 and ARM v5 processors. FCSE is a way of eliminating 172 * TLB/cache flushes on context switch by use of a smaller address space 173 * and a "process ID" that modifies the virtual address before being 174 * presented to the translation logic. 175 */ 176 177 #define L1_S_SIZE 0x00100000 /* 1M */ 178 #define L1_S_OFFSET (L1_S_SIZE - 1) 179 #define L1_S_FRAME (~L1_S_OFFSET) 180 #define L1_S_SHIFT 20 181 182 #define L2_L_SIZE 0x00010000 /* 64K */ 183 #define L2_L_OFFSET (L2_L_SIZE - 1) 184 #define L2_L_FRAME (~L2_L_OFFSET) 185 #define L2_L_SHIFT 16 186 187 #define L2_S_SIZE 0x00001000 /* 4K */ 188 #define L2_S_OFFSET (L2_S_SIZE - 1) 189 #define L2_S_FRAME (~L2_S_OFFSET) 190 #define L2_S_SHIFT 12 191 192 #define L2_T_SIZE 0x00000400 /* 1K */ 193 #define L2_T_OFFSET (L2_T_SIZE - 1) 194 #define L2_T_FRAME (~L2_T_OFFSET) 195 #define L2_T_SHIFT 10 196 197 /* 198 * The NetBSD VM implementation only works on whole pages (4K), 199 * whereas the ARM MMU's Coarse tables are sized in terms of 1K 200 * (16K L1 table, 1K L2 table). 201 * 202 * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2 203 * table. 204 */ 205 #define L1_ADDR_BITS 0xfff00000 /* L1 PTE address bits */ 206 #define L2_ADDR_BITS 0x000ff000 /* L2 PTE address bits */ 207 208 #define L1_TABLE_SIZE 0x4000 /* 16K */ 209 #define L2_TABLE_SIZE 0x1000 /* 4K */ 210 /* 211 * The new pmap deals with the 1KB coarse L2 tables by 212 * allocating them from a pool. Until every port has been converted, 213 * keep the old L2_TABLE_SIZE define lying around. Converted ports 214 * should use L2_TABLE_SIZE_REAL until then. 215 */ 216 #define L2_TABLE_SIZE_REAL 0x400 /* 1K */ 217 218 /* 219 * ARM L1 Descriptors 220 */ 221 222 #define L1_TYPE_INV 0x00 /* Invalid (fault) */ 223 #define L1_TYPE_C 0x01 /* Coarse L2 */ 224 #define L1_TYPE_S 0x02 /* Section */ 225 #define L1_TYPE_F 0x03 /* Fine L2 */ 226 #define L1_TYPE_MASK 0x03 /* mask of type bits */ 227 228 /* L1 Section Descriptor */ 229 #define L1_S_B 0x00000004 /* bufferable Section */ 230 #define L1_S_C 0x00000008 /* cacheable Section */ 231 #define L1_S_IMP 0x00000010 /* implementation defined */ 232 #define L1_S_DOM(x) ((x) << 5) /* domain */ 233 #define L1_S_DOM_MASK L1_S_DOM(0xf) 234 #define L1_S_AP(x) ((x) << 10) /* access permissions */ 235 #define L1_S_ADDR_MASK 0xfff00000 /* phys address of section */ 236 237 #define L1_S_XSCALE_P 0x00000200 /* ECC enable for this section */ 238 #define L1_S_XSCALE_TEX(x) ((x) << 12) /* Type Extension */ 239 240 /* L1 Coarse Descriptor */ 241 #define L1_C_IMP0 0x00000004 /* implementation defined */ 242 #define L1_C_IMP1 0x00000008 /* implementation defined */ 243 #define L1_C_IMP2 0x00000010 /* implementation defined */ 244 #define L1_C_DOM(x) ((x) << 5) /* domain */ 245 #define L1_C_DOM_MASK L1_C_DOM(0xf) 246 #define L1_C_ADDR_MASK 0xfffffc00 /* phys address of L2 Table */ 247 248 #define L1_C_XSCALE_P 0x00000200 /* ECC enable for this section */ 249 250 /* L1 Fine Descriptor */ 251 #define L1_F_IMP0 0x00000004 /* implementation defined */ 252 #define L1_F_IMP1 0x00000008 /* implementation defined */ 253 #define L1_F_IMP2 0x00000010 /* implementation defined */ 254 #define L1_F_DOM(x) ((x) << 5) /* domain */ 255 #define L1_F_DOM_MASK L1_F_DOM(0xf) 256 #define L1_F_ADDR_MASK 0xfffff000 /* phys address of L2 Table */ 257 258 #define L1_F_XSCALE_P 0x00000200 /* ECC enable for this section */ 259 260 /* 261 * ARM L2 Descriptors 262 */ 263 264 #define L2_TYPE_INV 0x00 /* Invalid (fault) */ 265 #define L2_TYPE_L 0x01 /* Large Page */ 266 #define L2_TYPE_S 0x02 /* Small Page */ 267 #define L2_TYPE_T 0x03 /* Tiny Page */ 268 #define L2_TYPE_MASK 0x03 /* mask of type bits */ 269 270 /* 271 * This L2 Descriptor type is available on XScale processors 272 * when using a Coarse L1 Descriptor. The Extended Small 273 * Descriptor has the same format as the XScale Tiny Descriptor, 274 * but describes a 4K page, rather than a 1K page. 275 */ 276 #define L2_TYPE_XSCALE_XS 0x03 /* XScale Extended Small Page */ 277 278 #define L2_B 0x00000004 /* Bufferable page */ 279 #define L2_C 0x00000008 /* Cacheable page */ 280 #define L2_AP0(x) ((x) << 4) /* access permissions (sp 0) */ 281 #define L2_AP1(x) ((x) << 6) /* access permissions (sp 1) */ 282 #define L2_AP2(x) ((x) << 8) /* access permissions (sp 2) */ 283 #define L2_AP3(x) ((x) << 10) /* access permissions (sp 3) */ 284 #define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) 285 286 #define L2_XSCALE_L_TEX(x) ((x) << 12) /* Type Extension */ 287 #define L2_XSCALE_T_TEX(x) ((x) << 6) /* Type Extension */ 288 289 /* 290 * Access Permissions for L1 and L2 Descriptors. 291 */ 292 #define AP_W 0x01 /* writable */ 293 #define AP_U 0x02 /* user */ 294 295 /* 296 * Short-hand for common AP_* constants. 297 * 298 * Note: These values assume the S (System) bit is set and 299 * the R (ROM) bit is clear in CP15 register 1. 300 */ 301 #define AP_KR 0x00 /* kernel read */ 302 #define AP_KRW 0x01 /* kernel read/write */ 303 #define AP_KRWUR 0x02 /* kernel read/write usr read */ 304 #define AP_KRWURW 0x03 /* kernel read/write usr read/write */ 305 306 /* 307 * Domain Types for the Domain Access Control Register. 308 */ 309 #define DOMAIN_FAULT 0x00 /* no access */ 310 #define DOMAIN_CLIENT 0x01 /* client */ 311 #define DOMAIN_RESERVED 0x02 /* reserved */ 312 #define DOMAIN_MANAGER 0x03 /* manager */ 313 314 /* 315 * Type Extension bits for XScale processors. 316 * 317 * Behavior of C and B when X == 0: 318 * 319 * C B Cacheable Bufferable Write Policy Line Allocate Policy 320 * 0 0 N N - - 321 * 0 1 N Y - - 322 * 1 0 Y Y Write-through Read Allocate 323 * 1 1 Y Y Write-back Read Allocate 324 * 325 * Behavior of C and B when X == 1: 326 * C B Cacheable Bufferable Write Policy Line Allocate Policy 327 * 0 0 - - - - DO NOT USE 328 * 0 1 N Y - - 329 * 1 0 Mini-Data - - - 330 * 1 1 Y Y Write-back R/W Allocate 331 */ 332 #define TEX_XSCALE_X 0x01 /* X modifies C and B */ 333 #endif /* !_MACHINE_PTE_H_ */ 334 335 /* End of pte.h */ 336