1 /*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * the Systems Programming Group of the University of Utah Computer 7 * Science Department and William Jolitz of UUNET Technologies Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * Derived from hp300 version by Mike Hibler, this version by William 38 * Jolitz uses a recursive map [a pde points to the page directory] to 39 * map the page tables using the pagetables themselves. This is done to 40 * reduce the impact on kernel virtual memory for lots of sparse address 41 * space, and to reduce the cost of memory to each process. 42 * 43 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90 44 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91 45 * from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30 46 * 47 * $FreeBSD$ 48 */ 49 50 #ifndef _MACHINE_PMAP_H_ 51 #define _MACHINE_PMAP_H_ 52 53 #include <machine/pte.h> 54 #include <machine/cpuconf.h> 55 /* 56 * Pte related macros 57 */ 58 #if ARM_ARCH_6 || ARM_ARCH_7A 59 #ifdef SMP 60 #define PTE_NOCACHE 2 61 #else 62 #define PTE_NOCACHE 1 63 #endif 64 #define PTE_CACHE 6 65 #define PTE_DEVICE 2 66 #define PTE_PAGETABLE 4 67 #else 68 #define PTE_NOCACHE 1 69 #define PTE_CACHE 2 70 #define PTE_PAGETABLE 3 71 #endif 72 73 enum mem_type { 74 STRONG_ORD = 0, 75 DEVICE_NOSHARE, 76 DEVICE_SHARE, 77 NRML_NOCACHE, 78 NRML_IWT_OWT, 79 NRML_IWB_OWB, 80 NRML_IWBA_OWBA 81 }; 82 83 #ifndef LOCORE 84 85 #include <sys/queue.h> 86 #include <sys/_cpuset.h> 87 #include <sys/_lock.h> 88 #include <sys/_mutex.h> 89 90 #define PDESIZE sizeof(pd_entry_t) /* for assembly files */ 91 #define PTESIZE sizeof(pt_entry_t) /* for assembly files */ 92 93 #ifdef _KERNEL 94 95 #define vtophys(va) pmap_kextract((vm_offset_t)(va)) 96 97 #endif 98 99 #define pmap_page_get_memattr(m) ((m)->md.pv_memattr) 100 #define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list)) 101 #define pmap_page_is_write_mapped(m) (((m)->aflags & PGA_WRITEABLE) != 0) 102 void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma); 103 104 /* 105 * Pmap stuff 106 */ 107 108 /* 109 * This structure is used to hold a virtual<->physical address 110 * association and is used mostly by bootstrap code 111 */ 112 struct pv_addr { 113 SLIST_ENTRY(pv_addr) pv_list; 114 vm_offset_t pv_va; 115 vm_paddr_t pv_pa; 116 }; 117 118 struct pv_entry; 119 struct pv_chunk; 120 121 struct md_page { 122 int pvh_attrs; 123 vm_memattr_t pv_memattr; 124 vm_offset_t pv_kva; /* first kernel VA mapping */ 125 TAILQ_HEAD(,pv_entry) pv_list; 126 }; 127 128 struct l1_ttable; 129 struct l2_dtable; 130 131 132 /* 133 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 134 * A bucket size of 16 provides for 16MB of contiguous virtual address 135 * space per l2_dtable. Most processes will, therefore, require only two or 136 * three of these to map their whole working set. 137 */ 138 #define L2_BUCKET_LOG2 4 139 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 140 /* 141 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 142 * of l2_dtable structures required to track all possible page descriptors 143 * mappable by an L1 translation table is given by the following constants: 144 */ 145 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 146 #define L2_SIZE (1 << L2_LOG2) 147 148 struct pmap { 149 struct mtx pm_mtx; 150 u_int8_t pm_domain; 151 struct l1_ttable *pm_l1; 152 struct l2_dtable *pm_l2[L2_SIZE]; 153 pd_entry_t *pm_pdir; /* KVA of page directory */ 154 cpuset_t pm_active; /* active on cpus */ 155 struct pmap_statistics pm_stats; /* pmap statictics */ 156 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0 157 TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */ 158 #else 159 TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */ 160 #endif 161 }; 162 163 typedef struct pmap *pmap_t; 164 165 #ifdef _KERNEL 166 extern struct pmap kernel_pmap_store; 167 #define kernel_pmap (&kernel_pmap_store) 168 #define pmap_kernel() kernel_pmap 169 170 #define PMAP_ASSERT_LOCKED(pmap) \ 171 mtx_assert(&(pmap)->pm_mtx, MA_OWNED) 172 #define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx) 173 #define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx) 174 #define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \ 175 NULL, MTX_DEF | MTX_DUPOK) 176 #define PMAP_OWNED(pmap) mtx_owned(&(pmap)->pm_mtx) 177 #define PMAP_MTX(pmap) (&(pmap)->pm_mtx) 178 #define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx) 179 #define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx) 180 #endif 181 182 183 /* 184 * For each vm_page_t, there is a list of all currently valid virtual 185 * mappings of that page. An entry is a pv_entry_t, the list is pv_list. 186 */ 187 typedef struct pv_entry { 188 vm_offset_t pv_va; /* virtual address for mapping */ 189 TAILQ_ENTRY(pv_entry) pv_list; 190 int pv_flags; /* flags (wired, etc...) */ 191 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0 192 pmap_t pv_pmap; /* pmap where mapping lies */ 193 TAILQ_ENTRY(pv_entry) pv_plist; 194 #endif 195 } *pv_entry_t; 196 197 /* 198 * pv_entries are allocated in chunks per-process. This avoids the 199 * need to track per-pmap assignments. 200 */ 201 #define _NPCM 8 202 #define _NPCPV 252 203 204 struct pv_chunk { 205 pmap_t pc_pmap; 206 TAILQ_ENTRY(pv_chunk) pc_list; 207 uint32_t pc_map[_NPCM]; /* bitmap; 1 = free */ 208 uint32_t pc_dummy[3]; /* aligns pv_chunk to 4KB */ 209 TAILQ_ENTRY(pv_chunk) pc_lru; 210 struct pv_entry pc_pventry[_NPCPV]; 211 }; 212 213 #ifdef _KERNEL 214 215 boolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **); 216 217 /* 218 * virtual address to page table entry and 219 * to physical address. Likewise for alternate address space. 220 * Note: these work recursively, thus vtopte of a pte will give 221 * the corresponding pde that in turn maps it. 222 */ 223 224 /* 225 * The current top of kernel VM. 226 */ 227 extern vm_offset_t pmap_curmaxkvaddr; 228 229 struct pcb; 230 231 void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 232 /* Virtual address to page table entry */ 233 static __inline pt_entry_t * 234 vtopte(vm_offset_t va) 235 { 236 pd_entry_t *pdep; 237 pt_entry_t *ptep; 238 239 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE) 240 return (NULL); 241 return (ptep); 242 } 243 244 extern vm_paddr_t phys_avail[]; 245 extern vm_offset_t virtual_avail; 246 extern vm_offset_t virtual_end; 247 248 void pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt); 249 int pmap_change_attr(vm_offset_t, vm_size_t, int); 250 void pmap_kenter(vm_offset_t va, vm_paddr_t pa); 251 void pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa); 252 void *pmap_kenter_temp(vm_paddr_t pa, int i); 253 void pmap_kenter_user(vm_offset_t va, vm_paddr_t pa); 254 vm_paddr_t pmap_kextract(vm_offset_t va); 255 void pmap_kremove(vm_offset_t); 256 void *pmap_mapdev(vm_offset_t, vm_size_t); 257 void pmap_unmapdev(vm_offset_t, vm_size_t); 258 vm_page_t pmap_use_pt(pmap_t, vm_offset_t); 259 void pmap_debug(int); 260 void pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int); 261 void pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *); 262 vm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int); 263 void 264 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 265 int cache); 266 int pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int); 267 int pmap_dmap_iscurrent(pmap_t pmap); 268 269 /* 270 * Definitions for MMU domains 271 */ 272 #define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */ 273 #define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */ 274 275 /* 276 * The new pmap ensures that page-tables are always mapping Write-Thru. 277 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 278 * on every change. 279 * 280 * Unfortunately, not all CPUs have a write-through cache mode. So we 281 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 282 * and if there is the chance for PTE syncs to be needed, we define 283 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 284 * the code. 285 */ 286 extern int pmap_needs_pte_sync; 287 288 /* 289 * These macros define the various bit masks in the PTE. 290 * 291 * We use these macros since we use different bits on different processor 292 * models. 293 */ 294 295 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 296 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)|\ 297 L1_S_XSCALE_TEX(TEX_XSCALE_T)) 298 299 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 300 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X) | \ 301 L2_XSCALE_L_TEX(TEX_XSCALE_T)) 302 303 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 304 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 305 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W) 306 307 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 308 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 309 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W) 310 311 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 312 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)| \ 313 L2_XSCALE_T_TEX(TEX_XSCALE_X)) 314 315 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 316 #define L1_S_PROTO_xscale (L1_TYPE_S) 317 318 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 319 #define L1_C_PROTO_xscale (L1_TYPE_C) 320 321 #define L2_L_PROTO (L2_TYPE_L) 322 323 #define L2_S_PROTO_generic (L2_TYPE_S) 324 #define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) 325 326 /* 327 * User-visible names for the ones that vary with MMU class. 328 */ 329 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0 330 #define L2_AP(x) (L2_AP0(x)) 331 #else 332 #define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) 333 #endif 334 335 #if ARM_NMMUS > 1 336 /* More than one MMU class configured; use variables. */ 337 #define L2_S_PROT_U pte_l2_s_prot_u 338 #define L2_S_PROT_W pte_l2_s_prot_w 339 #define L2_S_PROT_MASK pte_l2_s_prot_mask 340 341 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 342 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 343 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 344 345 #define L1_S_PROTO pte_l1_s_proto 346 #define L1_C_PROTO pte_l1_c_proto 347 #define L2_S_PROTO pte_l2_s_proto 348 349 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 350 #define L2_S_PROT_U L2_S_PROT_U_generic 351 #define L2_S_PROT_W L2_S_PROT_W_generic 352 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 353 354 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 355 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 356 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 357 358 #define L1_S_PROTO L1_S_PROTO_generic 359 #define L1_C_PROTO L1_C_PROTO_generic 360 #define L2_S_PROTO L2_S_PROTO_generic 361 362 #elif ARM_MMU_XSCALE == 1 363 #define L2_S_PROT_U L2_S_PROT_U_xscale 364 #define L2_S_PROT_W L2_S_PROT_W_xscale 365 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 366 367 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 368 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 369 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 370 371 #define L1_S_PROTO L1_S_PROTO_xscale 372 #define L1_C_PROTO L1_C_PROTO_xscale 373 #define L2_S_PROTO L2_S_PROTO_xscale 374 375 #elif (ARM_MMU_V6 + ARM_MMU_V7) != 0 376 377 #define L2_S_PROT_U (L2_AP0(2)) /* user access */ 378 #define L2_S_PROT_R (L2_AP0(1)) /* read access */ 379 380 #define L2_S_PROT_MASK (L2_S_PROT_U|L2_S_PROT_R) 381 #define L2_S_WRITABLE(pte) (!(pte & L2_APX)) 382 383 #ifndef SMP 384 #define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C) 385 #define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C) 386 #define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C) 387 #else 388 #define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C|L1_SHARED) 389 #define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C|L2_SHARED) 390 #define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C|L2_SHARED) 391 #endif /* SMP */ 392 393 #define L1_S_PROTO (L1_TYPE_S) 394 #define L1_C_PROTO (L1_TYPE_C) 395 #define L2_S_PROTO (L2_TYPE_S) 396 397 #ifndef SMP 398 #define ARM_L1S_STRONG_ORD (0) 399 #define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2)) 400 #define ARM_L1S_DEVICE_SHARE (L1_S_B) 401 #define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)) 402 #define ARM_L1S_NRML_IWT_OWT (L1_S_C) 403 #define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B) 404 #define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B) 405 406 #define ARM_L2L_STRONG_ORD (0) 407 #define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2)) 408 #define ARM_L2L_DEVICE_SHARE (L2_B) 409 #define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)) 410 #define ARM_L2L_NRML_IWT_OWT (L2_C) 411 #define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B) 412 #define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B) 413 414 #define ARM_L2S_STRONG_ORD (0) 415 #define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2)) 416 #define ARM_L2S_DEVICE_SHARE (L2_B) 417 #define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)) 418 #define ARM_L2S_NRML_IWT_OWT (L2_C) 419 #define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B) 420 #define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B) 421 #else 422 #define ARM_L1S_STRONG_ORD (0) 423 #define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2)) 424 #define ARM_L1S_DEVICE_SHARE (L1_S_B) 425 #define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)|L1_SHARED) 426 #define ARM_L1S_NRML_IWT_OWT (L1_S_C|L1_SHARED) 427 #define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B|L1_SHARED) 428 #define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B|L1_SHARED) 429 430 #define ARM_L2L_STRONG_ORD (0) 431 #define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2)) 432 #define ARM_L2L_DEVICE_SHARE (L2_B) 433 #define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)|L2_SHARED) 434 #define ARM_L2L_NRML_IWT_OWT (L2_C|L2_SHARED) 435 #define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED) 436 #define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B|L2_SHARED) 437 438 #define ARM_L2S_STRONG_ORD (0) 439 #define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2)) 440 #define ARM_L2S_DEVICE_SHARE (L2_B) 441 #define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)|L2_SHARED) 442 #define ARM_L2S_NRML_IWT_OWT (L2_C|L2_SHARED) 443 #define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED) 444 #define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B|L2_SHARED) 445 #endif /* SMP */ 446 #endif /* ARM_NMMUS > 1 */ 447 448 #if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1) 449 #define PMAP_NEEDS_PTE_SYNC 1 450 #define PMAP_INCLUDE_PTE_SYNC 451 #elif defined(CPU_XSCALE_81342) 452 #define PMAP_NEEDS_PTE_SYNC 1 453 #define PMAP_INCLUDE_PTE_SYNC 454 #elif (ARM_MMU_SA1 == 0) 455 #define PMAP_NEEDS_PTE_SYNC 0 456 #endif 457 458 /* 459 * These macros return various bits based on kernel/user and protection. 460 * Note that the compiler will usually fold these at compile time. 461 */ 462 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0 463 464 #define L1_S_PROT_U (L1_S_AP(AP_U)) 465 #define L1_S_PROT_W (L1_S_AP(AP_W)) 466 #define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) 467 #define L1_S_WRITABLE(pd) ((pd) & L1_S_PROT_W) 468 469 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 470 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) 471 472 #define L2_L_PROT_U (L2_AP(AP_U)) 473 #define L2_L_PROT_W (L2_AP(AP_W)) 474 #define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) 475 476 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 477 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) 478 479 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 480 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) 481 #else 482 #define L1_S_PROT_U (L1_S_AP(AP_U)) 483 #define L1_S_PROT_MASK (L1_S_APX|L1_S_AP(0x3)) 484 #define L1_S_WRITABLE(pd) (!((pd) & L1_S_APX)) 485 486 #define L1_S_PROT(ku, pr) (L1_S_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L1_S_PROT_U : 0) | \ 487 (((pr) & VM_PROT_WRITE) ? L1_S_APX : 0))) 488 489 #define L2_L_PROT_MASK (L2_APX|L2_AP0(0x3)) 490 #define L2_L_PROT(ku, pr) (L2_L_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \ 491 (((pr) & VM_PROT_WRITE) ? L2_APX : 0))) 492 493 #define L2_S_PROT(ku, pr) (L2_S_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \ 494 (((pr) & VM_PROT_WRITE) ? L2_APX : 0))) 495 496 #endif 497 498 /* 499 * Macros to test if a mapping is mappable with an L1 Section mapping 500 * or an L2 Large Page mapping. 501 */ 502 #define L1_S_MAPPABLE_P(va, pa, size) \ 503 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 504 505 #define L2_L_MAPPABLE_P(va, pa, size) \ 506 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 507 508 /* 509 * Provide a fallback in case we were not able to determine it at 510 * compile-time. 511 */ 512 #ifndef PMAP_NEEDS_PTE_SYNC 513 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 514 #define PMAP_INCLUDE_PTE_SYNC 515 #endif 516 517 #define PTE_SYNC(pte) \ 518 do { \ 519 if (PMAP_NEEDS_PTE_SYNC) { \ 520 cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ 521 cpu_l2cache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ 522 } else \ 523 cpu_drain_writebuf(); \ 524 } while (/*CONSTCOND*/0) 525 526 #define PTE_SYNC_RANGE(pte, cnt) \ 527 do { \ 528 if (PMAP_NEEDS_PTE_SYNC) { \ 529 cpu_dcache_wb_range((vm_offset_t)(pte), \ 530 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 531 cpu_l2cache_wb_range((vm_offset_t)(pte), \ 532 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 533 } else \ 534 cpu_drain_writebuf(); \ 535 } while (/*CONSTCOND*/0) 536 537 extern pt_entry_t pte_l1_s_cache_mode; 538 extern pt_entry_t pte_l1_s_cache_mask; 539 540 extern pt_entry_t pte_l2_l_cache_mode; 541 extern pt_entry_t pte_l2_l_cache_mask; 542 543 extern pt_entry_t pte_l2_s_cache_mode; 544 extern pt_entry_t pte_l2_s_cache_mask; 545 546 extern pt_entry_t pte_l1_s_cache_mode_pt; 547 extern pt_entry_t pte_l2_l_cache_mode_pt; 548 extern pt_entry_t pte_l2_s_cache_mode_pt; 549 550 extern pt_entry_t pte_l2_s_prot_u; 551 extern pt_entry_t pte_l2_s_prot_w; 552 extern pt_entry_t pte_l2_s_prot_mask; 553 554 extern pt_entry_t pte_l1_s_proto; 555 extern pt_entry_t pte_l1_c_proto; 556 extern pt_entry_t pte_l2_s_proto; 557 558 extern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 559 extern void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys, 560 vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs, int cnt); 561 extern void (*pmap_zero_page_func)(vm_paddr_t, int, int); 562 563 #if (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7 + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_81342) 564 void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t); 565 void pmap_zero_page_generic(vm_paddr_t, int, int); 566 567 void pmap_pte_init_generic(void); 568 #if defined(CPU_ARM8) 569 void pmap_pte_init_arm8(void); 570 #endif 571 #if defined(CPU_ARM9) 572 void pmap_pte_init_arm9(void); 573 #endif /* CPU_ARM9 */ 574 #if defined(CPU_ARM10) 575 void pmap_pte_init_arm10(void); 576 #endif /* CPU_ARM10 */ 577 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0 578 void pmap_pte_init_mmu_v6(void); 579 #endif /* (ARM_MMU_V6 + ARM_MMU_V7) != 0 */ 580 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 581 582 #if /* ARM_MMU_SA1 == */1 583 void pmap_pte_init_sa1(void); 584 #endif /* ARM_MMU_SA1 == 1 */ 585 586 #if ARM_MMU_XSCALE == 1 587 void pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t); 588 void pmap_zero_page_xscale(vm_paddr_t, int, int); 589 590 void pmap_pte_init_xscale(void); 591 592 void xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t); 593 594 void pmap_use_minicache(vm_offset_t, vm_size_t); 595 #endif /* ARM_MMU_XSCALE == 1 */ 596 #if defined(CPU_XSCALE_81342) 597 #define ARM_HAVE_SUPERSECTIONS 598 #endif 599 600 #define PTE_KERNEL 0 601 #define PTE_USER 1 602 #define l1pte_valid(pde) ((pde) != 0) 603 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 604 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 605 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 606 607 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 608 #define l2pte_valid(pte) ((pte) != 0) 609 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 610 #define l2pte_minidata(pte) (((pte) & \ 611 (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\ 612 == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X))) 613 614 /* L1 and L2 page table macros */ 615 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 616 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 617 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 618 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 619 620 #define pmap_pte_v(pte) l2pte_valid(*(pte)) 621 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 622 623 /* 624 * Flags that indicate attributes of pages or mappings of pages. 625 * 626 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 627 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 628 * pv_entry's for each page. They live in the same "namespace" so 629 * that we can clear multiple attributes at a time. 630 * 631 * Note the "non-cacheable" flag generally means the page has 632 * multiple mappings in a given address space. 633 */ 634 #define PVF_MOD 0x01 /* page is modified */ 635 #define PVF_REF 0x02 /* page is referenced */ 636 #define PVF_WIRED 0x04 /* mapping is wired */ 637 #define PVF_WRITE 0x08 /* mapping is writable */ 638 #define PVF_EXEC 0x10 /* mapping is executable */ 639 #define PVF_NC 0x20 /* mapping is non-cacheable */ 640 #define PVF_MWC 0x40 /* mapping is used multiple times in userland */ 641 #define PVF_UNMAN 0x80 /* mapping is unmanaged */ 642 643 void vector_page_setprot(int); 644 645 /* 646 * This structure is used by machine-dependent code to describe 647 * static mappings of devices, created at bootstrap time. 648 */ 649 struct pmap_devmap { 650 vm_offset_t pd_va; /* virtual address */ 651 vm_paddr_t pd_pa; /* physical address */ 652 vm_size_t pd_size; /* size of region */ 653 vm_prot_t pd_prot; /* protection code */ 654 int pd_cache; /* cache attributes */ 655 }; 656 657 const struct pmap_devmap *pmap_devmap_find_pa(vm_paddr_t, vm_size_t); 658 const struct pmap_devmap *pmap_devmap_find_va(vm_offset_t, vm_size_t); 659 660 void pmap_devmap_bootstrap(vm_offset_t, const struct pmap_devmap *); 661 void pmap_devmap_register(const struct pmap_devmap *); 662 663 #define SECTION_CACHE 0x1 664 #define SECTION_PT 0x2 665 void pmap_kenter_section(vm_offset_t, vm_paddr_t, int flags); 666 #ifdef ARM_HAVE_SUPERSECTIONS 667 void pmap_kenter_supersection(vm_offset_t, uint64_t, int flags); 668 #endif 669 670 extern char *_tmppt; 671 672 void pmap_postinit(void); 673 674 #ifdef ARM_USE_SMALL_ALLOC 675 void arm_add_smallalloc_pages(void *, void *, int, int); 676 vm_offset_t arm_ptovirt(vm_paddr_t); 677 void arm_init_smallalloc(void); 678 struct arm_small_page { 679 void *addr; 680 TAILQ_ENTRY(arm_small_page) pg_list; 681 }; 682 683 #endif 684 685 #define ARM_NOCACHE_KVA_SIZE 0x1000000 686 extern vm_offset_t arm_nocache_startaddr; 687 void *arm_remap_nocache(void *, vm_size_t); 688 void arm_unmap_nocache(void *, vm_size_t); 689 690 extern vm_paddr_t dump_avail[]; 691 #endif /* _KERNEL */ 692 693 #endif /* !LOCORE */ 694 695 #endif /* !_MACHINE_PMAP_H_ */ 696