1 /*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * the Systems Programming Group of the University of Utah Computer 7 * Science Department and William Jolitz of UUNET Technologies Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * Derived from hp300 version by Mike Hibler, this version by William 38 * Jolitz uses a recursive map [a pde points to the page directory] to 39 * map the page tables using the pagetables themselves. This is done to 40 * reduce the impact on kernel virtual memory for lots of sparse address 41 * space, and to reduce the cost of memory to each process. 42 * 43 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90 44 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91 45 * from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30 46 * 47 * $FreeBSD$ 48 */ 49 50 #ifndef _MACHINE_PMAP_H_ 51 #define _MACHINE_PMAP_H_ 52 53 #include <machine/pte.h> 54 #include <machine/cpuconf.h> 55 /* 56 * Pte related macros 57 */ 58 #if ARM_ARCH_6 || ARM_ARCH_7A 59 #ifdef SMP 60 #define PTE_NOCACHE 2 61 #else 62 #define PTE_NOCACHE 1 63 #endif 64 #define PTE_CACHE 6 65 #define PTE_DEVICE 2 66 #define PTE_PAGETABLE 4 67 #else 68 #define PTE_NOCACHE 1 69 #define PTE_CACHE 2 70 #define PTE_PAGETABLE 3 71 #endif 72 73 enum mem_type { 74 STRONG_ORD = 0, 75 DEVICE_NOSHARE, 76 DEVICE_SHARE, 77 NRML_NOCACHE, 78 NRML_IWT_OWT, 79 NRML_IWB_OWB, 80 NRML_IWBA_OWBA 81 }; 82 83 #ifndef LOCORE 84 85 #include <sys/queue.h> 86 #include <sys/_cpuset.h> 87 #include <sys/_lock.h> 88 #include <sys/_mutex.h> 89 90 #define PDESIZE sizeof(pd_entry_t) /* for assembly files */ 91 #define PTESIZE sizeof(pt_entry_t) /* for assembly files */ 92 93 #ifdef _KERNEL 94 95 #define vtophys(va) pmap_kextract((vm_offset_t)(va)) 96 97 #endif 98 99 #define pmap_page_get_memattr(m) ((m)->md.pv_memattr) 100 #define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list)) 101 #define pmap_page_is_write_mapped(m) (((m)->aflags & PGA_WRITEABLE) != 0) 102 void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma); 103 104 /* 105 * Pmap stuff 106 */ 107 108 /* 109 * This structure is used to hold a virtual<->physical address 110 * association and is used mostly by bootstrap code 111 */ 112 struct pv_addr { 113 SLIST_ENTRY(pv_addr) pv_list; 114 vm_offset_t pv_va; 115 vm_paddr_t pv_pa; 116 }; 117 118 struct pv_entry; 119 120 struct md_page { 121 int pvh_attrs; 122 vm_memattr_t pv_memattr; 123 vm_offset_t pv_kva; /* first kernel VA mapping */ 124 TAILQ_HEAD(,pv_entry) pv_list; 125 }; 126 127 struct l1_ttable; 128 struct l2_dtable; 129 130 131 /* 132 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 133 * A bucket size of 16 provides for 16MB of contiguous virtual address 134 * space per l2_dtable. Most processes will, therefore, require only two or 135 * three of these to map their whole working set. 136 */ 137 #define L2_BUCKET_LOG2 4 138 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 139 /* 140 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 141 * of l2_dtable structures required to track all possible page descriptors 142 * mappable by an L1 translation table is given by the following constants: 143 */ 144 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 145 #define L2_SIZE (1 << L2_LOG2) 146 147 struct pmap { 148 struct mtx pm_mtx; 149 u_int8_t pm_domain; 150 struct l1_ttable *pm_l1; 151 struct l2_dtable *pm_l2[L2_SIZE]; 152 pd_entry_t *pm_pdir; /* KVA of page directory */ 153 cpuset_t pm_active; /* active on cpus */ 154 struct pmap_statistics pm_stats; /* pmap statictics */ 155 TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */ 156 }; 157 158 typedef struct pmap *pmap_t; 159 160 #ifdef _KERNEL 161 extern struct pmap kernel_pmap_store; 162 #define kernel_pmap (&kernel_pmap_store) 163 #define pmap_kernel() kernel_pmap 164 165 #define PMAP_ASSERT_LOCKED(pmap) \ 166 mtx_assert(&(pmap)->pm_mtx, MA_OWNED) 167 #define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx) 168 #define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx) 169 #define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \ 170 NULL, MTX_DEF | MTX_DUPOK) 171 #define PMAP_OWNED(pmap) mtx_owned(&(pmap)->pm_mtx) 172 #define PMAP_MTX(pmap) (&(pmap)->pm_mtx) 173 #define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx) 174 #define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx) 175 #endif 176 177 178 /* 179 * For each vm_page_t, there is a list of all currently valid virtual 180 * mappings of that page. An entry is a pv_entry_t, the list is pv_list. 181 */ 182 typedef struct pv_entry { 183 pmap_t pv_pmap; /* pmap where mapping lies */ 184 vm_offset_t pv_va; /* virtual address for mapping */ 185 TAILQ_ENTRY(pv_entry) pv_list; 186 TAILQ_ENTRY(pv_entry) pv_plist; 187 int pv_flags; /* flags (wired, etc...) */ 188 } *pv_entry_t; 189 190 #ifdef _KERNEL 191 192 boolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **); 193 194 /* 195 * virtual address to page table entry and 196 * to physical address. Likewise for alternate address space. 197 * Note: these work recursively, thus vtopte of a pte will give 198 * the corresponding pde that in turn maps it. 199 */ 200 201 /* 202 * The current top of kernel VM. 203 */ 204 extern vm_offset_t pmap_curmaxkvaddr; 205 206 struct pcb; 207 208 void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 209 /* Virtual address to page table entry */ 210 static __inline pt_entry_t * 211 vtopte(vm_offset_t va) 212 { 213 pd_entry_t *pdep; 214 pt_entry_t *ptep; 215 216 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE) 217 return (NULL); 218 return (ptep); 219 } 220 221 extern vm_paddr_t phys_avail[]; 222 extern vm_offset_t virtual_avail; 223 extern vm_offset_t virtual_end; 224 225 void pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt); 226 int pmap_change_attr(vm_offset_t, vm_size_t, int); 227 void pmap_kenter(vm_offset_t va, vm_paddr_t pa); 228 void pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa); 229 void *pmap_kenter_temp(vm_paddr_t pa, int i); 230 void pmap_kenter_user(vm_offset_t va, vm_paddr_t pa); 231 vm_paddr_t pmap_kextract(vm_offset_t va); 232 void pmap_kremove(vm_offset_t); 233 void *pmap_mapdev(vm_offset_t, vm_size_t); 234 void pmap_unmapdev(vm_offset_t, vm_size_t); 235 vm_page_t pmap_use_pt(pmap_t, vm_offset_t); 236 void pmap_debug(int); 237 void pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int); 238 void pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *); 239 vm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int); 240 void 241 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 242 int cache); 243 int pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int); 244 int pmap_dmap_iscurrent(pmap_t pmap); 245 246 /* 247 * Definitions for MMU domains 248 */ 249 #define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */ 250 #define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */ 251 252 /* 253 * The new pmap ensures that page-tables are always mapping Write-Thru. 254 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 255 * on every change. 256 * 257 * Unfortunately, not all CPUs have a write-through cache mode. So we 258 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 259 * and if there is the chance for PTE syncs to be needed, we define 260 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 261 * the code. 262 */ 263 extern int pmap_needs_pte_sync; 264 265 /* 266 * These macros define the various bit masks in the PTE. 267 * 268 * We use these macros since we use different bits on different processor 269 * models. 270 */ 271 272 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 273 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)|\ 274 L1_S_XSCALE_TEX(TEX_XSCALE_T)) 275 276 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 277 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X) | \ 278 L2_XSCALE_L_TEX(TEX_XSCALE_T)) 279 280 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 281 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 282 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W) 283 284 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 285 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 286 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W) 287 288 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 289 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)| \ 290 L2_XSCALE_T_TEX(TEX_XSCALE_X)) 291 292 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 293 #define L1_S_PROTO_xscale (L1_TYPE_S) 294 295 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 296 #define L1_C_PROTO_xscale (L1_TYPE_C) 297 298 #define L2_L_PROTO (L2_TYPE_L) 299 300 #define L2_S_PROTO_generic (L2_TYPE_S) 301 #define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) 302 303 /* 304 * User-visible names for the ones that vary with MMU class. 305 */ 306 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0 307 #define L2_AP(x) (L2_AP0(x)) 308 #else 309 #define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) 310 #endif 311 312 #if ARM_NMMUS > 1 313 /* More than one MMU class configured; use variables. */ 314 #define L2_S_PROT_U pte_l2_s_prot_u 315 #define L2_S_PROT_W pte_l2_s_prot_w 316 #define L2_S_PROT_MASK pte_l2_s_prot_mask 317 318 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 319 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 320 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 321 322 #define L1_S_PROTO pte_l1_s_proto 323 #define L1_C_PROTO pte_l1_c_proto 324 #define L2_S_PROTO pte_l2_s_proto 325 326 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 327 #define L2_S_PROT_U L2_S_PROT_U_generic 328 #define L2_S_PROT_W L2_S_PROT_W_generic 329 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 330 331 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 332 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 333 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 334 335 #define L1_S_PROTO L1_S_PROTO_generic 336 #define L1_C_PROTO L1_C_PROTO_generic 337 #define L2_S_PROTO L2_S_PROTO_generic 338 339 #elif ARM_MMU_XSCALE == 1 340 #define L2_S_PROT_U L2_S_PROT_U_xscale 341 #define L2_S_PROT_W L2_S_PROT_W_xscale 342 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 343 344 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 345 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 346 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 347 348 #define L1_S_PROTO L1_S_PROTO_xscale 349 #define L1_C_PROTO L1_C_PROTO_xscale 350 #define L2_S_PROTO L2_S_PROTO_xscale 351 352 #elif (ARM_MMU_V6 + ARM_MMU_V7) != 0 353 354 #define L2_S_PROT_U (L2_AP0(2)) /* user access */ 355 #define L2_S_PROT_R (L2_APX|L2_AP0(1)) /* read access */ 356 357 #define L2_S_PROT_MASK (L2_S_PROT_U|L2_S_PROT_R) 358 #define L2_S_WRITABLE(pte) (!(pte & L2_APX)) 359 360 #ifndef SMP 361 #define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C) 362 #define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C) 363 #define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C) 364 #else 365 #define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C|L1_SHARED) 366 #define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C|L2_SHARED) 367 #define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C|L2_SHARED) 368 #endif /* SMP */ 369 370 #define L1_S_PROTO (L1_TYPE_S) 371 #define L1_C_PROTO (L1_TYPE_C) 372 #define L2_S_PROTO (L2_TYPE_S) 373 374 #ifndef SMP 375 #define ARM_L1S_STRONG_ORD (0) 376 #define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2)) 377 #define ARM_L1S_DEVICE_SHARE (L1_S_B) 378 #define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)) 379 #define ARM_L1S_NRML_IWT_OWT (L1_S_C) 380 #define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B) 381 #define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B) 382 383 #define ARM_L2L_STRONG_ORD (0) 384 #define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2)) 385 #define ARM_L2L_DEVICE_SHARE (L2_B) 386 #define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)) 387 #define ARM_L2L_NRML_IWT_OWT (L2_C) 388 #define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B) 389 #define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B) 390 391 #define ARM_L2S_STRONG_ORD (0) 392 #define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2)) 393 #define ARM_L2S_DEVICE_SHARE (L2_B) 394 #define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)) 395 #define ARM_L2S_NRML_IWT_OWT (L2_C) 396 #define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B) 397 #define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B) 398 #else 399 #define ARM_L1S_STRONG_ORD (0) 400 #define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2)) 401 #define ARM_L1S_DEVICE_SHARE (L1_S_B) 402 #define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)|L1_SHARED) 403 #define ARM_L1S_NRML_IWT_OWT (L1_S_C|L1_SHARED) 404 #define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B|L1_SHARED) 405 #define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B|L1_SHARED) 406 407 #define ARM_L2L_STRONG_ORD (0) 408 #define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2)) 409 #define ARM_L2L_DEVICE_SHARE (L2_B) 410 #define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)|L2_SHARED) 411 #define ARM_L2L_NRML_IWT_OWT (L2_C|L2_SHARED) 412 #define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED) 413 #define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B|L2_SHARED) 414 415 #define ARM_L2S_STRONG_ORD (0) 416 #define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2)) 417 #define ARM_L2S_DEVICE_SHARE (L2_B) 418 #define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)|L2_SHARED) 419 #define ARM_L2S_NRML_IWT_OWT (L2_C|L2_SHARED) 420 #define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED) 421 #define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B|L2_SHARED) 422 #endif /* SMP */ 423 #endif /* ARM_NMMUS > 1 */ 424 425 #if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1) 426 #define PMAP_NEEDS_PTE_SYNC 1 427 #define PMAP_INCLUDE_PTE_SYNC 428 #elif defined(CPU_XSCALE_81342) 429 #define PMAP_NEEDS_PTE_SYNC 1 430 #define PMAP_INCLUDE_PTE_SYNC 431 #elif (ARM_MMU_SA1 == 0) 432 #define PMAP_NEEDS_PTE_SYNC 0 433 #endif 434 435 /* 436 * These macros return various bits based on kernel/user and protection. 437 * Note that the compiler will usually fold these at compile time. 438 */ 439 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0 440 441 #define L1_S_PROT_U (L1_S_AP(AP_U)) 442 #define L1_S_PROT_W (L1_S_AP(AP_W)) 443 #define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) 444 #define L1_S_WRITABLE(pd) ((pd) & L1_S_PROT_W) 445 446 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 447 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) 448 449 #define L2_L_PROT_U (L2_AP(AP_U)) 450 #define L2_L_PROT_W (L2_AP(AP_W)) 451 #define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) 452 453 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 454 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) 455 456 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 457 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) 458 #else 459 #define L1_S_PROT_U (L1_S_AP(AP_U)) 460 #define L1_S_PROT_MASK (L1_S_APX|L1_S_AP(0x3)) 461 #define L1_S_WRITABLE(pd) (!((pd) & L1_S_APX)) 462 463 #define L1_S_PROT(ku, pr) (L1_S_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L1_S_PROT_U : 0) | \ 464 (((pr) & VM_PROT_WRITE) ? L1_S_APX : 0))) 465 466 #define L2_L_PROT_MASK (L2_APX|L2_AP0(0x3)) 467 #define L2_L_PROT(ku, pr) (L2_L_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \ 468 (((pr) & VM_PROT_WRITE) ? L2_APX : 0))) 469 470 #define L2_S_PROT(ku, pr) (L2_S_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \ 471 (((pr) & VM_PROT_WRITE) ? L2_APX : 0))) 472 473 #endif 474 475 /* 476 * Macros to test if a mapping is mappable with an L1 Section mapping 477 * or an L2 Large Page mapping. 478 */ 479 #define L1_S_MAPPABLE_P(va, pa, size) \ 480 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 481 482 #define L2_L_MAPPABLE_P(va, pa, size) \ 483 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 484 485 /* 486 * Provide a fallback in case we were not able to determine it at 487 * compile-time. 488 */ 489 #ifndef PMAP_NEEDS_PTE_SYNC 490 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 491 #define PMAP_INCLUDE_PTE_SYNC 492 #endif 493 494 #define PTE_SYNC(pte) \ 495 do { \ 496 if (PMAP_NEEDS_PTE_SYNC) { \ 497 cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ 498 cpu_l2cache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ 499 } else \ 500 cpu_drain_writebuf(); \ 501 } while (/*CONSTCOND*/0) 502 503 #define PTE_SYNC_RANGE(pte, cnt) \ 504 do { \ 505 if (PMAP_NEEDS_PTE_SYNC) { \ 506 cpu_dcache_wb_range((vm_offset_t)(pte), \ 507 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 508 cpu_l2cache_wb_range((vm_offset_t)(pte), \ 509 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 510 } else \ 511 cpu_drain_writebuf(); \ 512 } while (/*CONSTCOND*/0) 513 514 extern pt_entry_t pte_l1_s_cache_mode; 515 extern pt_entry_t pte_l1_s_cache_mask; 516 517 extern pt_entry_t pte_l2_l_cache_mode; 518 extern pt_entry_t pte_l2_l_cache_mask; 519 520 extern pt_entry_t pte_l2_s_cache_mode; 521 extern pt_entry_t pte_l2_s_cache_mask; 522 523 extern pt_entry_t pte_l1_s_cache_mode_pt; 524 extern pt_entry_t pte_l2_l_cache_mode_pt; 525 extern pt_entry_t pte_l2_s_cache_mode_pt; 526 527 extern pt_entry_t pte_l2_s_prot_u; 528 extern pt_entry_t pte_l2_s_prot_w; 529 extern pt_entry_t pte_l2_s_prot_mask; 530 531 extern pt_entry_t pte_l1_s_proto; 532 extern pt_entry_t pte_l1_c_proto; 533 extern pt_entry_t pte_l2_s_proto; 534 535 extern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 536 extern void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys, 537 vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs, int cnt); 538 extern void (*pmap_zero_page_func)(vm_paddr_t, int, int); 539 540 #if (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7 + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_81342) 541 void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t); 542 void pmap_zero_page_generic(vm_paddr_t, int, int); 543 544 void pmap_pte_init_generic(void); 545 #if defined(CPU_ARM8) 546 void pmap_pte_init_arm8(void); 547 #endif 548 #if defined(CPU_ARM9) 549 void pmap_pte_init_arm9(void); 550 #endif /* CPU_ARM9 */ 551 #if defined(CPU_ARM10) 552 void pmap_pte_init_arm10(void); 553 #endif /* CPU_ARM10 */ 554 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0 555 void pmap_pte_init_mmu_v6(void); 556 #endif /* (ARM_MMU_V6 + ARM_MMU_V7) != 0 */ 557 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 558 559 #if /* ARM_MMU_SA1 == */1 560 void pmap_pte_init_sa1(void); 561 #endif /* ARM_MMU_SA1 == 1 */ 562 563 #if ARM_MMU_XSCALE == 1 564 void pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t); 565 void pmap_zero_page_xscale(vm_paddr_t, int, int); 566 567 void pmap_pte_init_xscale(void); 568 569 void xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t); 570 571 void pmap_use_minicache(vm_offset_t, vm_size_t); 572 #endif /* ARM_MMU_XSCALE == 1 */ 573 #if defined(CPU_XSCALE_81342) 574 #define ARM_HAVE_SUPERSECTIONS 575 #endif 576 577 #define PTE_KERNEL 0 578 #define PTE_USER 1 579 #define l1pte_valid(pde) ((pde) != 0) 580 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 581 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 582 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 583 584 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 585 #define l2pte_valid(pte) ((pte) != 0) 586 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 587 #define l2pte_minidata(pte) (((pte) & \ 588 (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\ 589 == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X))) 590 591 /* L1 and L2 page table macros */ 592 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 593 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 594 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 595 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 596 597 #define pmap_pte_v(pte) l2pte_valid(*(pte)) 598 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 599 600 /* 601 * Flags that indicate attributes of pages or mappings of pages. 602 * 603 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 604 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 605 * pv_entry's for each page. They live in the same "namespace" so 606 * that we can clear multiple attributes at a time. 607 * 608 * Note the "non-cacheable" flag generally means the page has 609 * multiple mappings in a given address space. 610 */ 611 #define PVF_MOD 0x01 /* page is modified */ 612 #define PVF_REF 0x02 /* page is referenced */ 613 #define PVF_WIRED 0x04 /* mapping is wired */ 614 #define PVF_WRITE 0x08 /* mapping is writable */ 615 #define PVF_EXEC 0x10 /* mapping is executable */ 616 #define PVF_NC 0x20 /* mapping is non-cacheable */ 617 #define PVF_MWC 0x40 /* mapping is used multiple times in userland */ 618 #define PVF_UNMAN 0x80 /* mapping is unmanaged */ 619 620 void vector_page_setprot(int); 621 622 /* 623 * This structure is used by machine-dependent code to describe 624 * static mappings of devices, created at bootstrap time. 625 */ 626 struct pmap_devmap { 627 vm_offset_t pd_va; /* virtual address */ 628 vm_paddr_t pd_pa; /* physical address */ 629 vm_size_t pd_size; /* size of region */ 630 vm_prot_t pd_prot; /* protection code */ 631 int pd_cache; /* cache attributes */ 632 }; 633 634 const struct pmap_devmap *pmap_devmap_find_pa(vm_paddr_t, vm_size_t); 635 const struct pmap_devmap *pmap_devmap_find_va(vm_offset_t, vm_size_t); 636 637 void pmap_devmap_bootstrap(vm_offset_t, const struct pmap_devmap *); 638 void pmap_devmap_register(const struct pmap_devmap *); 639 640 #define SECTION_CACHE 0x1 641 #define SECTION_PT 0x2 642 void pmap_kenter_section(vm_offset_t, vm_paddr_t, int flags); 643 #ifdef ARM_HAVE_SUPERSECTIONS 644 void pmap_kenter_supersection(vm_offset_t, uint64_t, int flags); 645 #endif 646 647 extern char *_tmppt; 648 649 void pmap_postinit(void); 650 651 #ifdef ARM_USE_SMALL_ALLOC 652 void arm_add_smallalloc_pages(void *, void *, int, int); 653 vm_offset_t arm_ptovirt(vm_paddr_t); 654 void arm_init_smallalloc(void); 655 struct arm_small_page { 656 void *addr; 657 TAILQ_ENTRY(arm_small_page) pg_list; 658 }; 659 660 #endif 661 662 #define ARM_NOCACHE_KVA_SIZE 0x1000000 663 extern vm_offset_t arm_nocache_startaddr; 664 void *arm_remap_nocache(void *, vm_size_t); 665 void arm_unmap_nocache(void *, vm_size_t); 666 667 extern vm_paddr_t dump_avail[]; 668 #endif /* _KERNEL */ 669 670 #endif /* !LOCORE */ 671 672 #endif /* !_MACHINE_PMAP_H_ */ 673