1 /*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * the Systems Programming Group of the University of Utah Computer 7 * Science Department and William Jolitz of UUNET Technologies Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * Derived from hp300 version by Mike Hibler, this version by William 38 * Jolitz uses a recursive map [a pde points to the page directory] to 39 * map the page tables using the pagetables themselves. This is done to 40 * reduce the impact on kernel virtual memory for lots of sparse address 41 * space, and to reduce the cost of memory to each process. 42 * 43 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90 44 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91 45 * from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30 46 * 47 * $FreeBSD$ 48 */ 49 #include <machine/acle-compat.h> 50 51 #if __ARM_ARCH >= 6 52 #include <machine/pmap-v6.h> 53 #else /* __ARM_ARCH >= 6 */ 54 55 #ifndef _MACHINE_PMAP_H_ 56 #define _MACHINE_PMAP_H_ 57 58 #include <machine/pte.h> 59 #include <machine/cpuconf.h> 60 /* 61 * Pte related macros 62 */ 63 #if ARM_ARCH_6 || ARM_ARCH_7A 64 #ifdef SMP 65 #define PTE_NOCACHE 2 66 #else 67 #define PTE_NOCACHE 1 68 #endif 69 #define PTE_CACHE 6 70 #define PTE_DEVICE 2 71 #define PTE_PAGETABLE 6 72 #else 73 #define PTE_NOCACHE 1 74 #define PTE_CACHE 2 75 #define PTE_DEVICE PTE_NOCACHE 76 #define PTE_PAGETABLE 3 77 #endif 78 79 enum mem_type { 80 STRONG_ORD = 0, 81 DEVICE_NOSHARE, 82 DEVICE_SHARE, 83 NRML_NOCACHE, 84 NRML_IWT_OWT, 85 NRML_IWB_OWB, 86 NRML_IWBA_OWBA 87 }; 88 89 #ifndef LOCORE 90 91 #include <sys/queue.h> 92 #include <sys/_cpuset.h> 93 #include <sys/_lock.h> 94 #include <sys/_mutex.h> 95 96 #define PDESIZE sizeof(pd_entry_t) /* for assembly files */ 97 #define PTESIZE sizeof(pt_entry_t) /* for assembly files */ 98 99 #ifdef _KERNEL 100 101 #define vtophys(va) pmap_kextract((vm_offset_t)(va)) 102 103 #endif 104 105 #define pmap_page_get_memattr(m) ((m)->md.pv_memattr) 106 #define pmap_page_is_write_mapped(m) (((m)->aflags & PGA_WRITEABLE) != 0) 107 #if (ARM_MMU_V6 + ARM_MMU_V7) > 0 108 boolean_t pmap_page_is_mapped(vm_page_t); 109 #else 110 #define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list)) 111 #endif 112 void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma); 113 114 /* 115 * Pmap stuff 116 */ 117 118 /* 119 * This structure is used to hold a virtual<->physical address 120 * association and is used mostly by bootstrap code 121 */ 122 struct pv_addr { 123 SLIST_ENTRY(pv_addr) pv_list; 124 vm_offset_t pv_va; 125 vm_paddr_t pv_pa; 126 }; 127 128 struct pv_entry; 129 struct pv_chunk; 130 131 struct md_page { 132 int pvh_attrs; 133 vm_memattr_t pv_memattr; 134 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0 135 vm_offset_t pv_kva; /* first kernel VA mapping */ 136 #endif 137 TAILQ_HEAD(,pv_entry) pv_list; 138 }; 139 140 struct l1_ttable; 141 struct l2_dtable; 142 143 144 /* 145 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 146 * A bucket size of 16 provides for 16MB of contiguous virtual address 147 * space per l2_dtable. Most processes will, therefore, require only two or 148 * three of these to map their whole working set. 149 */ 150 #define L2_BUCKET_LOG2 4 151 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 152 /* 153 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 154 * of l2_dtable structures required to track all possible page descriptors 155 * mappable by an L1 translation table is given by the following constants: 156 */ 157 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 158 #define L2_SIZE (1 << L2_LOG2) 159 160 struct pmap { 161 struct mtx pm_mtx; 162 u_int8_t pm_domain; 163 struct l1_ttable *pm_l1; 164 struct l2_dtable *pm_l2[L2_SIZE]; 165 cpuset_t pm_active; /* active on cpus */ 166 struct pmap_statistics pm_stats; /* pmap statictics */ 167 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0 168 TAILQ_HEAD(,pv_chunk) pm_pvchunk; /* list of mappings in pmap */ 169 #else 170 TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */ 171 #endif 172 }; 173 174 typedef struct pmap *pmap_t; 175 176 #ifdef _KERNEL 177 extern struct pmap kernel_pmap_store; 178 #define kernel_pmap (&kernel_pmap_store) 179 180 #define PMAP_ASSERT_LOCKED(pmap) \ 181 mtx_assert(&(pmap)->pm_mtx, MA_OWNED) 182 #define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx) 183 #define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx) 184 #define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \ 185 NULL, MTX_DEF | MTX_DUPOK) 186 #define PMAP_OWNED(pmap) mtx_owned(&(pmap)->pm_mtx) 187 #define PMAP_MTX(pmap) (&(pmap)->pm_mtx) 188 #define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx) 189 #define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx) 190 #endif 191 192 193 /* 194 * For each vm_page_t, there is a list of all currently valid virtual 195 * mappings of that page. An entry is a pv_entry_t, the list is pv_list. 196 */ 197 typedef struct pv_entry { 198 vm_offset_t pv_va; /* virtual address for mapping */ 199 TAILQ_ENTRY(pv_entry) pv_list; 200 int pv_flags; /* flags (wired, etc...) */ 201 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0 202 pmap_t pv_pmap; /* pmap where mapping lies */ 203 TAILQ_ENTRY(pv_entry) pv_plist; 204 #endif 205 } *pv_entry_t; 206 207 /* 208 * pv_entries are allocated in chunks per-process. This avoids the 209 * need to track per-pmap assignments. 210 */ 211 #define _NPCM 8 212 #define _NPCPV 252 213 214 struct pv_chunk { 215 pmap_t pc_pmap; 216 TAILQ_ENTRY(pv_chunk) pc_list; 217 uint32_t pc_map[_NPCM]; /* bitmap; 1 = free */ 218 uint32_t pc_dummy[3]; /* aligns pv_chunk to 4KB */ 219 TAILQ_ENTRY(pv_chunk) pc_lru; 220 struct pv_entry pc_pventry[_NPCPV]; 221 }; 222 223 #ifdef _KERNEL 224 225 boolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **); 226 227 /* 228 * virtual address to page table entry and 229 * to physical address. Likewise for alternate address space. 230 * Note: these work recursively, thus vtopte of a pte will give 231 * the corresponding pde that in turn maps it. 232 */ 233 234 /* 235 * The current top of kernel VM. 236 */ 237 extern vm_offset_t pmap_curmaxkvaddr; 238 239 struct pcb; 240 241 void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 242 /* Virtual address to page table entry */ 243 static __inline pt_entry_t * 244 vtopte(vm_offset_t va) 245 { 246 pd_entry_t *pdep; 247 pt_entry_t *ptep; 248 249 if (pmap_get_pde_pte(kernel_pmap, va, &pdep, &ptep) == FALSE) 250 return (NULL); 251 return (ptep); 252 } 253 254 extern vm_paddr_t phys_avail[]; 255 extern vm_offset_t virtual_avail; 256 extern vm_offset_t virtual_end; 257 258 void pmap_bootstrap(vm_offset_t firstaddr, struct pv_addr *l1pt); 259 int pmap_change_attr(vm_offset_t, vm_size_t, int); 260 void pmap_kenter(vm_offset_t va, vm_paddr_t pa); 261 void pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa); 262 void pmap_kenter_device(vm_offset_t, vm_size_t, vm_paddr_t); 263 void pmap_kremove_device(vm_offset_t, vm_size_t); 264 void *pmap_kenter_temporary(vm_paddr_t pa, int i); 265 void pmap_kenter_user(vm_offset_t va, vm_paddr_t pa); 266 vm_paddr_t pmap_kextract(vm_offset_t va); 267 vm_paddr_t pmap_dump_kextract(vm_offset_t, pt2_entry_t *); 268 void pmap_kremove(vm_offset_t); 269 void *pmap_mapdev(vm_offset_t, vm_size_t); 270 void pmap_unmapdev(vm_offset_t, vm_size_t); 271 vm_page_t pmap_use_pt(pmap_t, vm_offset_t); 272 void pmap_debug(int); 273 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0 274 void pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int); 275 #endif 276 void pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *); 277 vm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int); 278 void 279 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 280 int cache); 281 int pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int); 282 283 /* 284 * Definitions for MMU domains 285 */ 286 #define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */ 287 #define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */ 288 289 /* 290 * The new pmap ensures that page-tables are always mapping Write-Thru. 291 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 292 * on every change. 293 * 294 * Unfortunately, not all CPUs have a write-through cache mode. So we 295 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 296 * and if there is the chance for PTE syncs to be needed, we define 297 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 298 * the code. 299 */ 300 extern int pmap_needs_pte_sync; 301 302 /* 303 * These macros define the various bit masks in the PTE. 304 * 305 * We use these macros since we use different bits on different processor 306 * models. 307 */ 308 309 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 310 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)|\ 311 L1_S_XSCALE_TEX(TEX_XSCALE_T)) 312 313 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 314 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X) | \ 315 L2_XSCALE_L_TEX(TEX_XSCALE_T)) 316 317 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 318 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 319 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W) 320 321 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 322 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 323 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W) 324 325 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 326 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)| \ 327 L2_XSCALE_T_TEX(TEX_XSCALE_X)) 328 329 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 330 #define L1_S_PROTO_xscale (L1_TYPE_S) 331 332 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 333 #define L1_C_PROTO_xscale (L1_TYPE_C) 334 335 #define L2_L_PROTO (L2_TYPE_L) 336 337 #define L2_S_PROTO_generic (L2_TYPE_S) 338 #define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) 339 340 /* 341 * User-visible names for the ones that vary with MMU class. 342 */ 343 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0 344 #define L2_AP(x) (L2_AP0(x)) 345 #else 346 #define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) 347 #endif 348 349 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0 350 /* 351 * AP[2:1] access permissions model: 352 * 353 * AP[2](APX) - Write Disable 354 * AP[1] - User Enable 355 * AP[0] - Reference Flag 356 * 357 * AP[2] AP[1] Kernel User 358 * 0 0 R/W N 359 * 0 1 R/W R/W 360 * 1 0 R N 361 * 1 1 R R 362 * 363 */ 364 #define L2_S_PROT_R (0) /* kernel read */ 365 #define L2_S_PROT_U (L2_AP0(2)) /* user read */ 366 #define L2_S_REF (L2_AP0(1)) /* reference flag */ 367 368 #define L2_S_PROT_MASK (L2_S_PROT_U|L2_S_PROT_R|L2_APX) 369 #define L2_S_EXECUTABLE(pte) (!(pte & L2_XN)) 370 #define L2_S_WRITABLE(pte) (!(pte & L2_APX)) 371 #define L2_S_REFERENCED(pte) (!!(pte & L2_S_REF)) 372 373 #ifndef SMP 374 #define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C) 375 #define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C) 376 #define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C) 377 #else 378 #define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C|L1_SHARED) 379 #define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C|L2_SHARED) 380 #define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C|L2_SHARED) 381 #endif /* SMP */ 382 383 #define L1_S_PROTO (L1_TYPE_S) 384 #define L1_C_PROTO (L1_TYPE_C) 385 #define L2_S_PROTO (L2_TYPE_S) 386 387 /* 388 * Promotion to a 1MB (SECTION) mapping requires that the corresponding 389 * 4KB (SMALL) page mappings have identical settings for the following fields: 390 */ 391 #define L2_S_PROMOTE (L2_S_REF | L2_SHARED | L2_S_PROT_MASK | \ 392 L2_XN | L2_S_PROTO) 393 394 /* 395 * In order to compare 1MB (SECTION) entry settings with the 4KB (SMALL) 396 * page mapping it is necessary to read and shift appropriate bits from 397 * L1 entry to positions of the corresponding bits in the L2 entry. 398 */ 399 #define L1_S_DEMOTE(l1pd) ((((l1pd) & L1_S_PROTO) >> 0) | \ 400 (((l1pd) & L1_SHARED) >> 6) | \ 401 (((l1pd) & L1_S_REF) >> 6) | \ 402 (((l1pd) & L1_S_PROT_MASK) >> 6) | \ 403 (((l1pd) & L1_S_XN) >> 4)) 404 405 #ifndef SMP 406 #define ARM_L1S_STRONG_ORD (0) 407 #define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2)) 408 #define ARM_L1S_DEVICE_SHARE (L1_S_B) 409 #define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)) 410 #define ARM_L1S_NRML_IWT_OWT (L1_S_C) 411 #define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B) 412 #define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B) 413 414 #define ARM_L2L_STRONG_ORD (0) 415 #define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2)) 416 #define ARM_L2L_DEVICE_SHARE (L2_B) 417 #define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)) 418 #define ARM_L2L_NRML_IWT_OWT (L2_C) 419 #define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B) 420 #define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B) 421 422 #define ARM_L2S_STRONG_ORD (0) 423 #define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2)) 424 #define ARM_L2S_DEVICE_SHARE (L2_B) 425 #define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)) 426 #define ARM_L2S_NRML_IWT_OWT (L2_C) 427 #define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B) 428 #define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B) 429 #else 430 #define ARM_L1S_STRONG_ORD (0) 431 #define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2)) 432 #define ARM_L1S_DEVICE_SHARE (L1_S_B) 433 #define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)|L1_SHARED) 434 #define ARM_L1S_NRML_IWT_OWT (L1_S_C|L1_SHARED) 435 #define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B|L1_SHARED) 436 #define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B|L1_SHARED) 437 438 #define ARM_L2L_STRONG_ORD (0) 439 #define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2)) 440 #define ARM_L2L_DEVICE_SHARE (L2_B) 441 #define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)|L2_SHARED) 442 #define ARM_L2L_NRML_IWT_OWT (L2_C|L2_SHARED) 443 #define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED) 444 #define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B|L2_SHARED) 445 446 #define ARM_L2S_STRONG_ORD (0) 447 #define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2)) 448 #define ARM_L2S_DEVICE_SHARE (L2_B) 449 #define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)|L2_SHARED) 450 #define ARM_L2S_NRML_IWT_OWT (L2_C|L2_SHARED) 451 #define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED) 452 #define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B|L2_SHARED) 453 #endif /* SMP */ 454 455 #elif ARM_NMMUS > 1 456 /* More than one MMU class configured; use variables. */ 457 #define L2_S_PROT_U pte_l2_s_prot_u 458 #define L2_S_PROT_W pte_l2_s_prot_w 459 #define L2_S_PROT_MASK pte_l2_s_prot_mask 460 461 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 462 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 463 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 464 465 #define L1_S_PROTO pte_l1_s_proto 466 #define L1_C_PROTO pte_l1_c_proto 467 #define L2_S_PROTO pte_l2_s_proto 468 469 #elif ARM_MMU_GENERIC != 0 470 #define L2_S_PROT_U L2_S_PROT_U_generic 471 #define L2_S_PROT_W L2_S_PROT_W_generic 472 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 473 474 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 475 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 476 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 477 478 #define L1_S_PROTO L1_S_PROTO_generic 479 #define L1_C_PROTO L1_C_PROTO_generic 480 #define L2_S_PROTO L2_S_PROTO_generic 481 482 #elif ARM_MMU_XSCALE == 1 483 #define L2_S_PROT_U L2_S_PROT_U_xscale 484 #define L2_S_PROT_W L2_S_PROT_W_xscale 485 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 486 487 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 488 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 489 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 490 491 #define L1_S_PROTO L1_S_PROTO_xscale 492 #define L1_C_PROTO L1_C_PROTO_xscale 493 #define L2_S_PROTO L2_S_PROTO_xscale 494 495 #endif /* ARM_NMMUS > 1 */ 496 497 #if defined(CPU_XSCALE_81342) || ARM_ARCH_6 || ARM_ARCH_7A 498 #define PMAP_NEEDS_PTE_SYNC 1 499 #define PMAP_INCLUDE_PTE_SYNC 500 #else 501 #define PMAP_NEEDS_PTE_SYNC 0 502 #endif 503 504 /* 505 * These macros return various bits based on kernel/user and protection. 506 * Note that the compiler will usually fold these at compile time. 507 */ 508 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0 509 510 #define L1_S_PROT_U (L1_S_AP(AP_U)) 511 #define L1_S_PROT_W (L1_S_AP(AP_W)) 512 #define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) 513 #define L1_S_WRITABLE(pd) ((pd) & L1_S_PROT_W) 514 515 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 516 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) 517 518 #define L2_L_PROT_U (L2_AP(AP_U)) 519 #define L2_L_PROT_W (L2_AP(AP_W)) 520 #define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) 521 522 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 523 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) 524 525 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 526 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) 527 #else 528 #define L1_S_PROT_U (L1_S_AP(AP_U)) 529 #define L1_S_PROT_W (L1_S_APX) /* Write disable */ 530 #define L1_S_PROT_MASK (L1_S_PROT_W|L1_S_PROT_U) 531 #define L1_S_REF (L1_S_AP(AP_REF)) /* Reference flag */ 532 #define L1_S_WRITABLE(pd) (!((pd) & L1_S_PROT_W)) 533 #define L1_S_EXECUTABLE(pd) (!((pd) & L1_S_XN)) 534 #define L1_S_REFERENCED(pd) ((pd) & L1_S_REF) 535 536 #define L1_S_PROT(ku, pr) (((((ku) == PTE_KERNEL) ? 0 : L1_S_PROT_U) | \ 537 (((pr) & VM_PROT_WRITE) ? 0 : L1_S_PROT_W) | \ 538 (((pr) & VM_PROT_EXECUTE) ? 0 : L1_S_XN))) 539 540 #define L2_L_PROT_MASK (L2_APX|L2_AP0(0x3)) 541 #define L2_L_PROT(ku, pr) (L2_L_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \ 542 (((pr) & VM_PROT_WRITE) ? L2_APX : 0))) 543 544 #define L2_S_PROT(ku, pr) (L2_S_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \ 545 (((pr) & VM_PROT_WRITE) ? L2_APX : 0))) 546 547 #endif 548 549 /* 550 * Macros to test if a mapping is mappable with an L1 Section mapping 551 * or an L2 Large Page mapping. 552 */ 553 #define L1_S_MAPPABLE_P(va, pa, size) \ 554 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 555 556 #define L2_L_MAPPABLE_P(va, pa, size) \ 557 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 558 559 /* 560 * Provide a fallback in case we were not able to determine it at 561 * compile-time. 562 */ 563 #ifndef PMAP_NEEDS_PTE_SYNC 564 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 565 #define PMAP_INCLUDE_PTE_SYNC 566 #endif 567 568 #ifdef ARM_L2_PIPT 569 #define _sync_l2(pte, size) cpu_l2cache_wb_range(vtophys(pte), size) 570 #else 571 #define _sync_l2(pte, size) cpu_l2cache_wb_range(pte, size) 572 #endif 573 574 #define PTE_SYNC(pte) \ 575 do { \ 576 if (PMAP_NEEDS_PTE_SYNC) { \ 577 cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ 578 cpu_drain_writebuf(); \ 579 _sync_l2((vm_offset_t)(pte), sizeof(pt_entry_t));\ 580 } else \ 581 cpu_drain_writebuf(); \ 582 } while (/*CONSTCOND*/0) 583 584 #define PTE_SYNC_RANGE(pte, cnt) \ 585 do { \ 586 if (PMAP_NEEDS_PTE_SYNC) { \ 587 cpu_dcache_wb_range((vm_offset_t)(pte), \ 588 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 589 cpu_drain_writebuf(); \ 590 _sync_l2((vm_offset_t)(pte), \ 591 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 592 } else \ 593 cpu_drain_writebuf(); \ 594 } while (/*CONSTCOND*/0) 595 596 extern pt_entry_t pte_l1_s_cache_mode; 597 extern pt_entry_t pte_l1_s_cache_mask; 598 599 extern pt_entry_t pte_l2_l_cache_mode; 600 extern pt_entry_t pte_l2_l_cache_mask; 601 602 extern pt_entry_t pte_l2_s_cache_mode; 603 extern pt_entry_t pte_l2_s_cache_mask; 604 605 extern pt_entry_t pte_l1_s_cache_mode_pt; 606 extern pt_entry_t pte_l2_l_cache_mode_pt; 607 extern pt_entry_t pte_l2_s_cache_mode_pt; 608 609 extern pt_entry_t pte_l2_s_prot_u; 610 extern pt_entry_t pte_l2_s_prot_w; 611 extern pt_entry_t pte_l2_s_prot_mask; 612 613 extern pt_entry_t pte_l1_s_proto; 614 extern pt_entry_t pte_l1_c_proto; 615 extern pt_entry_t pte_l2_s_proto; 616 617 extern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 618 extern void (*pmap_copy_page_offs_func)(vm_paddr_t a_phys, 619 vm_offset_t a_offs, vm_paddr_t b_phys, vm_offset_t b_offs, int cnt); 620 extern void (*pmap_zero_page_func)(vm_paddr_t, int, int); 621 622 #if (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7) != 0 || defined(CPU_XSCALE_81342) 623 void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t); 624 void pmap_zero_page_generic(vm_paddr_t, int, int); 625 626 void pmap_pte_init_generic(void); 627 #endif /* (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7) != 0 */ 628 629 #if ARM_MMU_XSCALE == 1 630 void pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t); 631 void pmap_zero_page_xscale(vm_paddr_t, int, int); 632 633 void pmap_pte_init_xscale(void); 634 635 void xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t); 636 637 void pmap_use_minicache(vm_offset_t, vm_size_t); 638 #endif /* ARM_MMU_XSCALE == 1 */ 639 #if defined(CPU_XSCALE_81342) 640 #define ARM_HAVE_SUPERSECTIONS 641 #endif 642 643 #define PTE_KERNEL 0 644 #define PTE_USER 1 645 #define l1pte_valid(pde) ((pde) != 0) 646 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 647 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 648 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 649 650 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 651 #define l2pte_valid(pte) ((pte) != 0) 652 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 653 #define l2pte_minidata(pte) (((pte) & \ 654 (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\ 655 == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X))) 656 657 /* L1 and L2 page table macros */ 658 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 659 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 660 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 661 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 662 663 #define pmap_pte_v(pte) l2pte_valid(*(pte)) 664 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 665 666 /* 667 * Flags that indicate attributes of pages or mappings of pages. 668 * 669 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 670 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 671 * pv_entry's for each page. They live in the same "namespace" so 672 * that we can clear multiple attributes at a time. 673 * 674 * Note the "non-cacheable" flag generally means the page has 675 * multiple mappings in a given address space. 676 */ 677 #define PVF_MOD 0x01 /* page is modified */ 678 #define PVF_REF 0x02 /* page is referenced */ 679 #define PVF_WIRED 0x04 /* mapping is wired */ 680 #define PVF_WRITE 0x08 /* mapping is writable */ 681 #define PVF_EXEC 0x10 /* mapping is executable */ 682 #define PVF_NC 0x20 /* mapping is non-cacheable */ 683 #define PVF_MWC 0x40 /* mapping is used multiple times in userland */ 684 #define PVF_UNMAN 0x80 /* mapping is unmanaged */ 685 686 void vector_page_setprot(int); 687 688 #define SECTION_CACHE 0x1 689 #define SECTION_PT 0x2 690 void pmap_kenter_section(vm_offset_t, vm_paddr_t, int flags); 691 #ifdef ARM_HAVE_SUPERSECTIONS 692 void pmap_kenter_supersection(vm_offset_t, uint64_t, int flags); 693 #endif 694 695 extern char *_tmppt; 696 697 void pmap_postinit(void); 698 699 extern vm_paddr_t dump_avail[]; 700 #endif /* _KERNEL */ 701 702 #endif /* !LOCORE */ 703 704 #endif /* !_MACHINE_PMAP_H_ */ 705 #endif /* __ARM_ARCH >= 6 */ 706