1 /*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * the Systems Programming Group of the University of Utah Computer 7 * Science Department and William Jolitz of UUNET Technologies Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * Derived from hp300 version by Mike Hibler, this version by William 38 * Jolitz uses a recursive map [a pde points to the page directory] to 39 * map the page tables using the pagetables themselves. This is done to 40 * reduce the impact on kernel virtual memory for lots of sparse address 41 * space, and to reduce the cost of memory to each process. 42 * 43 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90 44 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91 45 * from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30 46 * 47 * $FreeBSD$ 48 */ 49 50 #ifndef _MACHINE_PMAP_H_ 51 #define _MACHINE_PMAP_H_ 52 53 #include <machine/pte.h> 54 #include <machine/cpuconf.h> 55 /* 56 * Pte related macros 57 */ 58 #if ARM_ARCH_6 || ARM_ARCH_7A 59 #ifdef SMP 60 #define PTE_NOCACHE 2 61 #else 62 #define PTE_NOCACHE 1 63 #endif 64 #define PTE_CACHE 4 65 #define PTE_DEVICE 2 66 #define PTE_PAGETABLE 4 67 #else 68 #define PTE_NOCACHE 1 69 #define PTE_CACHE 2 70 #define PTE_PAGETABLE 3 71 #endif 72 73 enum mem_type { 74 STRONG_ORD = 0, 75 DEVICE_NOSHARE, 76 DEVICE_SHARE, 77 NRML_NOCACHE, 78 NRML_IWT_OWT, 79 NRML_IWB_OWB, 80 NRML_IWBA_OWBA 81 }; 82 83 #ifndef LOCORE 84 85 #include <sys/queue.h> 86 #include <sys/_cpuset.h> 87 #include <sys/_lock.h> 88 #include <sys/_mutex.h> 89 90 #define PDESIZE sizeof(pd_entry_t) /* for assembly files */ 91 #define PTESIZE sizeof(pt_entry_t) /* for assembly files */ 92 93 #ifdef _KERNEL 94 95 #define vtophys(va) pmap_kextract((vm_offset_t)(va)) 96 97 #endif 98 99 #define pmap_page_get_memattr(m) VM_MEMATTR_DEFAULT 100 #define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list)) 101 #define pmap_page_is_write_mapped(m) (((m)->aflags & PGA_WRITEABLE) != 0) 102 #define pmap_page_set_memattr(m, ma) (void)0 103 104 /* 105 * Pmap stuff 106 */ 107 108 /* 109 * This structure is used to hold a virtual<->physical address 110 * association and is used mostly by bootstrap code 111 */ 112 struct pv_addr { 113 SLIST_ENTRY(pv_addr) pv_list; 114 vm_offset_t pv_va; 115 vm_paddr_t pv_pa; 116 }; 117 118 struct pv_entry; 119 120 struct md_page { 121 int pvh_attrs; 122 vm_offset_t pv_kva; /* first kernel VA mapping */ 123 TAILQ_HEAD(,pv_entry) pv_list; 124 }; 125 126 struct l1_ttable; 127 struct l2_dtable; 128 129 130 /* 131 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 132 * A bucket size of 16 provides for 16MB of contiguous virtual address 133 * space per l2_dtable. Most processes will, therefore, require only two or 134 * three of these to map their whole working set. 135 */ 136 #define L2_BUCKET_LOG2 4 137 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 138 /* 139 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 140 * of l2_dtable structures required to track all possible page descriptors 141 * mappable by an L1 translation table is given by the following constants: 142 */ 143 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 144 #define L2_SIZE (1 << L2_LOG2) 145 146 struct pmap { 147 struct mtx pm_mtx; 148 u_int8_t pm_domain; 149 struct l1_ttable *pm_l1; 150 struct l2_dtable *pm_l2[L2_SIZE]; 151 pd_entry_t *pm_pdir; /* KVA of page directory */ 152 cpuset_t pm_active; /* active on cpus */ 153 struct pmap_statistics pm_stats; /* pmap statictics */ 154 TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */ 155 }; 156 157 typedef struct pmap *pmap_t; 158 159 #ifdef _KERNEL 160 extern struct pmap kernel_pmap_store; 161 #define kernel_pmap (&kernel_pmap_store) 162 #define pmap_kernel() kernel_pmap 163 164 #define PMAP_ASSERT_LOCKED(pmap) \ 165 mtx_assert(&(pmap)->pm_mtx, MA_OWNED) 166 #define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx) 167 #define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx) 168 #define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \ 169 NULL, MTX_DEF | MTX_DUPOK) 170 #define PMAP_OWNED(pmap) mtx_owned(&(pmap)->pm_mtx) 171 #define PMAP_MTX(pmap) (&(pmap)->pm_mtx) 172 #define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx) 173 #define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx) 174 #endif 175 176 177 /* 178 * For each vm_page_t, there is a list of all currently valid virtual 179 * mappings of that page. An entry is a pv_entry_t, the list is pv_list. 180 */ 181 typedef struct pv_entry { 182 pmap_t pv_pmap; /* pmap where mapping lies */ 183 vm_offset_t pv_va; /* virtual address for mapping */ 184 TAILQ_ENTRY(pv_entry) pv_list; 185 TAILQ_ENTRY(pv_entry) pv_plist; 186 int pv_flags; /* flags (wired, etc...) */ 187 } *pv_entry_t; 188 189 #ifdef _KERNEL 190 191 boolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **); 192 193 /* 194 * virtual address to page table entry and 195 * to physical address. Likewise for alternate address space. 196 * Note: these work recursively, thus vtopte of a pte will give 197 * the corresponding pde that in turn maps it. 198 */ 199 200 /* 201 * The current top of kernel VM. 202 */ 203 extern vm_offset_t pmap_curmaxkvaddr; 204 205 struct pcb; 206 207 void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 208 /* Virtual address to page table entry */ 209 static __inline pt_entry_t * 210 vtopte(vm_offset_t va) 211 { 212 pd_entry_t *pdep; 213 pt_entry_t *ptep; 214 215 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE) 216 return (NULL); 217 return (ptep); 218 } 219 220 extern vm_paddr_t phys_avail[]; 221 extern vm_offset_t virtual_avail; 222 extern vm_offset_t virtual_end; 223 224 void pmap_bootstrap(vm_offset_t, vm_offset_t, struct pv_addr *); 225 int pmap_change_attr(vm_offset_t, vm_size_t, int); 226 void pmap_kenter(vm_offset_t va, vm_paddr_t pa); 227 void pmap_kenter_nocache(vm_offset_t va, vm_paddr_t pa); 228 void *pmap_kenter_temp(vm_paddr_t pa, int i); 229 void pmap_kenter_user(vm_offset_t va, vm_paddr_t pa); 230 vm_paddr_t pmap_kextract(vm_offset_t va); 231 void pmap_kremove(vm_offset_t); 232 void *pmap_mapdev(vm_offset_t, vm_size_t); 233 void pmap_unmapdev(vm_offset_t, vm_size_t); 234 vm_page_t pmap_use_pt(pmap_t, vm_offset_t); 235 void pmap_debug(int); 236 void pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int); 237 void pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *); 238 vm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int); 239 void 240 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 241 int cache); 242 int pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int); 243 int pmap_dmap_iscurrent(pmap_t pmap); 244 245 /* 246 * Definitions for MMU domains 247 */ 248 #define PMAP_DOMAINS 15 /* 15 'user' domains (1-15) */ 249 #define PMAP_DOMAIN_KERNEL 0 /* The kernel uses domain #0 */ 250 251 /* 252 * The new pmap ensures that page-tables are always mapping Write-Thru. 253 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 254 * on every change. 255 * 256 * Unfortunately, not all CPUs have a write-through cache mode. So we 257 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 258 * and if there is the chance for PTE syncs to be needed, we define 259 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 260 * the code. 261 */ 262 extern int pmap_needs_pte_sync; 263 264 /* 265 * These macros define the various bit masks in the PTE. 266 * 267 * We use these macros since we use different bits on different processor 268 * models. 269 */ 270 271 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 272 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)|\ 273 L1_S_XSCALE_TEX(TEX_XSCALE_T)) 274 275 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 276 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X) | \ 277 L2_XSCALE_L_TEX(TEX_XSCALE_T)) 278 279 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 280 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 281 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W) 282 283 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 284 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 285 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W) 286 287 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 288 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)| \ 289 L2_XSCALE_T_TEX(TEX_XSCALE_X)) 290 291 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 292 #define L1_S_PROTO_xscale (L1_TYPE_S) 293 294 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 295 #define L1_C_PROTO_xscale (L1_TYPE_C) 296 297 #define L2_L_PROTO (L2_TYPE_L) 298 299 #define L2_S_PROTO_generic (L2_TYPE_S) 300 #define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) 301 302 /* 303 * User-visible names for the ones that vary with MMU class. 304 */ 305 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0 306 #define L2_AP(x) (L2_AP0(x)) 307 #else 308 #define L2_AP(x) (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x)) 309 #endif 310 311 #if ARM_NMMUS > 1 312 /* More than one MMU class configured; use variables. */ 313 #define L2_S_PROT_U pte_l2_s_prot_u 314 #define L2_S_PROT_W pte_l2_s_prot_w 315 #define L2_S_PROT_MASK pte_l2_s_prot_mask 316 317 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 318 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 319 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 320 321 #define L1_S_PROTO pte_l1_s_proto 322 #define L1_C_PROTO pte_l1_c_proto 323 #define L2_S_PROTO pte_l2_s_proto 324 325 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 326 #define L2_S_PROT_U L2_S_PROT_U_generic 327 #define L2_S_PROT_W L2_S_PROT_W_generic 328 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 329 330 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 331 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 332 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 333 334 #define L1_S_PROTO L1_S_PROTO_generic 335 #define L1_C_PROTO L1_C_PROTO_generic 336 #define L2_S_PROTO L2_S_PROTO_generic 337 338 #elif ARM_MMU_XSCALE == 1 339 #define L2_S_PROT_U L2_S_PROT_U_xscale 340 #define L2_S_PROT_W L2_S_PROT_W_xscale 341 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 342 343 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 344 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 345 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 346 347 #define L1_S_PROTO L1_S_PROTO_xscale 348 #define L1_C_PROTO L1_C_PROTO_xscale 349 #define L2_S_PROTO L2_S_PROTO_xscale 350 351 #elif (ARM_MMU_V6 + ARM_MMU_V7) != 0 352 353 #define L2_S_PROT_U (L2_AP0(2)) /* user access */ 354 #define L2_S_PROT_R (L2_APX|L2_AP0(1)) /* read access */ 355 356 #define L2_S_PROT_MASK (L2_S_PROT_U|L2_S_PROT_R) 357 #define L2_S_WRITABLE(pte) (!(pte & L2_APX)) 358 359 #ifndef SMP 360 #define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C) 361 #define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C) 362 #define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C) 363 #else 364 #define L1_S_CACHE_MASK (L1_S_TEX_MASK|L1_S_B|L1_S_C|L1_SHARED) 365 #define L2_L_CACHE_MASK (L2_L_TEX_MASK|L2_B|L2_C|L2_SHARED) 366 #define L2_S_CACHE_MASK (L2_S_TEX_MASK|L2_B|L2_C|L2_SHARED) 367 #endif /* SMP */ 368 369 #define L1_S_PROTO (L1_TYPE_S) 370 #define L1_C_PROTO (L1_TYPE_C) 371 #define L2_S_PROTO (L2_TYPE_S) 372 373 #ifndef SMP 374 #define ARM_L1S_STRONG_ORD (0) 375 #define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2)) 376 #define ARM_L1S_DEVICE_SHARE (L1_S_B) 377 #define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)) 378 #define ARM_L1S_NRML_IWT_OWT (L1_S_C) 379 #define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B) 380 #define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B) 381 382 #define ARM_L2L_STRONG_ORD (0) 383 #define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2)) 384 #define ARM_L2L_DEVICE_SHARE (L2_B) 385 #define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)) 386 #define ARM_L2L_NRML_IWT_OWT (L2_C) 387 #define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B) 388 #define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B) 389 390 #define ARM_L2S_STRONG_ORD (0) 391 #define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2)) 392 #define ARM_L2S_DEVICE_SHARE (L2_B) 393 #define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)) 394 #define ARM_L2S_NRML_IWT_OWT (L2_C) 395 #define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B) 396 #define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B) 397 #else 398 #define ARM_L1S_STRONG_ORD (0) 399 #define ARM_L1S_DEVICE_NOSHARE (L1_S_TEX(2)) 400 #define ARM_L1S_DEVICE_SHARE (L1_S_B) 401 #define ARM_L1S_NRML_NOCACHE (L1_S_TEX(1)|L1_SHARED) 402 #define ARM_L1S_NRML_IWT_OWT (L1_S_C|L1_SHARED) 403 #define ARM_L1S_NRML_IWB_OWB (L1_S_C|L1_S_B|L1_SHARED) 404 #define ARM_L1S_NRML_IWBA_OWBA (L1_S_TEX(1)|L1_S_C|L1_S_B|L1_SHARED) 405 406 #define ARM_L2L_STRONG_ORD (0) 407 #define ARM_L2L_DEVICE_NOSHARE (L2_L_TEX(2)) 408 #define ARM_L2L_DEVICE_SHARE (L2_B) 409 #define ARM_L2L_NRML_NOCACHE (L2_L_TEX(1)|L2_SHARED) 410 #define ARM_L2L_NRML_IWT_OWT (L2_C|L2_SHARED) 411 #define ARM_L2L_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED) 412 #define ARM_L2L_NRML_IWBA_OWBA (L2_L_TEX(1)|L2_C|L2_B|L2_SHARED) 413 414 #define ARM_L2S_STRONG_ORD (0) 415 #define ARM_L2S_DEVICE_NOSHARE (L2_S_TEX(2)) 416 #define ARM_L2S_DEVICE_SHARE (L2_B) 417 #define ARM_L2S_NRML_NOCACHE (L2_S_TEX(1)|L2_SHARED) 418 #define ARM_L2S_NRML_IWT_OWT (L2_C|L2_SHARED) 419 #define ARM_L2S_NRML_IWB_OWB (L2_C|L2_B|L2_SHARED) 420 #define ARM_L2S_NRML_IWBA_OWBA (L2_S_TEX(1)|L2_C|L2_B|L2_SHARED) 421 #endif /* SMP */ 422 #endif /* ARM_NMMUS > 1 */ 423 424 #if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1) 425 #define PMAP_NEEDS_PTE_SYNC 1 426 #define PMAP_INCLUDE_PTE_SYNC 427 #elif defined(CPU_XSCALE_81342) 428 #define PMAP_NEEDS_PTE_SYNC 1 429 #define PMAP_INCLUDE_PTE_SYNC 430 #elif (ARM_MMU_SA1 == 0) 431 #define PMAP_NEEDS_PTE_SYNC 0 432 #endif 433 434 /* 435 * These macros return various bits based on kernel/user and protection. 436 * Note that the compiler will usually fold these at compile time. 437 */ 438 #if (ARM_MMU_V6 + ARM_MMU_V7) == 0 439 440 #define L1_S_PROT_U (L1_S_AP(AP_U)) 441 #define L1_S_PROT_W (L1_S_AP(AP_W)) 442 #define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) 443 #define L1_S_WRITABLE(pd) ((pd) & L1_S_PROT_W) 444 445 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 446 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) 447 448 #define L2_L_PROT_U (L2_AP(AP_U)) 449 #define L2_L_PROT_W (L2_AP(AP_W)) 450 #define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) 451 452 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 453 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) 454 455 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 456 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) 457 #else 458 #define L1_S_PROT_U (L1_S_AP(AP_U)) 459 #define L1_S_PROT_MASK (L1_S_APX|L1_S_AP(0x3)) 460 #define L1_S_WRITABLE(pd) (!((pd) & L1_S_APX)) 461 462 #define L1_S_PROT(ku, pr) (L1_S_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L1_S_PROT_U : 0) | \ 463 (((pr) & VM_PROT_WRITE) ? L1_S_APX : 0))) 464 465 #define L2_L_PROT_MASK (L2_APX|L2_AP0(0x3)) 466 #define L2_L_PROT(ku, pr) (L2_L_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \ 467 (((pr) & VM_PROT_WRITE) ? L2_APX : 0))) 468 469 #define L2_S_PROT(ku, pr) (L2_S_PROT_MASK & ~((((ku) == PTE_KERNEL) ? L2_S_PROT_U : 0) | \ 470 (((pr) & VM_PROT_WRITE) ? L2_APX : 0))) 471 472 #endif 473 474 /* 475 * Macros to test if a mapping is mappable with an L1 Section mapping 476 * or an L2 Large Page mapping. 477 */ 478 #define L1_S_MAPPABLE_P(va, pa, size) \ 479 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 480 481 #define L2_L_MAPPABLE_P(va, pa, size) \ 482 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 483 484 /* 485 * Provide a fallback in case we were not able to determine it at 486 * compile-time. 487 */ 488 #ifndef PMAP_NEEDS_PTE_SYNC 489 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 490 #define PMAP_INCLUDE_PTE_SYNC 491 #endif 492 493 #define PTE_SYNC(pte) \ 494 do { \ 495 if (PMAP_NEEDS_PTE_SYNC) { \ 496 cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ 497 cpu_l2cache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ 498 } else \ 499 cpu_drain_writebuf(); \ 500 } while (/*CONSTCOND*/0) 501 502 #define PTE_SYNC_RANGE(pte, cnt) \ 503 do { \ 504 if (PMAP_NEEDS_PTE_SYNC) { \ 505 cpu_dcache_wb_range((vm_offset_t)(pte), \ 506 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 507 cpu_l2cache_wb_range((vm_offset_t)(pte), \ 508 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 509 } else \ 510 cpu_drain_writebuf(); \ 511 } while (/*CONSTCOND*/0) 512 513 extern pt_entry_t pte_l1_s_cache_mode; 514 extern pt_entry_t pte_l1_s_cache_mask; 515 516 extern pt_entry_t pte_l2_l_cache_mode; 517 extern pt_entry_t pte_l2_l_cache_mask; 518 519 extern pt_entry_t pte_l2_s_cache_mode; 520 extern pt_entry_t pte_l2_s_cache_mask; 521 522 extern pt_entry_t pte_l1_s_cache_mode_pt; 523 extern pt_entry_t pte_l2_l_cache_mode_pt; 524 extern pt_entry_t pte_l2_s_cache_mode_pt; 525 526 extern pt_entry_t pte_l2_s_prot_u; 527 extern pt_entry_t pte_l2_s_prot_w; 528 extern pt_entry_t pte_l2_s_prot_mask; 529 530 extern pt_entry_t pte_l1_s_proto; 531 extern pt_entry_t pte_l1_c_proto; 532 extern pt_entry_t pte_l2_s_proto; 533 534 extern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 535 extern void (*pmap_zero_page_func)(vm_paddr_t, int, int); 536 537 #if (ARM_MMU_GENERIC + ARM_MMU_V6 + ARM_MMU_V7 + ARM_MMU_SA1) != 0 || defined(CPU_XSCALE_81342) 538 void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t); 539 void pmap_zero_page_generic(vm_paddr_t, int, int); 540 541 void pmap_pte_init_generic(void); 542 #if defined(CPU_ARM8) 543 void pmap_pte_init_arm8(void); 544 #endif 545 #if defined(CPU_ARM9) 546 void pmap_pte_init_arm9(void); 547 #endif /* CPU_ARM9 */ 548 #if defined(CPU_ARM10) 549 void pmap_pte_init_arm10(void); 550 #endif /* CPU_ARM10 */ 551 #if (ARM_MMU_V6 + ARM_MMU_V7) != 0 552 void pmap_pte_init_mmu_v6(void); 553 #endif /* CPU_ARM11 */ 554 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 555 556 #if /* ARM_MMU_SA1 == */1 557 void pmap_pte_init_sa1(void); 558 #endif /* ARM_MMU_SA1 == 1 */ 559 560 #if ARM_MMU_XSCALE == 1 561 void pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t); 562 void pmap_zero_page_xscale(vm_paddr_t, int, int); 563 564 void pmap_pte_init_xscale(void); 565 566 void xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t); 567 568 void pmap_use_minicache(vm_offset_t, vm_size_t); 569 #endif /* ARM_MMU_XSCALE == 1 */ 570 #if defined(CPU_XSCALE_81342) 571 #define ARM_HAVE_SUPERSECTIONS 572 #endif 573 574 #define PTE_KERNEL 0 575 #define PTE_USER 1 576 #define l1pte_valid(pde) ((pde) != 0) 577 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 578 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 579 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 580 581 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 582 #define l2pte_valid(pte) ((pte) != 0) 583 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 584 #define l2pte_minidata(pte) (((pte) & \ 585 (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\ 586 == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X))) 587 588 /* L1 and L2 page table macros */ 589 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 590 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 591 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 592 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 593 594 #define pmap_pte_v(pte) l2pte_valid(*(pte)) 595 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 596 597 /* 598 * Flags that indicate attributes of pages or mappings of pages. 599 * 600 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 601 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 602 * pv_entry's for each page. They live in the same "namespace" so 603 * that we can clear multiple attributes at a time. 604 * 605 * Note the "non-cacheable" flag generally means the page has 606 * multiple mappings in a given address space. 607 */ 608 #define PVF_MOD 0x01 /* page is modified */ 609 #define PVF_REF 0x02 /* page is referenced */ 610 #define PVF_WIRED 0x04 /* mapping is wired */ 611 #define PVF_WRITE 0x08 /* mapping is writable */ 612 #define PVF_EXEC 0x10 /* mapping is executable */ 613 #define PVF_NC 0x20 /* mapping is non-cacheable */ 614 #define PVF_MWC 0x40 /* mapping is used multiple times in userland */ 615 #define PVF_UNMAN 0x80 /* mapping is unmanaged */ 616 617 void vector_page_setprot(int); 618 619 /* 620 * This structure is used by machine-dependent code to describe 621 * static mappings of devices, created at bootstrap time. 622 */ 623 struct pmap_devmap { 624 vm_offset_t pd_va; /* virtual address */ 625 vm_paddr_t pd_pa; /* physical address */ 626 vm_size_t pd_size; /* size of region */ 627 vm_prot_t pd_prot; /* protection code */ 628 int pd_cache; /* cache attributes */ 629 }; 630 631 const struct pmap_devmap *pmap_devmap_find_pa(vm_paddr_t, vm_size_t); 632 const struct pmap_devmap *pmap_devmap_find_va(vm_offset_t, vm_size_t); 633 634 void pmap_devmap_bootstrap(vm_offset_t, const struct pmap_devmap *); 635 void pmap_devmap_register(const struct pmap_devmap *); 636 637 #define SECTION_CACHE 0x1 638 #define SECTION_PT 0x2 639 void pmap_kenter_section(vm_offset_t, vm_paddr_t, int flags); 640 #ifdef ARM_HAVE_SUPERSECTIONS 641 void pmap_kenter_supersection(vm_offset_t, uint64_t, int flags); 642 #endif 643 644 extern char *_tmppt; 645 646 void pmap_postinit(void); 647 648 #ifdef ARM_USE_SMALL_ALLOC 649 void arm_add_smallalloc_pages(void *, void *, int, int); 650 vm_offset_t arm_ptovirt(vm_paddr_t); 651 void arm_init_smallalloc(void); 652 struct arm_small_page { 653 void *addr; 654 TAILQ_ENTRY(arm_small_page) pg_list; 655 }; 656 657 #endif 658 659 #define ARM_NOCACHE_KVA_SIZE 0x1000000 660 extern vm_offset_t arm_nocache_startaddr; 661 void *arm_remap_nocache(void *, vm_size_t); 662 void arm_unmap_nocache(void *, vm_size_t); 663 664 extern vm_paddr_t dump_avail[]; 665 #endif /* _KERNEL */ 666 667 #endif /* !LOCORE */ 668 669 #endif /* !_MACHINE_PMAP_H_ */ 670