1 /* 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * the Systems Programming Group of the University of Utah Computer 7 * Science Department and William Jolitz of UUNET Technologies Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * Derived from hp300 version by Mike Hibler, this version by William 38 * Jolitz uses a recursive map [a pde points to the page directory] to 39 * map the page tables using the pagetables themselves. This is done to 40 * reduce the impact on kernel virtual memory for lots of sparse address 41 * space, and to reduce the cost of memory to each process. 42 * 43 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90 44 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91 45 * from: FreeBSD: src/sys/i386/include/pmap.h,v 1.70 2000/11/30 46 * 47 * $FreeBSD$ 48 */ 49 50 #ifndef _MACHINE_PMAP_H_ 51 #define _MACHINE_PMAP_H_ 52 53 #include <machine/pte.h> 54 55 /* 56 * Pte related macros 57 */ 58 #define PTE_NOCACHE 0 59 #define PTE_CACHE 1 60 61 #define VADDR(pdi, pti) ((vm_offset_t)(((pdi)<<PDR_SHIFT)+((pti)<<PAGE_SHIFT))) 62 #define PTDIPDE(ptd) ((ptd)/1024) 63 #define PTDIPTE(ptd) ((ptd)%256) 64 65 #ifndef NKPT 66 #define NKPT 120 /* actual number of kernel page tables */ 67 #endif 68 69 #ifndef NKPDE 70 #define NKPDE 1019 /* Maximum number of kernel PDE */ 71 #endif 72 73 #define NPDEPTD 16 /* Number of PDE in each PTD */ 74 75 /* 76 * The *PTDI values control the layout of virtual memory 77 */ 78 79 #define KPTDI (NPDEPG-NKPDE) /* ptd entry for kernel space begin */ 80 #define PTDPTDI (KPTDI-1) /* ptd entry that points to ptd! */ 81 #define KPTPTDI (PTDPTDI-1) /* ptd entry for kernel PTEs */ 82 #define UPTPTDI (KPTPTDI-3) /* ptd entry for uspace PTEs */ 83 #define UMAXPTDI (UPTPTDI-1) /* ptd entry for user space end */ 84 #define UMAXPTEOFF (NPTEPG) /* pte entry for user space end */ 85 86 #ifndef LOCORE 87 88 #include <sys/queue.h> 89 90 #define PDESIZE sizeof(pd_entry_t) /* for assembly files */ 91 #define PTESIZE sizeof(pt_entry_t) /* for assembly files */ 92 93 #ifdef _KERNEL 94 #define ARM_PTE_TO_PFN(pte) ((pt_entry_t)(pte) >> PAGE_SHIFT) 95 #define ARM_PDE_TO_PFN(pde) ((pd_entry_t)(pde) >> 10) 96 #define ARM_PHYS_TO_KSPACE(x) ((vm_offset_t) (x) | (UPTPTDI << PDR_SHIFT)) 97 #define ARM_KSPACE_TO_PHYS(x) ((vm_offset_t) (x) & ~(UPTPTDI << PDR_SHIFT)) 98 99 extern pt_entry_t PTmap[], APTmap; 100 extern pd_entry_t PTD[], APTD, PTDpde, APTDpde; 101 102 extern pd_entry_t IdlePTD; /* physical address of "Idle" state directory */ 103 104 105 106 #if 0 107 static __inline vm_offset_t 108 pmap_akextract(vm_offset_t va) 109 { 110 vm_offset_t pa; 111 pa = *(vm_offset_t *)avtopte(va); 112 pa = (pa & PG_FRAME) | (va & PAGE_MASK); 113 return pa; 114 } 115 #endif 116 #define vtophys(va) pmap_kextract(((vm_offset_t) (va))) 117 118 #define avtophys(va) pmap_akextract(((vm_offset_t) (va))) 119 120 #endif 121 122 #define pmap_page_is_mapped(m) (!TAILQ_EMPTY(&(m)->md.pv_list)) 123 /* 124 * Pmap sutff 125 */ 126 127 /* 128 * This structure is used to hold a virtual<->physical address 129 * association and is used mostly by bootstrap code 130 */ 131 struct pv_addr { 132 SLIST_ENTRY(pv_addr) pv_list; 133 vm_offset_t pv_va; 134 vm_paddr_t pv_pa; 135 }; 136 137 struct pv_entry; 138 139 struct md_page { 140 int pvh_attrs; 141 u_int uro_mappings; 142 u_int urw_mappings; 143 union { 144 u_short s_mappings[2]; /* Assume kernel count <= 65535 */ 145 u_int i_mappings; 146 } k_u; 147 #define kro_mappings k_u.s_mappings[0] 148 #define krw_mappings k_u.s_mappings[1] 149 #define k_mappings k_u.i_mappings 150 int pv_list_count; 151 TAILQ_HEAD(,pv_entry) pv_list; 152 }; 153 154 #define VM_MDPAGE_INIT(pg) \ 155 do { \ 156 TAILQ_INIT(&pg->pv_list); \ 157 mtx_init(&(pg)->md_page.pvh_mtx, "MDPAGE Mutex", NULL, MTX_DEV);\ 158 (pg)->mdpage.pvh_attrs = 0; \ 159 (pg)->mdpage.uro_mappings = 0; \ 160 (pg)->mdpage.urw_mappings = 0; \ 161 (pg)->mdpage.k_mappings = 0; \ 162 } while (/*CONSTCOND*/0) 163 164 struct l1_ttable; 165 struct l2_dtable; 166 167 /* 168 * Track cache/tlb occupancy using the following structure 169 */ 170 union pmap_cache_state { 171 struct { 172 union { 173 u_int8_t csu_cache_b[2]; 174 u_int16_t csu_cache; 175 } cs_cache_u; 176 177 union { 178 u_int8_t csu_tlb_b[2]; 179 u_int16_t csu_tlb; 180 } cs_tlb_u; 181 } cs_s; 182 u_int32_t cs_all; 183 }; 184 #define cs_cache_id cs_s.cs_cache_u.csu_cache_b[0] 185 #define cs_cache_d cs_s.cs_cache_u.csu_cache_b[1] 186 #define cs_cache cs_s.cs_cache_u.csu_cache 187 #define cs_tlb_id cs_s.cs_tlb_u.csu_tlb_b[0] 188 #define cs_tlb_d cs_s.cs_tlb_u.csu_tlb_b[1] 189 #define cs_tlb cs_s.cs_tlb_u.csu_tlb 190 191 /* 192 * Assigned to cs_all to force cacheops to work for a particular pmap 193 */ 194 #define PMAP_CACHE_STATE_ALL 0xffffffffu 195 196 /* 197 * The number of L2 descriptor tables which can be tracked by an l2_dtable. 198 * A bucket size of 16 provides for 16MB of contiguous virtual address 199 * space per l2_dtable. Most processes will, therefore, require only two or 200 * three of these to map their whole working set. 201 */ 202 #define L2_BUCKET_LOG2 4 203 #define L2_BUCKET_SIZE (1 << L2_BUCKET_LOG2) 204 /* 205 * Given the above "L2-descriptors-per-l2_dtable" constant, the number 206 * of l2_dtable structures required to track all possible page descriptors 207 * mappable by an L1 translation table is given by the following constants: 208 */ 209 #define L2_LOG2 ((32 - L1_S_SHIFT) - L2_BUCKET_LOG2) 210 #define L2_SIZE (1 << L2_LOG2) 211 212 struct pmap { 213 u_int8_t pm_domain; 214 struct l1_ttable *pm_l1; 215 struct l2_dtable *pm_l2[L2_SIZE]; 216 pd_entry_t *pm_pdir; /* KVA of page directory */ 217 TAILQ_HEAD(,pv_entry) pm_pvlist; /* list of mappings in pmap */ 218 struct pv_addr pm_ptpt; /* pagetable of pagetables */ 219 int pm_count; /* reference count */ 220 int pm_active; /* active on cpus */ 221 struct pmap_statistics pm_stats; /* pmap statictics */ 222 struct vm_page *pm_ptphint; /* pmap ptp hint */ 223 union pmap_cache_state pm_cstate; 224 LIST_ENTRY(pmap) pm_list; /* List of all pmaps */ 225 }; 226 227 typedef struct pmap *pmap_t; 228 229 #ifdef _KERNEL 230 extern pmap_t kernel_pmap; 231 #define pmap_kernel() kernel_pmap 232 #endif 233 234 /* 235 * For each vm_page_t, there is a list of all currently valid virtual 236 * mappings of that page. An entry is a pv_entry_t, the list is pv_table. 237 */ 238 typedef struct pv_entry { 239 pmap_t pv_pmap; /* pmap where mapping lies */ 240 vm_offset_t pv_va; /* virtual address for mapping */ 241 TAILQ_ENTRY(pv_entry) pv_list; 242 TAILQ_ENTRY(pv_entry) pv_plist; 243 vm_page_t pv_ptem; /* VM page for pte */ 244 int pv_flags; /* flags (wired, etc...) */ 245 } *pv_entry_t; 246 247 #define PV_ENTRY_NULL ((pv_entry_t) 0) 248 249 #define PV_CI 0x01 /* all entries must be cache inhibited */ 250 #define PV_PTPAGE 0x02 /* entry maps a page table page */ 251 252 /* 253 * Page hooks. 254 * For speed we store the both the virtual address and the page table 255 * entry address for each page hook. 256 */ 257 typedef struct { 258 vm_offset_t va; 259 pt_entry_t *pte; 260 } pagehook_t; 261 262 263 #ifdef _KERNEL 264 265 boolean_t pmap_get_pde_pte(pmap_t, vm_offset_t, pd_entry_t **, pt_entry_t **); 266 267 /* 268 * virtual address to page table entry and 269 * to physical address. Likewise for alternate address space. 270 * Note: these work recursively, thus vtopte of a pte will give 271 * the corresponding pde that in turn maps it. 272 */ 273 274 struct pcb; 275 276 void pmap_set_pcb_pagedir(pmap_t, struct pcb *); 277 /* Virtual address to page table entry */ 278 static __inline pt_entry_t * 279 vtopte(vm_offset_t va) 280 { 281 pd_entry_t *pdep; 282 pt_entry_t *ptep; 283 284 if (pmap_get_pde_pte(pmap_kernel(), va, &pdep, &ptep) == FALSE) 285 return (NULL); 286 return (ptep); 287 } 288 289 extern vm_offset_t avail_end; 290 extern vm_offset_t clean_eva; 291 extern vm_offset_t clean_sva; 292 extern vm_offset_t phys_avail[]; 293 extern vm_offset_t virtual_avail; 294 extern vm_offset_t virtual_end; 295 296 void pmap_bootstrap(vm_offset_t, vm_offset_t, struct pv_addr *); 297 void pmap_kenter(vm_offset_t va, vm_paddr_t pa); 298 void pmap_kremove(vm_offset_t); 299 void *pmap_mapdev(vm_offset_t, vm_size_t); 300 void pmap_unmapdev(vm_offset_t, vm_size_t); 301 vm_page_t pmap_use_pt(pmap_t, vm_offset_t); 302 void pmap_debug(int); 303 void pmap_map_section(vm_offset_t, vm_offset_t, vm_offset_t, int, int); 304 void pmap_link_l2pt(vm_offset_t, vm_offset_t, struct pv_addr *); 305 vm_size_t pmap_map_chunk(vm_offset_t, vm_offset_t, vm_offset_t, vm_size_t, int, int); 306 void 307 pmap_map_entry(vm_offset_t l1pt, vm_offset_t va, vm_offset_t pa, int prot, 308 int cache); 309 int pmap_fault_fixup(pmap_t, vm_offset_t, vm_prot_t, int); 310 311 /* 312 * Definitions for MMU domains 313 */ 314 #define PMAP_DOMAINS 15 /* 15 'user' domains (0-14) */ 315 #define PMAP_DOMAIN_KERNEL 15 /* The kernel uses domain #15 */ 316 317 /* 318 * The new pmap ensures that page-tables are always mapping Write-Thru. 319 * Thus, on some platforms we can run fast and loose and avoid syncing PTEs 320 * on every change. 321 * 322 * Unfortunately, not all CPUs have a write-through cache mode. So we 323 * define PMAP_NEEDS_PTE_SYNC for C code to conditionally do PTE syncs, 324 * and if there is the chance for PTE syncs to be needed, we define 325 * PMAP_INCLUDE_PTE_SYNC so e.g. assembly code can include (and run) 326 * the code. 327 */ 328 extern int pmap_needs_pte_sync; 329 330 /* 331 * These macros define the various bit masks in the PTE. 332 * 333 * We use these macros since we use different bits on different processor 334 * models. 335 */ 336 #define L1_S_PROT_U (L1_S_AP(AP_U)) 337 #define L1_S_PROT_W (L1_S_AP(AP_W)) 338 #define L1_S_PROT_MASK (L1_S_PROT_U|L1_S_PROT_W) 339 340 #define L1_S_CACHE_MASK_generic (L1_S_B|L1_S_C) 341 #define L1_S_CACHE_MASK_xscale (L1_S_B|L1_S_C|L1_S_XSCALE_TEX(TEX_XSCALE_X)) 342 343 #define L2_L_PROT_U (L2_AP(AP_U)) 344 #define L2_L_PROT_W (L2_AP(AP_W)) 345 #define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W) 346 347 #define L2_L_CACHE_MASK_generic (L2_B|L2_C) 348 #define L2_L_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_L_TEX(TEX_XSCALE_X)) 349 350 #define L2_S_PROT_U_generic (L2_AP(AP_U)) 351 #define L2_S_PROT_W_generic (L2_AP(AP_W)) 352 #define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W) 353 354 #define L2_S_PROT_U_xscale (L2_AP0(AP_U)) 355 #define L2_S_PROT_W_xscale (L2_AP0(AP_W)) 356 #define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W) 357 358 #define L2_S_CACHE_MASK_generic (L2_B|L2_C) 359 #define L2_S_CACHE_MASK_xscale (L2_B|L2_C|L2_XSCALE_T_TEX(TEX_XSCALE_X)) 360 361 #define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP) 362 #define L1_S_PROTO_xscale (L1_TYPE_S) 363 364 #define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2) 365 #define L1_C_PROTO_xscale (L1_TYPE_C) 366 367 #define L2_L_PROTO (L2_TYPE_L) 368 369 #define L2_S_PROTO_generic (L2_TYPE_S) 370 #define L2_S_PROTO_xscale (L2_TYPE_XSCALE_XS) 371 372 /* 373 * User-visible names for the ones that vary with MMU class. 374 */ 375 376 #if ARM_NMMUS > 1 377 /* More than one MMU class configured; use variables. */ 378 #define L2_S_PROT_U pte_l2_s_prot_u 379 #define L2_S_PROT_W pte_l2_s_prot_w 380 #define L2_S_PROT_MASK pte_l2_s_prot_mask 381 382 #define L1_S_CACHE_MASK pte_l1_s_cache_mask 383 #define L2_L_CACHE_MASK pte_l2_l_cache_mask 384 #define L2_S_CACHE_MASK pte_l2_s_cache_mask 385 386 #define L1_S_PROTO pte_l1_s_proto 387 #define L1_C_PROTO pte_l1_c_proto 388 #define L2_S_PROTO pte_l2_s_proto 389 390 #elif (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 391 #define L2_S_PROT_U L2_S_PROT_U_generic 392 #define L2_S_PROT_W L2_S_PROT_W_generic 393 #define L2_S_PROT_MASK L2_S_PROT_MASK_generic 394 395 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_generic 396 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_generic 397 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_generic 398 399 #define L1_S_PROTO L1_S_PROTO_generic 400 #define L1_C_PROTO L1_C_PROTO_generic 401 #define L2_S_PROTO L2_S_PROTO_generic 402 403 #elif ARM_MMU_XSCALE == 1 404 #define L2_S_PROT_U L2_S_PROT_U_xscale 405 #define L2_S_PROT_W L2_S_PROT_W_xscale 406 #define L2_S_PROT_MASK L2_S_PROT_MASK_xscale 407 408 #define L1_S_CACHE_MASK L1_S_CACHE_MASK_xscale 409 #define L2_L_CACHE_MASK L2_L_CACHE_MASK_xscale 410 #define L2_S_CACHE_MASK L2_S_CACHE_MASK_xscale 411 412 #define L1_S_PROTO L1_S_PROTO_xscale 413 #define L1_C_PROTO L1_C_PROTO_xscale 414 #define L2_S_PROTO L2_S_PROTO_xscale 415 416 #endif /* ARM_NMMUS > 1 */ 417 418 #if (ARM_MMU_SA1 == 1) && (ARM_NMMUS == 1) 419 #define PMAP_NEEDS_PTE_SYNC 1 420 #define PMAP_INCLUDE_PTE_SYNC 421 #elif (ARM_MMU_SA1 == 0) 422 #define PMAP_NEEDS_PTE_SYNC 0 423 #endif 424 425 /* 426 * These macros return various bits based on kernel/user and protection. 427 * Note that the compiler will usually fold these at compile time. 428 */ 429 #define L1_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L1_S_PROT_U : 0) | \ 430 (((pr) & VM_PROT_WRITE) ? L1_S_PROT_W : 0)) 431 432 #define L2_L_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_L_PROT_U : 0) | \ 433 (((pr) & VM_PROT_WRITE) ? L2_L_PROT_W : 0)) 434 435 #define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \ 436 (((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0)) 437 438 /* 439 * Macros to test if a mapping is mappable with an L1 Section mapping 440 * or an L2 Large Page mapping. 441 */ 442 #define L1_S_MAPPABLE_P(va, pa, size) \ 443 ((((va) | (pa)) & L1_S_OFFSET) == 0 && (size) >= L1_S_SIZE) 444 445 #define L2_L_MAPPABLE_P(va, pa, size) \ 446 ((((va) | (pa)) & L2_L_OFFSET) == 0 && (size) >= L2_L_SIZE) 447 448 /* 449 * Provide a fallback in case we were not able to determine it at 450 * compile-time. 451 */ 452 #ifndef PMAP_NEEDS_PTE_SYNC 453 #define PMAP_NEEDS_PTE_SYNC pmap_needs_pte_sync 454 #define PMAP_INCLUDE_PTE_SYNC 455 #endif 456 457 #define PTE_SYNC(pte) \ 458 do { \ 459 if (PMAP_NEEDS_PTE_SYNC) \ 460 cpu_dcache_wb_range((vm_offset_t)(pte), sizeof(pt_entry_t));\ 461 } while (/*CONSTCOND*/0) 462 463 #define PTE_SYNC_RANGE(pte, cnt) \ 464 do { \ 465 if (PMAP_NEEDS_PTE_SYNC) { \ 466 cpu_dcache_wb_range((vm_offset_t)(pte), \ 467 (cnt) << 2); /* * sizeof(pt_entry_t) */ \ 468 } \ 469 } while (/*CONSTCOND*/0) 470 471 extern pt_entry_t pte_l1_s_cache_mode; 472 extern pt_entry_t pte_l1_s_cache_mask; 473 474 extern pt_entry_t pte_l2_l_cache_mode; 475 extern pt_entry_t pte_l2_l_cache_mask; 476 477 extern pt_entry_t pte_l2_s_cache_mode; 478 extern pt_entry_t pte_l2_s_cache_mask; 479 480 extern pt_entry_t pte_l1_s_cache_mode_pt; 481 extern pt_entry_t pte_l2_l_cache_mode_pt; 482 extern pt_entry_t pte_l2_s_cache_mode_pt; 483 484 extern pt_entry_t pte_l2_s_prot_u; 485 extern pt_entry_t pte_l2_s_prot_w; 486 extern pt_entry_t pte_l2_s_prot_mask; 487 488 extern pt_entry_t pte_l1_s_proto; 489 extern pt_entry_t pte_l1_c_proto; 490 extern pt_entry_t pte_l2_s_proto; 491 492 extern void (*pmap_copy_page_func)(vm_paddr_t, vm_paddr_t); 493 extern void (*pmap_zero_page_func)(vm_paddr_t, int, int); 494 495 #if (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 496 void pmap_copy_page_generic(vm_paddr_t, vm_paddr_t); 497 void pmap_zero_page_generic(vm_paddr_t, int, int); 498 499 void pmap_pte_init_generic(void); 500 #if defined(CPU_ARM8) 501 void pmap_pte_init_arm8(void); 502 #endif 503 #if defined(CPU_ARM9) 504 void pmap_pte_init_arm9(void); 505 #endif /* CPU_ARM9 */ 506 #if defined(CPU_ARM10) 507 void pmap_pte_init_arm10(void); 508 #endif /* CPU_ARM10 */ 509 #endif /* (ARM_MMU_GENERIC + ARM_MMU_SA1) != 0 */ 510 511 #if /* ARM_MMU_SA1 == */1 512 void pmap_pte_init_sa1(void); 513 #endif /* ARM_MMU_SA1 == 1 */ 514 515 #if ARM_MMU_XSCALE == 1 516 void pmap_copy_page_xscale(vm_paddr_t, vm_paddr_t); 517 void pmap_zero_page_xscale(vm_paddr_t, int, int); 518 519 void pmap_pte_init_xscale(void); 520 521 void xscale_setup_minidata(vm_offset_t, vm_offset_t, vm_offset_t); 522 523 #define PMAP_UAREA(va) pmap_uarea(va) 524 void pmap_uarea(vm_offset_t); 525 #endif /* ARM_MMU_XSCALE == 1 */ 526 #define PTE_KERNEL 0 527 #define PTE_USER 1 528 #define l1pte_valid(pde) ((pde) != 0) 529 #define l1pte_section_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_S) 530 #define l1pte_page_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_C) 531 #define l1pte_fpage_p(pde) (((pde) & L1_TYPE_MASK) == L1_TYPE_F) 532 533 #define l2pte_index(v) (((v) & L2_ADDR_BITS) >> L2_S_SHIFT) 534 #define l2pte_valid(pte) ((pte) != 0) 535 #define l2pte_pa(pte) ((pte) & L2_S_FRAME) 536 #define l2pte_minidata(pte) (((pte) & \ 537 (L2_B | L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X)))\ 538 == (L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X))) 539 540 /* L1 and L2 page table macros */ 541 #define pmap_pde_v(pde) l1pte_valid(*(pde)) 542 #define pmap_pde_section(pde) l1pte_section_p(*(pde)) 543 #define pmap_pde_page(pde) l1pte_page_p(*(pde)) 544 #define pmap_pde_fpage(pde) l1pte_fpage_p(*(pde)) 545 546 #define pmap_pte_v(pte) l2pte_valid(*(pte)) 547 #define pmap_pte_pa(pte) l2pte_pa(*(pte)) 548 549 /* Size of the kernel part of the L1 page table */ 550 #define KERNEL_PD_SIZE \ 551 (L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t)) 552 #define PTE_PAGETABLE 2 553 554 /* 555 * Flags that indicate attributes of pages or mappings of pages. 556 * 557 * The PVF_MOD and PVF_REF flags are stored in the mdpage for each 558 * page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual 559 * pv_entry's for each page. They live in the same "namespace" so 560 * that we can clear multiple attributes at a time. 561 * 562 * Note the "non-cacheable" flag generally means the page has 563 * multiple mappings in a given address space. 564 */ 565 #define PVF_MOD 0x01 /* page is modified */ 566 #define PVF_REF 0x02 /* page is referenced */ 567 #define PVF_WIRED 0x04 /* mapping is wired */ 568 #define PVF_WRITE 0x08 /* mapping is writable */ 569 #define PVF_EXEC 0x10 /* mapping is executable */ 570 #define PVF_UNC 0x20 /* mapping is 'user' non-cacheable */ 571 #define PVF_KNC 0x40 /* mapping is 'kernel' non-cacheable */ 572 #define PVF_NC (PVF_UNC|PVF_KNC) 573 574 void vector_page_setprot(int); 575 /* 576 * Routine: pmap_kextract 577 * Function: 578 * Extract the physical page address associated 579 * kernel virtual address. 580 */ 581 582 vm_paddr_t pmap_kextract(vm_offset_t); 583 584 void pmap_update(pmap_t); 585 #endif /* _KERNEL */ 586 587 #endif /* !LOCORE */ 588 589 #endif /* !_MACHINE_PMAP_H_ */ 590