1 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * 41 * $FreeBSD$ 42 */ 43 44 #ifndef _MACHINE_CPUFUNC_H_ 45 #define _MACHINE_CPUFUNC_H_ 46 47 #ifdef _KERNEL 48 49 #include <sys/types.h> 50 #include <machine/cpuconf.h> 51 #include <machine/katelib.h> /* For in[bwl] and out[bwl] */ 52 53 static __inline void 54 breakpoint(void) 55 { 56 __asm(".word 0xe7ffffff"); 57 } 58 59 struct cpu_functions { 60 61 /* CPU functions */ 62 63 u_int (*cf_id) (void); 64 void (*cf_cpwait) (void); 65 66 /* MMU functions */ 67 68 u_int (*cf_control) (u_int bic, u_int eor); 69 void (*cf_domains) (u_int domains); 70 void (*cf_setttb) (u_int ttb); 71 u_int (*cf_faultstatus) (void); 72 u_int (*cf_faultaddress) (void); 73 74 /* TLB functions */ 75 76 void (*cf_tlb_flushID) (void); 77 void (*cf_tlb_flushID_SE) (u_int va); 78 void (*cf_tlb_flushI) (void); 79 void (*cf_tlb_flushI_SE) (u_int va); 80 void (*cf_tlb_flushD) (void); 81 void (*cf_tlb_flushD_SE) (u_int va); 82 83 /* 84 * Cache operations: 85 * 86 * We define the following primitives: 87 * 88 * icache_sync_all Synchronize I-cache 89 * icache_sync_range Synchronize I-cache range 90 * 91 * dcache_wbinv_all Write-back and Invalidate D-cache 92 * dcache_wbinv_range Write-back and Invalidate D-cache range 93 * dcache_inv_range Invalidate D-cache range 94 * dcache_wb_range Write-back D-cache range 95 * 96 * idcache_wbinv_all Write-back and Invalidate D-cache, 97 * Invalidate I-cache 98 * idcache_wbinv_range Write-back and Invalidate D-cache, 99 * Invalidate I-cache range 100 * 101 * Note that the ARM term for "write-back" is "clean". We use 102 * the term "write-back" since it's a more common way to describe 103 * the operation. 104 * 105 * There are some rules that must be followed: 106 * 107 * ID-cache Invalidate All: 108 * Unlike other functions, this one must never write back. 109 * It is used to intialize the MMU when it is in an unknown 110 * state (such as when it may have lines tagged as valid 111 * that belong to a previous set of mappings). 112 * 113 * I-cache Synch (all or range): 114 * The goal is to synchronize the instruction stream, 115 * so you may beed to write-back dirty D-cache blocks 116 * first. If a range is requested, and you can't 117 * synchronize just a range, you have to hit the whole 118 * thing. 119 * 120 * D-cache Write-Back and Invalidate range: 121 * If you can't WB-Inv a range, you must WB-Inv the 122 * entire D-cache. 123 * 124 * D-cache Invalidate: 125 * If you can't Inv the D-cache, you must Write-Back 126 * and Invalidate. Code that uses this operation 127 * MUST NOT assume that the D-cache will not be written 128 * back to memory. 129 * 130 * D-cache Write-Back: 131 * If you can't Write-back without doing an Inv, 132 * that's fine. Then treat this as a WB-Inv. 133 * Skipping the invalidate is merely an optimization. 134 * 135 * All operations: 136 * Valid virtual addresses must be passed to each 137 * cache operation. 138 */ 139 void (*cf_icache_sync_all) (void); 140 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 141 142 void (*cf_dcache_wbinv_all) (void); 143 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 144 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 145 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 146 147 void (*cf_idcache_inv_all) (void); 148 void (*cf_idcache_wbinv_all) (void); 149 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 150 void (*cf_l2cache_wbinv_all) (void); 151 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 152 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 153 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 154 155 /* Other functions */ 156 157 void (*cf_flush_prefetchbuf) (void); 158 void (*cf_drain_writebuf) (void); 159 void (*cf_flush_brnchtgt_C) (void); 160 void (*cf_flush_brnchtgt_E) (u_int va); 161 162 void (*cf_sleep) (int mode); 163 164 /* Soft functions */ 165 166 int (*cf_dataabt_fixup) (void *arg); 167 int (*cf_prefetchabt_fixup) (void *arg); 168 169 void (*cf_context_switch) (void); 170 171 void (*cf_setup) (char *string); 172 }; 173 174 extern struct cpu_functions cpufuncs; 175 extern u_int cputype; 176 177 #define cpu_id() cpufuncs.cf_id() 178 #define cpu_cpwait() cpufuncs.cf_cpwait() 179 180 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 181 #define cpu_domains(d) cpufuncs.cf_domains(d) 182 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 183 #define cpu_faultstatus() cpufuncs.cf_faultstatus() 184 #define cpu_faultaddress() cpufuncs.cf_faultaddress() 185 186 #ifndef SMP 187 188 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 189 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 190 #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 191 #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 192 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 193 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 194 195 #else 196 void tlb_broadcast(int); 197 198 #if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) 199 #define TLB_BROADCAST /* No need to explicitely send an IPI */ 200 #else 201 #define TLB_BROADCAST tlb_broadcast(7) 202 #endif 203 204 #define cpu_tlb_flushID() do { \ 205 cpufuncs.cf_tlb_flushID(); \ 206 TLB_BROADCAST; \ 207 } while(0) 208 209 #define cpu_tlb_flushID_SE(e) do { \ 210 cpufuncs.cf_tlb_flushID_SE(e); \ 211 TLB_BROADCAST; \ 212 } while(0) 213 214 215 #define cpu_tlb_flushI() do { \ 216 cpufuncs.cf_tlb_flushI(); \ 217 TLB_BROADCAST; \ 218 } while(0) 219 220 221 #define cpu_tlb_flushI_SE(e) do { \ 222 cpufuncs.cf_tlb_flushI_SE(e); \ 223 TLB_BROADCAST; \ 224 } while(0) 225 226 227 #define cpu_tlb_flushD() do { \ 228 cpufuncs.cf_tlb_flushD(); \ 229 TLB_BROADCAST; \ 230 } while(0) 231 232 233 #define cpu_tlb_flushD_SE(e) do { \ 234 cpufuncs.cf_tlb_flushD_SE(e); \ 235 TLB_BROADCAST; \ 236 } while(0) 237 238 #endif 239 240 #define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 241 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 242 243 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 244 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 245 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 246 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 247 248 #define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all() 249 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 250 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 251 #define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 252 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 253 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 254 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 255 256 #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 257 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 258 #define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 259 #define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 260 261 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 262 263 #define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 264 #define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 265 #define ABORT_FIXUP_OK 0 /* fixup succeeded */ 266 #define ABORT_FIXUP_FAILED 1 /* fixup failed */ 267 #define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 268 269 #define cpu_setup(a) cpufuncs.cf_setup(a) 270 271 int set_cpufuncs (void); 272 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 273 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 274 275 void cpufunc_nullop (void); 276 int cpufunc_null_fixup (void *); 277 int early_abort_fixup (void *); 278 int late_abort_fixup (void *); 279 u_int cpufunc_id (void); 280 u_int cpufunc_cpuid (void); 281 u_int cpufunc_control (u_int clear, u_int bic); 282 void cpufunc_domains (u_int domains); 283 u_int cpufunc_faultstatus (void); 284 u_int cpufunc_faultaddress (void); 285 u_int cpu_pfr (int); 286 287 #if defined(CPU_FA526) || defined(CPU_FA626TE) 288 void fa526_setup (char *arg); 289 void fa526_setttb (u_int ttb); 290 void fa526_context_switch (void); 291 void fa526_cpu_sleep (int); 292 void fa526_tlb_flushI_SE (u_int); 293 void fa526_tlb_flushID_SE (u_int); 294 void fa526_flush_prefetchbuf (void); 295 void fa526_flush_brnchtgt_E (u_int); 296 297 void fa526_icache_sync_all (void); 298 void fa526_icache_sync_range(vm_offset_t start, vm_size_t end); 299 void fa526_dcache_wbinv_all (void); 300 void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end); 301 void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end); 302 void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end); 303 void fa526_idcache_wbinv_all(void); 304 void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end); 305 #endif 306 307 308 #ifdef CPU_ARM9 309 void arm9_setttb (u_int); 310 311 void arm9_tlb_flushID_SE (u_int va); 312 313 void arm9_icache_sync_all (void); 314 void arm9_icache_sync_range (vm_offset_t, vm_size_t); 315 316 void arm9_dcache_wbinv_all (void); 317 void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); 318 void arm9_dcache_inv_range (vm_offset_t, vm_size_t); 319 void arm9_dcache_wb_range (vm_offset_t, vm_size_t); 320 321 void arm9_idcache_wbinv_all (void); 322 void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); 323 324 void arm9_context_switch (void); 325 326 void arm9_setup (char *string); 327 328 extern unsigned arm9_dcache_sets_max; 329 extern unsigned arm9_dcache_sets_inc; 330 extern unsigned arm9_dcache_index_max; 331 extern unsigned arm9_dcache_index_inc; 332 #endif 333 334 #if defined(CPU_ARM9E) || defined(CPU_ARM10) 335 void arm10_setttb (u_int); 336 337 void arm10_tlb_flushID_SE (u_int); 338 void arm10_tlb_flushI_SE (u_int); 339 340 void arm10_icache_sync_all (void); 341 void arm10_icache_sync_range (vm_offset_t, vm_size_t); 342 343 void arm10_dcache_wbinv_all (void); 344 void arm10_dcache_wbinv_range (vm_offset_t, vm_size_t); 345 void arm10_dcache_inv_range (vm_offset_t, vm_size_t); 346 void arm10_dcache_wb_range (vm_offset_t, vm_size_t); 347 348 void arm10_idcache_wbinv_all (void); 349 void arm10_idcache_wbinv_range (vm_offset_t, vm_size_t); 350 351 void arm10_context_switch (void); 352 353 void arm10_setup (char *string); 354 355 extern unsigned arm10_dcache_sets_max; 356 extern unsigned arm10_dcache_sets_inc; 357 extern unsigned arm10_dcache_index_max; 358 extern unsigned arm10_dcache_index_inc; 359 360 u_int sheeva_control_ext (u_int, u_int); 361 void sheeva_cpu_sleep (int); 362 void sheeva_setttb (u_int); 363 void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); 364 void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); 365 void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); 366 void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); 367 368 void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); 369 void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); 370 void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); 371 void sheeva_l2cache_wbinv_all (void); 372 #endif 373 374 #if defined(CPU_ARM1136) || defined(CPU_ARM1176) || \ 375 defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) 376 void arm11_setttb (u_int); 377 void arm11_sleep (int); 378 379 void arm11_tlb_flushID_SE (u_int); 380 void arm11_tlb_flushI_SE (u_int); 381 382 void arm11_context_switch (void); 383 384 void arm11_setup (char *string); 385 void arm11_tlb_flushID (void); 386 void arm11_tlb_flushI (void); 387 void arm11_tlb_flushD (void); 388 void arm11_tlb_flushD_SE (u_int va); 389 390 void arm11_drain_writebuf (void); 391 392 void pj4b_setttb (u_int); 393 394 void pj4b_drain_readbuf (void); 395 void pj4b_flush_brnchtgt_all (void); 396 void pj4b_flush_brnchtgt_va (u_int); 397 void pj4b_sleep (int); 398 399 void armv6_icache_sync_all (void); 400 void armv6_icache_sync_range (vm_offset_t, vm_size_t); 401 402 void armv6_dcache_wbinv_all (void); 403 void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t); 404 void armv6_dcache_inv_range (vm_offset_t, vm_size_t); 405 void armv6_dcache_wb_range (vm_offset_t, vm_size_t); 406 407 void armv6_idcache_inv_all (void); 408 void armv6_idcache_wbinv_all (void); 409 void armv6_idcache_wbinv_range (vm_offset_t, vm_size_t); 410 411 void armv7_setttb (u_int); 412 void armv7_tlb_flushID (void); 413 void armv7_tlb_flushID_SE (u_int); 414 void armv7_icache_sync_range (vm_offset_t, vm_size_t); 415 void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); 416 void armv7_idcache_inv_all (void); 417 void armv7_dcache_wbinv_all (void); 418 void armv7_idcache_wbinv_all (void); 419 void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t); 420 void armv7_dcache_inv_range (vm_offset_t, vm_size_t); 421 void armv7_dcache_wb_range (vm_offset_t, vm_size_t); 422 void armv7_cpu_sleep (int); 423 void armv7_setup (char *string); 424 void armv7_context_switch (void); 425 void armv7_drain_writebuf (void); 426 void armv7_sev (void); 427 void armv7_sleep (int unused); 428 u_int armv7_auxctrl (u_int, u_int); 429 void pj4bv7_setup (char *string); 430 void pj4b_config (void); 431 432 int get_core_id (void); 433 434 void armadaxp_idcache_wbinv_all (void); 435 436 void cortexa_setup (char *); 437 #endif 438 439 #if defined(CPU_ARM1136) || defined(CPU_ARM1176) 440 void arm11x6_setttb (u_int); 441 void arm11x6_idcache_wbinv_all (void); 442 void arm11x6_dcache_wbinv_all (void); 443 void arm11x6_icache_sync_all (void); 444 void arm11x6_flush_prefetchbuf (void); 445 void arm11x6_icache_sync_range (vm_offset_t, vm_size_t); 446 void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t); 447 void arm11x6_setup (char *string); 448 void arm11x6_sleep (int); /* no ref. for errata */ 449 #endif 450 #if defined(CPU_ARM1136) 451 void arm1136_sleep_rev0 (int); /* for errata 336501 */ 452 #endif 453 454 #if defined(CPU_ARM9E) || defined (CPU_ARM10) 455 void armv5_ec_setttb(u_int); 456 457 void armv5_ec_icache_sync_all(void); 458 void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); 459 460 void armv5_ec_dcache_wbinv_all(void); 461 void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); 462 void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); 463 void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); 464 465 void armv5_ec_idcache_wbinv_all(void); 466 void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); 467 #endif 468 469 #if defined (CPU_ARM10) 470 void armv5_setttb(u_int); 471 472 void armv5_icache_sync_all(void); 473 void armv5_icache_sync_range(vm_offset_t, vm_size_t); 474 475 void armv5_dcache_wbinv_all(void); 476 void armv5_dcache_wbinv_range(vm_offset_t, vm_size_t); 477 void armv5_dcache_inv_range(vm_offset_t, vm_size_t); 478 void armv5_dcache_wb_range(vm_offset_t, vm_size_t); 479 480 void armv5_idcache_wbinv_all(void); 481 void armv5_idcache_wbinv_range(vm_offset_t, vm_size_t); 482 483 extern unsigned armv5_dcache_sets_max; 484 extern unsigned armv5_dcache_sets_inc; 485 extern unsigned armv5_dcache_index_max; 486 extern unsigned armv5_dcache_index_inc; 487 #endif 488 489 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 490 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 491 defined(CPU_FA526) || defined(CPU_FA626TE) || \ 492 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 493 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 494 495 void armv4_tlb_flushID (void); 496 void armv4_tlb_flushI (void); 497 void armv4_tlb_flushD (void); 498 void armv4_tlb_flushD_SE (u_int va); 499 500 void armv4_drain_writebuf (void); 501 void armv4_idcache_inv_all (void); 502 #endif 503 504 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 505 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 506 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 507 void xscale_cpwait (void); 508 509 void xscale_cpu_sleep (int mode); 510 511 u_int xscale_control (u_int clear, u_int bic); 512 513 void xscale_setttb (u_int ttb); 514 515 void xscale_tlb_flushID_SE (u_int va); 516 517 void xscale_cache_flushID (void); 518 void xscale_cache_flushI (void); 519 void xscale_cache_flushD (void); 520 void xscale_cache_flushD_SE (u_int entry); 521 522 void xscale_cache_cleanID (void); 523 void xscale_cache_cleanD (void); 524 void xscale_cache_cleanD_E (u_int entry); 525 526 void xscale_cache_clean_minidata (void); 527 528 void xscale_cache_purgeID (void); 529 void xscale_cache_purgeID_E (u_int entry); 530 void xscale_cache_purgeD (void); 531 void xscale_cache_purgeD_E (u_int entry); 532 533 void xscale_cache_syncI (void); 534 void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 535 void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 536 void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 537 void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 538 void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 539 void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 540 541 void xscale_context_switch (void); 542 543 void xscale_setup (char *string); 544 #endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 545 CPU_XSCALE_80219 */ 546 547 #ifdef CPU_XSCALE_81342 548 549 void xscalec3_l2cache_purge (void); 550 void xscalec3_cache_purgeID (void); 551 void xscalec3_cache_purgeD (void); 552 void xscalec3_cache_cleanID (void); 553 void xscalec3_cache_cleanD (void); 554 void xscalec3_cache_syncI (void); 555 556 void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 557 void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 558 void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 559 void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 560 void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end); 561 562 void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t); 563 void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end); 564 void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end); 565 566 567 void xscalec3_setttb (u_int ttb); 568 void xscalec3_context_switch (void); 569 570 #endif /* CPU_XSCALE_81342 */ 571 572 #define tlb_flush cpu_tlb_flushID 573 #define setttb cpu_setttb 574 #define drain_writebuf cpu_drain_writebuf 575 576 /* 577 * Macros for manipulating CPU interrupts 578 */ 579 static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__)); 580 581 static __inline u_int32_t 582 __set_cpsr_c(u_int bic, u_int eor) 583 { 584 u_int32_t tmp, ret; 585 586 __asm __volatile( 587 "mrs %0, cpsr\n" /* Get the CPSR */ 588 "bic %1, %0, %2\n" /* Clear bits */ 589 "eor %1, %1, %3\n" /* XOR bits */ 590 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 591 : "=&r" (ret), "=&r" (tmp) 592 : "r" (bic), "r" (eor) : "memory"); 593 594 return ret; 595 } 596 597 #define ARM_CPSR_F32 (1 << 6) /* FIQ disable */ 598 #define ARM_CPSR_I32 (1 << 7) /* IRQ disable */ 599 600 #define disable_interrupts(mask) \ 601 (__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), \ 602 (mask) & (ARM_CPSR_I32 | ARM_CPSR_F32))) 603 604 #define enable_interrupts(mask) \ 605 (__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), 0)) 606 607 #define restore_interrupts(old_cpsr) \ 608 (__set_cpsr_c((ARM_CPSR_I32 | ARM_CPSR_F32), \ 609 (old_cpsr) & (ARM_CPSR_I32 | ARM_CPSR_F32))) 610 611 static __inline register_t 612 intr_disable(void) 613 { 614 register_t s; 615 616 s = disable_interrupts(ARM_CPSR_I32 | ARM_CPSR_F32); 617 return (s); 618 } 619 620 static __inline void 621 intr_restore(register_t s) 622 { 623 624 restore_interrupts(s); 625 } 626 627 /* Functions to manipulate the CPSR. */ 628 u_int SetCPSR(u_int bic, u_int eor); 629 u_int GetCPSR(void); 630 631 /* 632 * Functions to manipulate cpu r13 633 * (in arm/arm32/setstack.S) 634 */ 635 636 void set_stackptr (u_int mode, u_int address); 637 u_int get_stackptr (u_int mode); 638 639 /* 640 * Miscellany 641 */ 642 643 int get_pc_str_offset (void); 644 645 /* 646 * CPU functions from locore.S 647 */ 648 649 void cpu_reset (void) __attribute__((__noreturn__)); 650 651 /* 652 * Cache info variables. 653 */ 654 655 /* PRIMARY CACHE VARIABLES */ 656 extern int arm_picache_size; 657 extern int arm_picache_line_size; 658 extern int arm_picache_ways; 659 660 extern int arm_pdcache_size; /* and unified */ 661 extern int arm_pdcache_line_size; 662 extern int arm_pdcache_ways; 663 664 extern int arm_pcache_type; 665 extern int arm_pcache_unified; 666 667 extern int arm_dcache_align; 668 extern int arm_dcache_align_mask; 669 670 extern u_int arm_cache_level; 671 extern u_int arm_cache_loc; 672 extern u_int arm_cache_type[14]; 673 674 #endif /* _KERNEL */ 675 #endif /* _MACHINE_CPUFUNC_H_ */ 676 677 /* End of cpufunc.h */ 678