1 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * 41 * $FreeBSD$ 42 */ 43 44 #ifndef _MACHINE_CPUFUNC_H_ 45 #define _MACHINE_CPUFUNC_H_ 46 47 #ifdef _KERNEL 48 49 #include <sys/types.h> 50 #include <machine/armreg.h> 51 52 static __inline void 53 breakpoint(void) 54 { 55 __asm(".word 0xe7ffffff"); 56 } 57 58 struct cpu_functions { 59 60 /* CPU functions */ 61 #if __ARM_ARCH < 6 62 void (*cf_cpwait) (void); 63 64 /* MMU functions */ 65 66 u_int (*cf_control) (u_int bic, u_int eor); 67 void (*cf_setttb) (u_int ttb); 68 69 /* TLB functions */ 70 71 void (*cf_tlb_flushID) (void); 72 void (*cf_tlb_flushID_SE) (u_int va); 73 void (*cf_tlb_flushD) (void); 74 void (*cf_tlb_flushD_SE) (u_int va); 75 76 /* 77 * Cache operations: 78 * 79 * We define the following primitives: 80 * 81 * icache_sync_range Synchronize I-cache range 82 * 83 * dcache_wbinv_all Write-back and Invalidate D-cache 84 * dcache_wbinv_range Write-back and Invalidate D-cache range 85 * dcache_inv_range Invalidate D-cache range 86 * dcache_wb_range Write-back D-cache range 87 * 88 * idcache_wbinv_all Write-back and Invalidate D-cache, 89 * Invalidate I-cache 90 * idcache_wbinv_range Write-back and Invalidate D-cache, 91 * Invalidate I-cache range 92 * 93 * Note that the ARM term for "write-back" is "clean". We use 94 * the term "write-back" since it's a more common way to describe 95 * the operation. 96 * 97 * There are some rules that must be followed: 98 * 99 * ID-cache Invalidate All: 100 * Unlike other functions, this one must never write back. 101 * It is used to intialize the MMU when it is in an unknown 102 * state (such as when it may have lines tagged as valid 103 * that belong to a previous set of mappings). 104 * 105 * I-cache Sync range: 106 * The goal is to synchronize the instruction stream, 107 * so you may beed to write-back dirty D-cache blocks 108 * first. If a range is requested, and you can't 109 * synchronize just a range, you have to hit the whole 110 * thing. 111 * 112 * D-cache Write-Back and Invalidate range: 113 * If you can't WB-Inv a range, you must WB-Inv the 114 * entire D-cache. 115 * 116 * D-cache Invalidate: 117 * If you can't Inv the D-cache, you must Write-Back 118 * and Invalidate. Code that uses this operation 119 * MUST NOT assume that the D-cache will not be written 120 * back to memory. 121 * 122 * D-cache Write-Back: 123 * If you can't Write-back without doing an Inv, 124 * that's fine. Then treat this as a WB-Inv. 125 * Skipping the invalidate is merely an optimization. 126 * 127 * All operations: 128 * Valid virtual addresses must be passed to each 129 * cache operation. 130 */ 131 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 132 133 void (*cf_dcache_wbinv_all) (void); 134 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 135 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 136 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 137 138 void (*cf_idcache_inv_all) (void); 139 void (*cf_idcache_wbinv_all) (void); 140 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 141 #endif 142 void (*cf_l2cache_wbinv_all) (void); 143 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 144 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 145 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 146 void (*cf_l2cache_drain_writebuf) (void); 147 148 /* Other functions */ 149 150 #if __ARM_ARCH < 6 151 void (*cf_drain_writebuf) (void); 152 #endif 153 154 void (*cf_sleep) (int mode); 155 156 #if __ARM_ARCH < 6 157 /* Soft functions */ 158 159 void (*cf_context_switch) (void); 160 #endif 161 162 void (*cf_setup) (void); 163 }; 164 165 extern struct cpu_functions cpufuncs; 166 extern u_int cputype; 167 168 #if __ARM_ARCH < 6 169 #define cpu_cpwait() cpufuncs.cf_cpwait() 170 171 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 172 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 173 174 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 175 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 176 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 177 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 178 179 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 180 181 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 182 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 183 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 184 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 185 186 #define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all() 187 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 188 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 189 #endif 190 191 #define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 192 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 193 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 194 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 195 #define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf() 196 197 #if __ARM_ARCH < 6 198 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 199 #endif 200 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 201 202 #define cpu_setup() cpufuncs.cf_setup() 203 204 int set_cpufuncs (void); 205 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 206 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 207 208 void cpufunc_nullop (void); 209 u_int cpu_ident (void); 210 u_int cpufunc_control (u_int clear, u_int bic); 211 void cpu_domains (u_int domains); 212 u_int cpu_faultstatus (void); 213 u_int cpu_faultaddress (void); 214 u_int cpu_get_control (void); 215 u_int cpu_pfr (int); 216 217 #if defined(CPU_FA526) 218 void fa526_setup (void); 219 void fa526_setttb (u_int ttb); 220 void fa526_context_switch (void); 221 void fa526_cpu_sleep (int); 222 void fa526_tlb_flushID_SE (u_int); 223 224 void fa526_icache_sync_range(vm_offset_t start, vm_size_t end); 225 void fa526_dcache_wbinv_all (void); 226 void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end); 227 void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end); 228 void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end); 229 void fa526_idcache_wbinv_all(void); 230 void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end); 231 #endif 232 233 234 #if defined(CPU_ARM9) || defined(CPU_ARM9E) 235 void arm9_setttb (u_int); 236 void arm9_tlb_flushID_SE (u_int va); 237 void arm9_context_switch (void); 238 #endif 239 240 #if defined(CPU_ARM9) 241 void arm9_icache_sync_range (vm_offset_t, vm_size_t); 242 243 void arm9_dcache_wbinv_all (void); 244 void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); 245 void arm9_dcache_inv_range (vm_offset_t, vm_size_t); 246 void arm9_dcache_wb_range (vm_offset_t, vm_size_t); 247 248 void arm9_idcache_wbinv_all (void); 249 void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); 250 251 void arm9_setup (void); 252 253 extern unsigned arm9_dcache_sets_max; 254 extern unsigned arm9_dcache_sets_inc; 255 extern unsigned arm9_dcache_index_max; 256 extern unsigned arm9_dcache_index_inc; 257 #endif 258 259 #if defined(CPU_ARM9E) 260 void arm10_setup (void); 261 262 u_int sheeva_control_ext (u_int, u_int); 263 void sheeva_cpu_sleep (int); 264 void sheeva_setttb (u_int); 265 void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); 266 void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); 267 void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); 268 void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); 269 270 void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); 271 void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); 272 void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); 273 void sheeva_l2cache_wbinv_all (void); 274 #endif 275 276 #if defined(CPU_MV_PJ4B) 277 void armv6_idcache_wbinv_all (void); 278 #endif 279 #if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) 280 void armv7_idcache_wbinv_all (void); 281 void armv7_cpu_sleep (int); 282 void armv7_setup (void); 283 void armv7_drain_writebuf (void); 284 285 void cortexa_setup (void); 286 #endif 287 #if defined(CPU_MV_PJ4B) 288 void pj4b_config (void); 289 void pj4bv7_setup (void); 290 #endif 291 292 #if defined(CPU_ARM1176) 293 void arm11_drain_writebuf (void); 294 295 void arm11x6_setup (void); 296 void arm11x6_sleep (int); /* no ref. for errata */ 297 #endif 298 299 #if defined(CPU_ARM9E) 300 void armv5_ec_setttb(u_int); 301 302 void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); 303 304 void armv5_ec_dcache_wbinv_all(void); 305 void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); 306 void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); 307 void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); 308 309 void armv5_ec_idcache_wbinv_all(void); 310 void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); 311 #endif 312 313 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 314 defined(CPU_FA526) || \ 315 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 316 defined(CPU_XSCALE_81342) 317 318 void armv4_tlb_flushID (void); 319 void armv4_tlb_flushD (void); 320 void armv4_tlb_flushD_SE (u_int va); 321 322 void armv4_drain_writebuf (void); 323 void armv4_idcache_inv_all (void); 324 #endif 325 326 #if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 327 defined(CPU_XSCALE_81342) 328 void xscale_cpwait (void); 329 330 void xscale_cpu_sleep (int mode); 331 332 u_int xscale_control (u_int clear, u_int bic); 333 334 void xscale_setttb (u_int ttb); 335 336 void xscale_tlb_flushID_SE (u_int va); 337 338 void xscale_cache_flushID (void); 339 void xscale_cache_flushI (void); 340 void xscale_cache_flushD (void); 341 void xscale_cache_flushD_SE (u_int entry); 342 343 void xscale_cache_cleanID (void); 344 void xscale_cache_cleanD (void); 345 void xscale_cache_cleanD_E (u_int entry); 346 347 void xscale_cache_clean_minidata (void); 348 349 void xscale_cache_purgeID (void); 350 void xscale_cache_purgeID_E (u_int entry); 351 void xscale_cache_purgeD (void); 352 void xscale_cache_purgeD_E (u_int entry); 353 354 void xscale_cache_syncI (void); 355 void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 356 void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 357 void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 358 void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 359 void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 360 void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 361 362 void xscale_context_switch (void); 363 364 void xscale_setup (void); 365 #endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ 366 367 #ifdef CPU_XSCALE_81342 368 369 void xscalec3_l2cache_purge (void); 370 void xscalec3_cache_purgeID (void); 371 void xscalec3_cache_purgeD (void); 372 void xscalec3_cache_cleanID (void); 373 void xscalec3_cache_cleanD (void); 374 void xscalec3_cache_syncI (void); 375 376 void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 377 void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 378 void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 379 void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 380 void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end); 381 382 void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t); 383 void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end); 384 void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end); 385 386 387 void xscalec3_setttb (u_int ttb); 388 void xscalec3_context_switch (void); 389 390 #endif /* CPU_XSCALE_81342 */ 391 392 /* 393 * Macros for manipulating CPU interrupts 394 */ 395 #if __ARM_ARCH < 6 396 #define __ARM_INTR_BITS (PSR_I | PSR_F) 397 #else 398 #define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A) 399 #endif 400 401 static __inline uint32_t 402 __set_cpsr(uint32_t bic, uint32_t eor) 403 { 404 uint32_t tmp, ret; 405 406 __asm __volatile( 407 "mrs %0, cpsr\n" /* Get the CPSR */ 408 "bic %1, %0, %2\n" /* Clear bits */ 409 "eor %1, %1, %3\n" /* XOR bits */ 410 "msr cpsr_xc, %1\n" /* Set the CPSR */ 411 : "=&r" (ret), "=&r" (tmp) 412 : "r" (bic), "r" (eor) : "memory"); 413 414 return ret; 415 } 416 417 static __inline uint32_t 418 disable_interrupts(uint32_t mask) 419 { 420 421 return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS)); 422 } 423 424 static __inline uint32_t 425 enable_interrupts(uint32_t mask) 426 { 427 428 return (__set_cpsr(mask & __ARM_INTR_BITS, 0)); 429 } 430 431 static __inline uint32_t 432 restore_interrupts(uint32_t old_cpsr) 433 { 434 435 return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS)); 436 } 437 438 static __inline register_t 439 intr_disable(void) 440 { 441 442 return (disable_interrupts(PSR_I | PSR_F)); 443 } 444 445 static __inline void 446 intr_restore(register_t s) 447 { 448 449 restore_interrupts(s); 450 } 451 #undef __ARM_INTR_BITS 452 453 /* 454 * Functions to manipulate cpu r13 455 * (in arm/arm32/setstack.S) 456 */ 457 458 void set_stackptr (u_int mode, u_int address); 459 u_int get_stackptr (u_int mode); 460 461 /* 462 * Miscellany 463 */ 464 465 int get_pc_str_offset (void); 466 467 /* 468 * CPU functions from locore.S 469 */ 470 471 void cpu_reset (void) __attribute__((__noreturn__)); 472 473 /* 474 * Cache info variables. 475 */ 476 477 /* PRIMARY CACHE VARIABLES */ 478 extern int arm_picache_size; 479 extern int arm_picache_line_size; 480 extern int arm_picache_ways; 481 482 extern int arm_pdcache_size; /* and unified */ 483 extern int arm_pdcache_line_size; 484 extern int arm_pdcache_ways; 485 486 extern int arm_pcache_type; 487 extern int arm_pcache_unified; 488 489 extern int arm_dcache_align; 490 extern int arm_dcache_align_mask; 491 492 extern u_int arm_cache_level; 493 extern u_int arm_cache_loc; 494 extern u_int arm_cache_type[14]; 495 496 #endif /* _KERNEL */ 497 #endif /* _MACHINE_CPUFUNC_H_ */ 498 499 /* End of cpufunc.h */ 500