1 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright (c) 1997 Mark Brinicombe. 7 * Copyright (c) 1997 Causality Limited 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Causality Limited. 21 * 4. The name of Causality Limited may not be used to endorse or promote 22 * products derived from this software without specific prior written 23 * permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * cpufunc.h 40 * 41 * Prototypes for cpu, mmu and tlb related functions. 42 * 43 * $FreeBSD$ 44 */ 45 46 #ifndef _MACHINE_CPUFUNC_H_ 47 #define _MACHINE_CPUFUNC_H_ 48 49 #ifdef _KERNEL 50 51 #include <sys/types.h> 52 #include <machine/armreg.h> 53 54 static __inline void 55 breakpoint(void) 56 { 57 __asm("udf 0xffff"); 58 } 59 60 struct cpu_functions { 61 /* CPU functions */ 62 void (*cf_l2cache_wbinv_all) (void); 63 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 64 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 65 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 66 void (*cf_l2cache_drain_writebuf) (void); 67 68 /* Other functions */ 69 70 void (*cf_sleep) (int mode); 71 72 void (*cf_setup) (void); 73 }; 74 75 extern struct cpu_functions cpufuncs; 76 extern u_int cputype; 77 78 #define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 79 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 80 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 81 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 82 #define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf() 83 84 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 85 86 #define cpu_setup() cpufuncs.cf_setup() 87 88 int set_cpufuncs (void); 89 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 90 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 91 92 void cpufunc_nullop (void); 93 u_int cpufunc_control (u_int clear, u_int bic); 94 void cpu_domains (u_int domains); 95 96 97 #if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) 98 void armv7_cpu_sleep (int); 99 #endif 100 #if defined(CPU_MV_PJ4B) 101 void pj4b_config (void); 102 #endif 103 104 #if defined(CPU_ARM1176) 105 void arm11x6_sleep (int); /* no ref. for errata */ 106 #endif 107 108 109 /* 110 * Macros for manipulating CPU interrupts 111 */ 112 #define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A) 113 114 static __inline uint32_t 115 __set_cpsr(uint32_t bic, uint32_t eor) 116 { 117 uint32_t tmp, ret; 118 119 __asm __volatile( 120 "mrs %0, cpsr\n" /* Get the CPSR */ 121 "bic %1, %0, %2\n" /* Clear bits */ 122 "eor %1, %1, %3\n" /* XOR bits */ 123 "msr cpsr_xc, %1\n" /* Set the CPSR */ 124 : "=&r" (ret), "=&r" (tmp) 125 : "r" (bic), "r" (eor) : "memory"); 126 127 return ret; 128 } 129 130 static __inline uint32_t 131 disable_interrupts(uint32_t mask) 132 { 133 134 return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS)); 135 } 136 137 static __inline uint32_t 138 enable_interrupts(uint32_t mask) 139 { 140 141 return (__set_cpsr(mask & __ARM_INTR_BITS, 0)); 142 } 143 144 static __inline uint32_t 145 restore_interrupts(uint32_t old_cpsr) 146 { 147 148 return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS)); 149 } 150 151 static __inline register_t 152 intr_disable(void) 153 { 154 155 return (disable_interrupts(PSR_I | PSR_F)); 156 } 157 158 static __inline void 159 intr_restore(register_t s) 160 { 161 162 restore_interrupts(s); 163 } 164 #undef __ARM_INTR_BITS 165 166 /* 167 * Functions to manipulate cpu r13 168 * (in arm/arm32/setstack.S) 169 */ 170 171 void set_stackptr (u_int mode, u_int address); 172 u_int get_stackptr (u_int mode); 173 174 /* 175 * CPU functions from locore.S 176 */ 177 178 void cpu_reset (void) __attribute__((__noreturn__)); 179 180 /* 181 * Cache info variables. 182 */ 183 184 /* PRIMARY CACHE VARIABLES */ 185 extern int arm_picache_size; 186 extern int arm_picache_line_size; 187 extern int arm_picache_ways; 188 189 extern int arm_pdcache_size; /* and unified */ 190 extern int arm_pdcache_line_size; 191 extern int arm_pdcache_ways; 192 193 extern int arm_pcache_type; 194 extern int arm_pcache_unified; 195 196 extern int arm_dcache_align; 197 extern int arm_dcache_align_mask; 198 199 extern u_int arm_cache_level; 200 extern u_int arm_cache_loc; 201 extern u_int arm_cache_type[14]; 202 203 #define HAVE_INLINE_FFS 204 205 static __inline __pure2 int 206 ffs(int mask) 207 { 208 209 return (__builtin_ffs(mask)); 210 } 211 212 #define HAVE_INLINE_FFSL 213 214 static __inline __pure2 int 215 ffsl(long mask) 216 { 217 218 return (__builtin_ffsl(mask)); 219 } 220 221 #define HAVE_INLINE_FFSLL 222 223 static __inline __pure2 int 224 ffsll(long long mask) 225 { 226 227 return (__builtin_ffsll(mask)); 228 } 229 230 #define HAVE_INLINE_FLS 231 232 static __inline __pure2 int 233 fls(int mask) 234 { 235 236 return (mask == 0 ? 0 : 237 8 * sizeof(mask) - __builtin_clz((u_int)mask)); 238 } 239 240 #define HAVE_INLINE_FLSL 241 242 static __inline __pure2 int 243 flsl(long mask) 244 { 245 246 return (mask == 0 ? 0 : 247 8 * sizeof(mask) - __builtin_clzl((u_long)mask)); 248 } 249 250 #define HAVE_INLINE_FLSLL 251 252 static __inline __pure2 int 253 flsll(long long mask) 254 { 255 256 return (mask == 0 ? 0 : 257 8 * sizeof(mask) - __builtin_clzll((unsigned long long)mask)); 258 } 259 #else /* !_KERNEL */ 260 261 static __inline void 262 breakpoint(void) 263 { 264 265 /* 266 * This matches the instruction used by GDB for software 267 * breakpoints. 268 */ 269 __asm("udf 0xfdee"); 270 } 271 272 #endif /* _KERNEL */ 273 #endif /* _MACHINE_CPUFUNC_H_ */ 274 275 /* End of cpufunc.h */ 276