1 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * 41 * $FreeBSD$ 42 */ 43 44 #ifndef _MACHINE_CPUFUNC_H_ 45 #define _MACHINE_CPUFUNC_H_ 46 47 #ifdef _KERNEL 48 49 #include <sys/types.h> 50 #include <machine/armreg.h> 51 #include <machine/cpuconf.h> 52 53 static __inline void 54 breakpoint(void) 55 { 56 __asm(".word 0xe7ffffff"); 57 } 58 59 struct cpu_functions { 60 61 /* CPU functions */ 62 63 void (*cf_cpwait) (void); 64 65 /* MMU functions */ 66 67 u_int (*cf_control) (u_int bic, u_int eor); 68 void (*cf_setttb) (u_int ttb); 69 70 /* TLB functions */ 71 72 void (*cf_tlb_flushID) (void); 73 void (*cf_tlb_flushID_SE) (u_int va); 74 void (*cf_tlb_flushD) (void); 75 void (*cf_tlb_flushD_SE) (u_int va); 76 77 /* 78 * Cache operations: 79 * 80 * We define the following primitives: 81 * 82 * icache_sync_all Synchronize I-cache 83 * icache_sync_range Synchronize I-cache range 84 * 85 * dcache_wbinv_all Write-back and Invalidate D-cache 86 * dcache_wbinv_range Write-back and Invalidate D-cache range 87 * dcache_inv_range Invalidate D-cache range 88 * dcache_wb_range Write-back D-cache range 89 * 90 * idcache_wbinv_all Write-back and Invalidate D-cache, 91 * Invalidate I-cache 92 * idcache_wbinv_range Write-back and Invalidate D-cache, 93 * Invalidate I-cache range 94 * 95 * Note that the ARM term for "write-back" is "clean". We use 96 * the term "write-back" since it's a more common way to describe 97 * the operation. 98 * 99 * There are some rules that must be followed: 100 * 101 * ID-cache Invalidate All: 102 * Unlike other functions, this one must never write back. 103 * It is used to intialize the MMU when it is in an unknown 104 * state (such as when it may have lines tagged as valid 105 * that belong to a previous set of mappings). 106 * 107 * I-cache Synch (all or range): 108 * The goal is to synchronize the instruction stream, 109 * so you may beed to write-back dirty D-cache blocks 110 * first. If a range is requested, and you can't 111 * synchronize just a range, you have to hit the whole 112 * thing. 113 * 114 * D-cache Write-Back and Invalidate range: 115 * If you can't WB-Inv a range, you must WB-Inv the 116 * entire D-cache. 117 * 118 * D-cache Invalidate: 119 * If you can't Inv the D-cache, you must Write-Back 120 * and Invalidate. Code that uses this operation 121 * MUST NOT assume that the D-cache will not be written 122 * back to memory. 123 * 124 * D-cache Write-Back: 125 * If you can't Write-back without doing an Inv, 126 * that's fine. Then treat this as a WB-Inv. 127 * Skipping the invalidate is merely an optimization. 128 * 129 * All operations: 130 * Valid virtual addresses must be passed to each 131 * cache operation. 132 */ 133 void (*cf_icache_sync_all) (void); 134 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 135 136 void (*cf_dcache_wbinv_all) (void); 137 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 138 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 139 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 140 141 void (*cf_idcache_inv_all) (void); 142 void (*cf_idcache_wbinv_all) (void); 143 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 144 void (*cf_l2cache_wbinv_all) (void); 145 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 146 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 147 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 148 void (*cf_l2cache_drain_writebuf) (void); 149 150 /* Other functions */ 151 152 void (*cf_drain_writebuf) (void); 153 154 void (*cf_sleep) (int mode); 155 156 /* Soft functions */ 157 158 void (*cf_context_switch) (void); 159 160 void (*cf_setup) (void); 161 }; 162 163 extern struct cpu_functions cpufuncs; 164 extern u_int cputype; 165 166 #define cpu_cpwait() cpufuncs.cf_cpwait() 167 168 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 169 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 170 171 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 172 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 173 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 174 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 175 176 #define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 177 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 178 179 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 180 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 181 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 182 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 183 184 #define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all() 185 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 186 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 187 #define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 188 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 189 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 190 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 191 #define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf() 192 193 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 194 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 195 196 #define cpu_setup() cpufuncs.cf_setup() 197 198 int set_cpufuncs (void); 199 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 200 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 201 202 void cpufunc_nullop (void); 203 u_int cpu_ident (void); 204 u_int cpufunc_control (u_int clear, u_int bic); 205 void cpu_domains (u_int domains); 206 u_int cpu_faultstatus (void); 207 u_int cpu_faultaddress (void); 208 u_int cpu_pfr (int); 209 210 #if defined(CPU_FA526) 211 void fa526_setup (void); 212 void fa526_setttb (u_int ttb); 213 void fa526_context_switch (void); 214 void fa526_cpu_sleep (int); 215 void fa526_tlb_flushID_SE (u_int); 216 217 void fa526_icache_sync_all (void); 218 void fa526_icache_sync_range(vm_offset_t start, vm_size_t end); 219 void fa526_dcache_wbinv_all (void); 220 void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end); 221 void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end); 222 void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end); 223 void fa526_idcache_wbinv_all(void); 224 void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end); 225 #endif 226 227 228 #ifdef CPU_ARM9 229 void arm9_setttb (u_int); 230 231 void arm9_tlb_flushID_SE (u_int va); 232 233 void arm9_icache_sync_all (void); 234 void arm9_icache_sync_range (vm_offset_t, vm_size_t); 235 236 void arm9_dcache_wbinv_all (void); 237 void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); 238 void arm9_dcache_inv_range (vm_offset_t, vm_size_t); 239 void arm9_dcache_wb_range (vm_offset_t, vm_size_t); 240 241 void arm9_idcache_wbinv_all (void); 242 void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); 243 244 void arm9_context_switch (void); 245 246 void arm9_setup (void); 247 248 extern unsigned arm9_dcache_sets_max; 249 extern unsigned arm9_dcache_sets_inc; 250 extern unsigned arm9_dcache_index_max; 251 extern unsigned arm9_dcache_index_inc; 252 #endif 253 254 #if defined(CPU_ARM9E) 255 void arm10_tlb_flushID_SE (u_int); 256 257 void arm10_context_switch (void); 258 259 void arm10_setup (void); 260 261 u_int sheeva_control_ext (u_int, u_int); 262 void sheeva_cpu_sleep (int); 263 void sheeva_setttb (u_int); 264 void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); 265 void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); 266 void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); 267 void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); 268 269 void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); 270 void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); 271 void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); 272 void sheeva_l2cache_wbinv_all (void); 273 #endif 274 275 #if defined(CPU_MV_PJ4B) 276 void armv6_idcache_wbinv_all (void); 277 #endif 278 #if defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) 279 void armv7_setttb (u_int); 280 void armv7_tlb_flushID (void); 281 void armv7_tlb_flushID_SE (u_int); 282 void armv7_icache_sync_all (void); 283 void armv7_icache_sync_range (vm_offset_t, vm_size_t); 284 void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); 285 void armv7_idcache_inv_all (void); 286 void armv7_dcache_wbinv_all (void); 287 void armv7_idcache_wbinv_all (void); 288 void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t); 289 void armv7_dcache_inv_range (vm_offset_t, vm_size_t); 290 void armv7_dcache_wb_range (vm_offset_t, vm_size_t); 291 void armv7_cpu_sleep (int); 292 void armv7_setup (void); 293 void armv7_context_switch (void); 294 void armv7_drain_writebuf (void); 295 void armv7_sev (void); 296 u_int armv7_auxctrl (u_int, u_int); 297 298 void armadaxp_idcache_wbinv_all (void); 299 300 void cortexa_setup (void); 301 #endif 302 #if defined(CPU_MV_PJ4B) 303 void pj4b_config (void); 304 void pj4bv7_setup (void); 305 #endif 306 307 #if defined(CPU_ARM1176) 308 void arm11_tlb_flushID (void); 309 void arm11_tlb_flushID_SE (u_int); 310 void arm11_tlb_flushD (void); 311 void arm11_tlb_flushD_SE (u_int va); 312 313 void arm11_context_switch (void); 314 315 void arm11_drain_writebuf (void); 316 317 void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t); 318 void armv6_dcache_inv_range (vm_offset_t, vm_size_t); 319 void armv6_dcache_wb_range (vm_offset_t, vm_size_t); 320 321 void armv6_idcache_inv_all (void); 322 323 void arm11x6_setttb (u_int); 324 void arm11x6_idcache_wbinv_all (void); 325 void arm11x6_dcache_wbinv_all (void); 326 void arm11x6_icache_sync_all (void); 327 void arm11x6_icache_sync_range (vm_offset_t, vm_size_t); 328 void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t); 329 void arm11x6_setup (void); 330 void arm11x6_sleep (int); /* no ref. for errata */ 331 #endif 332 333 #if defined(CPU_ARM9E) 334 void armv5_ec_setttb(u_int); 335 336 void armv5_ec_icache_sync_all(void); 337 void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); 338 339 void armv5_ec_dcache_wbinv_all(void); 340 void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); 341 void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); 342 void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); 343 344 void armv5_ec_idcache_wbinv_all(void); 345 void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); 346 #endif 347 348 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 349 defined(CPU_XSCALE_80321) || \ 350 defined(CPU_FA526) || \ 351 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 352 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 353 354 void armv4_tlb_flushID (void); 355 void armv4_tlb_flushD (void); 356 void armv4_tlb_flushD_SE (u_int va); 357 358 void armv4_drain_writebuf (void); 359 void armv4_idcache_inv_all (void); 360 #endif 361 362 #if defined(CPU_XSCALE_80321) || \ 363 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 364 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 365 void xscale_cpwait (void); 366 367 void xscale_cpu_sleep (int mode); 368 369 u_int xscale_control (u_int clear, u_int bic); 370 371 void xscale_setttb (u_int ttb); 372 373 void xscale_tlb_flushID_SE (u_int va); 374 375 void xscale_cache_flushID (void); 376 void xscale_cache_flushI (void); 377 void xscale_cache_flushD (void); 378 void xscale_cache_flushD_SE (u_int entry); 379 380 void xscale_cache_cleanID (void); 381 void xscale_cache_cleanD (void); 382 void xscale_cache_cleanD_E (u_int entry); 383 384 void xscale_cache_clean_minidata (void); 385 386 void xscale_cache_purgeID (void); 387 void xscale_cache_purgeID_E (u_int entry); 388 void xscale_cache_purgeD (void); 389 void xscale_cache_purgeD_E (u_int entry); 390 391 void xscale_cache_syncI (void); 392 void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 393 void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 394 void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 395 void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 396 void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 397 void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 398 399 void xscale_context_switch (void); 400 401 void xscale_setup (void); 402 #endif /* CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 403 CPU_XSCALE_80219 */ 404 405 #ifdef CPU_XSCALE_81342 406 407 void xscalec3_l2cache_purge (void); 408 void xscalec3_cache_purgeID (void); 409 void xscalec3_cache_purgeD (void); 410 void xscalec3_cache_cleanID (void); 411 void xscalec3_cache_cleanD (void); 412 void xscalec3_cache_syncI (void); 413 414 void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 415 void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 416 void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 417 void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 418 void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end); 419 420 void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t); 421 void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end); 422 void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end); 423 424 425 void xscalec3_setttb (u_int ttb); 426 void xscalec3_context_switch (void); 427 428 #endif /* CPU_XSCALE_81342 */ 429 430 #define setttb cpu_setttb 431 #define drain_writebuf cpu_drain_writebuf 432 433 /* 434 * Macros for manipulating CPU interrupts 435 */ 436 #if __ARM_ARCH < 6 437 #define __ARM_INTR_BITS (PSR_I | PSR_F) 438 #else 439 #define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A) 440 #endif 441 442 static __inline uint32_t 443 __set_cpsr(uint32_t bic, uint32_t eor) 444 { 445 uint32_t tmp, ret; 446 447 __asm __volatile( 448 "mrs %0, cpsr\n" /* Get the CPSR */ 449 "bic %1, %0, %2\n" /* Clear bits */ 450 "eor %1, %1, %3\n" /* XOR bits */ 451 "msr cpsr_xc, %1\n" /* Set the CPSR */ 452 : "=&r" (ret), "=&r" (tmp) 453 : "r" (bic), "r" (eor) : "memory"); 454 455 return ret; 456 } 457 458 static __inline uint32_t 459 disable_interrupts(uint32_t mask) 460 { 461 462 return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS)); 463 } 464 465 static __inline uint32_t 466 enable_interrupts(uint32_t mask) 467 { 468 469 return (__set_cpsr(mask & __ARM_INTR_BITS, 0)); 470 } 471 472 static __inline uint32_t 473 restore_interrupts(uint32_t old_cpsr) 474 { 475 476 return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS)); 477 } 478 479 static __inline register_t 480 intr_disable(void) 481 { 482 483 return (disable_interrupts(PSR_I | PSR_F)); 484 } 485 486 static __inline void 487 intr_restore(register_t s) 488 { 489 490 restore_interrupts(s); 491 } 492 #undef __ARM_INTR_BITS 493 494 /* 495 * Functions to manipulate cpu r13 496 * (in arm/arm32/setstack.S) 497 */ 498 499 void set_stackptr (u_int mode, u_int address); 500 u_int get_stackptr (u_int mode); 501 502 /* 503 * Miscellany 504 */ 505 506 int get_pc_str_offset (void); 507 508 /* 509 * CPU functions from locore.S 510 */ 511 512 void cpu_reset (void) __attribute__((__noreturn__)); 513 514 /* 515 * Cache info variables. 516 */ 517 518 /* PRIMARY CACHE VARIABLES */ 519 extern int arm_picache_size; 520 extern int arm_picache_line_size; 521 extern int arm_picache_ways; 522 523 extern int arm_pdcache_size; /* and unified */ 524 extern int arm_pdcache_line_size; 525 extern int arm_pdcache_ways; 526 527 extern int arm_pcache_type; 528 extern int arm_pcache_unified; 529 530 extern int arm_dcache_align; 531 extern int arm_dcache_align_mask; 532 533 extern u_int arm_cache_level; 534 extern u_int arm_cache_loc; 535 extern u_int arm_cache_type[14]; 536 537 #endif /* _KERNEL */ 538 #endif /* _MACHINE_CPUFUNC_H_ */ 539 540 /* End of cpufunc.h */ 541