1 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright (c) 1997 Mark Brinicombe. 7 * Copyright (c) 1997 Causality Limited 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Causality Limited. 21 * 4. The name of Causality Limited may not be used to endorse or promote 22 * products derived from this software without specific prior written 23 * permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * cpufunc.h 40 * 41 * Prototypes for cpu, mmu and tlb related functions. 42 * 43 * $FreeBSD$ 44 */ 45 46 #ifndef _MACHINE_CPUFUNC_H_ 47 #define _MACHINE_CPUFUNC_H_ 48 49 #ifdef _KERNEL 50 51 #include <sys/types.h> 52 #include <machine/armreg.h> 53 54 static __inline void 55 breakpoint(void) 56 { 57 __asm("udf 0xffff"); 58 } 59 60 struct cpu_functions { 61 /* CPU functions */ 62 void (*cf_l2cache_wbinv_all) (void); 63 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 64 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 65 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 66 void (*cf_l2cache_drain_writebuf) (void); 67 68 /* Other functions */ 69 70 void (*cf_sleep) (int mode); 71 72 void (*cf_setup) (void); 73 }; 74 75 extern struct cpu_functions cpufuncs; 76 extern u_int cputype; 77 78 #define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 79 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 80 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 81 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 82 #define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf() 83 84 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 85 86 #define cpu_setup() cpufuncs.cf_setup() 87 88 int set_cpufuncs (void); 89 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 90 91 void cpufunc_nullop (void); 92 u_int cpufunc_control (u_int clear, u_int bic); 93 94 95 #if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) 96 void armv7_cpu_sleep (int); 97 #endif 98 #if defined(CPU_MV_PJ4B) 99 void pj4b_config (void); 100 #endif 101 102 #if defined(CPU_ARM1176) 103 void arm11x6_sleep (int); /* no ref. for errata */ 104 #endif 105 106 107 /* 108 * Macros for manipulating CPU interrupts 109 */ 110 #define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A) 111 112 static __inline uint32_t 113 __set_cpsr(uint32_t bic, uint32_t eor) 114 { 115 uint32_t tmp, ret; 116 117 __asm __volatile( 118 "mrs %0, cpsr\n" /* Get the CPSR */ 119 "bic %1, %0, %2\n" /* Clear bits */ 120 "eor %1, %1, %3\n" /* XOR bits */ 121 "msr cpsr_xc, %1\n" /* Set the CPSR */ 122 : "=&r" (ret), "=&r" (tmp) 123 : "r" (bic), "r" (eor) : "memory"); 124 125 return ret; 126 } 127 128 static __inline uint32_t 129 disable_interrupts(uint32_t mask) 130 { 131 132 return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS)); 133 } 134 135 static __inline uint32_t 136 enable_interrupts(uint32_t mask) 137 { 138 139 return (__set_cpsr(mask & __ARM_INTR_BITS, 0)); 140 } 141 142 static __inline uint32_t 143 restore_interrupts(uint32_t old_cpsr) 144 { 145 146 return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS)); 147 } 148 149 static __inline register_t 150 intr_disable(void) 151 { 152 153 return (disable_interrupts(PSR_I | PSR_F)); 154 } 155 156 static __inline void 157 intr_restore(register_t s) 158 { 159 160 restore_interrupts(s); 161 } 162 #undef __ARM_INTR_BITS 163 164 /* 165 * Functions to manipulate cpu r13 166 * (in arm/arm32/setstack.S) 167 */ 168 169 void set_stackptr (u_int mode, u_int address); 170 u_int get_stackptr (u_int mode); 171 172 /* 173 * CPU functions from locore.S 174 */ 175 176 void cpu_reset (void) __attribute__((__noreturn__)); 177 178 /* 179 * Cache info variables. 180 */ 181 182 /* PRIMARY CACHE VARIABLES */ 183 extern int arm_dcache_align; 184 extern int arm_dcache_align_mask; 185 186 187 #define HAVE_INLINE_FFS 188 189 static __inline __pure2 int 190 ffs(int mask) 191 { 192 193 return (__builtin_ffs(mask)); 194 } 195 196 #define HAVE_INLINE_FFSL 197 198 static __inline __pure2 int 199 ffsl(long mask) 200 { 201 202 return (__builtin_ffsl(mask)); 203 } 204 205 #define HAVE_INLINE_FFSLL 206 207 static __inline __pure2 int 208 ffsll(long long mask) 209 { 210 211 return (__builtin_ffsll(mask)); 212 } 213 214 #define HAVE_INLINE_FLS 215 216 static __inline __pure2 int 217 fls(int mask) 218 { 219 220 return (mask == 0 ? 0 : 221 8 * sizeof(mask) - __builtin_clz((u_int)mask)); 222 } 223 224 #define HAVE_INLINE_FLSL 225 226 static __inline __pure2 int 227 flsl(long mask) 228 { 229 230 return (mask == 0 ? 0 : 231 8 * sizeof(mask) - __builtin_clzl((u_long)mask)); 232 } 233 234 #define HAVE_INLINE_FLSLL 235 236 static __inline __pure2 int 237 flsll(long long mask) 238 { 239 240 return (mask == 0 ? 0 : 241 8 * sizeof(mask) - __builtin_clzll((unsigned long long)mask)); 242 } 243 #else /* !_KERNEL */ 244 245 static __inline void 246 breakpoint(void) 247 { 248 249 /* 250 * This matches the instruction used by GDB for software 251 * breakpoints. 252 */ 253 __asm("udf 0xfdee"); 254 } 255 256 #endif /* _KERNEL */ 257 #endif /* _MACHINE_CPUFUNC_H_ */ 258 259 /* End of cpufunc.h */ 260