1 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * 41 * $FreeBSD$ 42 */ 43 44 #ifndef _MACHINE_CPUFUNC_H_ 45 #define _MACHINE_CPUFUNC_H_ 46 47 #ifdef _KERNEL 48 49 #include <sys/types.h> 50 #include <machine/cpuconf.h> 51 #include <machine/katelib.h> /* For in[bwl] and out[bwl] */ 52 53 void disable_intr(void); 54 void enable_intr(void); 55 56 static __inline void 57 breakpoint(void) 58 { 59 } 60 static __inline register_t 61 intr_disable(void) 62 { 63 int s = 0, tmp; 64 65 __asm __volatile("mrs %0, cpsr; \ 66 orr %1, %0, %2;\ 67 msr cpsr_all, %1;" 68 : "=r" (s), "=r" (tmp) 69 : "I" (I32_bit) 70 : "cc"); 71 return (s); 72 } 73 74 static __inline void 75 intr_restore(int s) 76 { 77 __asm __volatile("msr cpsr_all, %0 " 78 : /* no output */ 79 : "r" (s) 80 : "cc"); 81 } 82 struct cpu_functions { 83 84 /* CPU functions */ 85 86 u_int (*cf_id) (void); 87 void (*cf_cpwait) (void); 88 89 /* MMU functions */ 90 91 u_int (*cf_control) (u_int bic, u_int eor); 92 void (*cf_domains) (u_int domains); 93 void (*cf_setttb) (u_int ttb); 94 u_int (*cf_faultstatus) (void); 95 u_int (*cf_faultaddress) (void); 96 97 /* TLB functions */ 98 99 void (*cf_tlb_flushID) (void); 100 void (*cf_tlb_flushID_SE) (u_int va); 101 void (*cf_tlb_flushI) (void); 102 void (*cf_tlb_flushI_SE) (u_int va); 103 void (*cf_tlb_flushD) (void); 104 void (*cf_tlb_flushD_SE) (u_int va); 105 106 /* 107 * Cache operations: 108 * 109 * We define the following primitives: 110 * 111 * icache_sync_all Synchronize I-cache 112 * icache_sync_range Synchronize I-cache range 113 * 114 * dcache_wbinv_all Write-back and Invalidate D-cache 115 * dcache_wbinv_range Write-back and Invalidate D-cache range 116 * dcache_inv_range Invalidate D-cache range 117 * dcache_wb_range Write-back D-cache range 118 * 119 * idcache_wbinv_all Write-back and Invalidate D-cache, 120 * Invalidate I-cache 121 * idcache_wbinv_range Write-back and Invalidate D-cache, 122 * Invalidate I-cache range 123 * 124 * Note that the ARM term for "write-back" is "clean". We use 125 * the term "write-back" since it's a more common way to describe 126 * the operation. 127 * 128 * There are some rules that must be followed: 129 * 130 * I-cache Synch (all or range): 131 * The goal is to synchronize the instruction stream, 132 * so you may beed to write-back dirty D-cache blocks 133 * first. If a range is requested, and you can't 134 * synchronize just a range, you have to hit the whole 135 * thing. 136 * 137 * D-cache Write-Back and Invalidate range: 138 * If you can't WB-Inv a range, you must WB-Inv the 139 * entire D-cache. 140 * 141 * D-cache Invalidate: 142 * If you can't Inv the D-cache, you must Write-Back 143 * and Invalidate. Code that uses this operation 144 * MUST NOT assume that the D-cache will not be written 145 * back to memory. 146 * 147 * D-cache Write-Back: 148 * If you can't Write-back without doing an Inv, 149 * that's fine. Then treat this as a WB-Inv. 150 * Skipping the invalidate is merely an optimization. 151 * 152 * All operations: 153 * Valid virtual addresses must be passed to each 154 * cache operation. 155 */ 156 void (*cf_icache_sync_all) (void); 157 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 158 159 void (*cf_dcache_wbinv_all) (void); 160 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 161 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 162 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 163 164 void (*cf_idcache_wbinv_all) (void); 165 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 166 167 /* Other functions */ 168 169 void (*cf_flush_prefetchbuf) (void); 170 void (*cf_drain_writebuf) (void); 171 void (*cf_flush_brnchtgt_C) (void); 172 void (*cf_flush_brnchtgt_E) (u_int va); 173 174 void (*cf_sleep) (int mode); 175 176 /* Soft functions */ 177 178 int (*cf_dataabt_fixup) (void *arg); 179 int (*cf_prefetchabt_fixup) (void *arg); 180 181 void (*cf_context_switch) (void); 182 183 void (*cf_setup) (char *string); 184 }; 185 186 extern struct cpu_functions cpufuncs; 187 extern u_int cputype; 188 189 #define cpu_id() cpufuncs.cf_id() 190 #define cpu_cpwait() cpufuncs.cf_cpwait() 191 192 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 193 #define cpu_domains(d) cpufuncs.cf_domains(d) 194 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 195 #define cpu_faultstatus() cpufuncs.cf_faultstatus() 196 #define cpu_faultaddress() cpufuncs.cf_faultaddress() 197 198 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 199 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 200 #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 201 #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 202 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 203 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 204 205 #define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 206 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 207 208 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 209 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 210 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 211 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 212 213 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 214 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 215 216 #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 217 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 218 #define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 219 #define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 220 221 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 222 223 #define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 224 #define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 225 #define ABORT_FIXUP_OK 0 /* fixup succeeded */ 226 #define ABORT_FIXUP_FAILED 1 /* fixup failed */ 227 #define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 228 229 #define cpu_setup(a) cpufuncs.cf_setup(a) 230 231 int set_cpufuncs (void); 232 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 233 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 234 235 void cpufunc_nullop (void); 236 int cpufunc_null_fixup (void *); 237 int early_abort_fixup (void *); 238 int late_abort_fixup (void *); 239 u_int cpufunc_id (void); 240 u_int cpufunc_control (u_int clear, u_int bic); 241 void cpufunc_domains (u_int domains); 242 u_int cpufunc_faultstatus (void); 243 u_int cpufunc_faultaddress (void); 244 245 #ifdef CPU_ARM3 246 u_int arm3_control (u_int clear, u_int bic); 247 void arm3_cache_flush (void); 248 #endif /* CPU_ARM3 */ 249 250 #if defined(CPU_ARM6) || defined(CPU_ARM7) 251 void arm67_setttb (u_int ttb); 252 void arm67_tlb_flush (void); 253 void arm67_tlb_purge (u_int va); 254 void arm67_cache_flush (void); 255 void arm67_context_switch (void); 256 #endif /* CPU_ARM6 || CPU_ARM7 */ 257 258 #ifdef CPU_ARM6 259 void arm6_setup (char *string); 260 #endif /* CPU_ARM6 */ 261 262 #ifdef CPU_ARM7 263 void arm7_setup (char *string); 264 #endif /* CPU_ARM7 */ 265 266 #ifdef CPU_ARM7TDMI 267 int arm7_dataabt_fixup (void *arg); 268 void arm7tdmi_setup (char *string); 269 void arm7tdmi_setttb (u_int ttb); 270 void arm7tdmi_tlb_flushID (void); 271 void arm7tdmi_tlb_flushID_SE (u_int va); 272 void arm7tdmi_cache_flushID (void); 273 void arm7tdmi_context_switch (void); 274 #endif /* CPU_ARM7TDMI */ 275 276 #ifdef CPU_ARM8 277 void arm8_setttb (u_int ttb); 278 void arm8_tlb_flushID (void); 279 void arm8_tlb_flushID_SE (u_int va); 280 void arm8_cache_flushID (void); 281 void arm8_cache_flushID_E (u_int entry); 282 void arm8_cache_cleanID (void); 283 void arm8_cache_cleanID_E (u_int entry); 284 void arm8_cache_purgeID (void); 285 void arm8_cache_purgeID_E (u_int entry); 286 287 void arm8_cache_syncI (void); 288 void arm8_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 289 void arm8_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 290 void arm8_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 291 void arm8_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 292 void arm8_cache_syncI_rng (vm_offset_t start, vm_size_t end); 293 294 void arm8_context_switch (void); 295 296 void arm8_setup (char *string); 297 298 u_int arm8_clock_config (u_int, u_int); 299 #endif 300 301 #ifdef CPU_SA110 302 void sa110_setup (char *string); 303 void sa110_context_switch (void); 304 #endif /* CPU_SA110 */ 305 306 #if defined(CPU_SA1100) || defined(CPU_SA1110) 307 void sa11x0_drain_readbuf (void); 308 309 void sa11x0_context_switch (void); 310 void sa11x0_cpu_sleep (int mode); 311 312 void sa11x0_setup (char *string); 313 #endif 314 315 #if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) 316 void sa1_setttb (u_int ttb); 317 318 void sa1_tlb_flushID_SE (u_int va); 319 320 void sa1_cache_flushID (void); 321 void sa1_cache_flushI (void); 322 void sa1_cache_flushD (void); 323 void sa1_cache_flushD_SE (u_int entry); 324 325 void sa1_cache_cleanID (void); 326 void sa1_cache_cleanD (void); 327 void sa1_cache_cleanD_E (u_int entry); 328 329 void sa1_cache_purgeID (void); 330 void sa1_cache_purgeID_E (u_int entry); 331 void sa1_cache_purgeD (void); 332 void sa1_cache_purgeD_E (u_int entry); 333 334 void sa1_cache_syncI (void); 335 void sa1_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 336 void sa1_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 337 void sa1_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 338 void sa1_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 339 void sa1_cache_syncI_rng (vm_offset_t start, vm_size_t end); 340 341 #endif 342 343 #ifdef CPU_ARM9 344 void arm9_setttb (u_int); 345 346 void arm9_tlb_flushID_SE (u_int va); 347 348 void arm9_cache_flushID (void); 349 void arm9_cache_flushID_SE (u_int); 350 void arm9_cache_flushI (void); 351 void arm9_cache_flushI_SE (u_int); 352 void arm9_cache_flushD (void); 353 void arm9_cache_flushD_SE (u_int); 354 355 void arm9_cache_cleanID (void); 356 357 void arm9_cache_syncI (void); 358 void arm9_cache_flushID_rng (vm_offset_t, vm_size_t); 359 void arm9_cache_flushD_rng (vm_offset_t, vm_size_t); 360 void arm9_cache_syncI_rng (vm_offset_t, vm_size_t); 361 362 void arm9_context_switch (void); 363 364 void arm9_setup (char *string); 365 #endif 366 367 #ifdef CPU_ARM10 368 void arm10_setttb (u_int); 369 370 void arm10_tlb_flushID_SE (u_int); 371 void arm10_tlb_flushI_SE (u_int); 372 373 void arm10_icache_sync_all (void); 374 void arm10_icache_sync_range (vm_offset_t, vm_size_t); 375 376 void arm10_dcache_wbinv_all (void); 377 void arm10_dcache_wbinv_range (vm_offset_t, vm_size_t); 378 void arm10_dcache_inv_range (vm_offset_t, vm_size_t); 379 void arm10_dcache_wb_range (vm_offset_t, vm_size_t); 380 381 void arm10_idcache_wbinv_all (void); 382 void arm10_idcache_wbinv_range (vm_offset_t, vm_size_t); 383 384 void arm10_context_switch (void); 385 386 void arm10_setup (char *string); 387 388 extern unsigned arm10_dcache_sets_max; 389 extern unsigned arm10_dcache_sets_inc; 390 extern unsigned arm10_dcache_index_max; 391 extern unsigned arm10_dcache_index_inc; 392 #endif 393 394 #if defined(CPU_ARM9) || defined(CPU_ARM10) || defined(CPU_SA110) || \ 395 defined(CPU_SA1100) || defined(CPU_SA1110) || \ 396 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 397 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) 398 399 void armv4_tlb_flushID (void); 400 void armv4_tlb_flushI (void); 401 void armv4_tlb_flushD (void); 402 void armv4_tlb_flushD_SE (u_int va); 403 404 void armv4_drain_writebuf (void); 405 #endif 406 407 #if defined(CPU_IXP12X0) 408 void ixp12x0_drain_readbuf (void); 409 void ixp12x0_context_switch (void); 410 void ixp12x0_setup (char *string); 411 #endif 412 413 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 414 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) 415 void xscale_cpwait (void); 416 417 void xscale_cpu_sleep (int mode); 418 419 u_int xscale_control (u_int clear, u_int bic); 420 421 void xscale_setttb (u_int ttb); 422 423 void xscale_tlb_flushID_SE (u_int va); 424 425 void xscale_cache_flushID (void); 426 void xscale_cache_flushI (void); 427 void xscale_cache_flushD (void); 428 void xscale_cache_flushD_SE (u_int entry); 429 430 void xscale_cache_cleanID (void); 431 void xscale_cache_cleanD (void); 432 void xscale_cache_cleanD_E (u_int entry); 433 434 void xscale_cache_clean_minidata (void); 435 436 void xscale_cache_purgeID (void); 437 void xscale_cache_purgeID_E (u_int entry); 438 void xscale_cache_purgeD (void); 439 void xscale_cache_purgeD_E (u_int entry); 440 441 void xscale_cache_syncI (void); 442 void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 443 void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 444 void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 445 void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 446 void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 447 void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 448 449 void xscale_context_switch (void); 450 451 void xscale_setup (char *string); 452 #endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ 453 454 #define tlb_flush cpu_tlb_flushID 455 #define setttb cpu_setttb 456 #define drain_writebuf cpu_drain_writebuf 457 458 /* 459 * Macros for manipulating CPU interrupts 460 */ 461 static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__)); 462 463 static __inline u_int32_t 464 __set_cpsr_c(u_int bic, u_int eor) 465 { 466 u_int32_t tmp, ret; 467 468 __asm __volatile( 469 "mrs %0, cpsr\n" /* Get the CPSR */ 470 "bic %1, %0, %2\n" /* Clear bits */ 471 "eor %1, %1, %3\n" /* XOR bits */ 472 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 473 : "=&r" (ret), "=&r" (tmp) 474 : "r" (bic), "r" (eor)); 475 476 return ret; 477 } 478 479 #define disable_interrupts(mask) \ 480 (__set_cpsr_c((mask) & (I32_bit | F32_bit), \ 481 (mask) & (I32_bit | F32_bit))) 482 483 #define enable_interrupts(mask) \ 484 (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0)) 485 486 #define restore_interrupts(old_cpsr) \ 487 (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 488 489 /* Functions to manipulate the CPSR. */ 490 u_int SetCPSR(u_int bic, u_int eor); 491 u_int GetCPSR(void); 492 493 /* 494 * Functions to manipulate cpu r13 495 * (in arm/arm32/setstack.S) 496 */ 497 498 void set_stackptr __P((u_int mode, u_int address)); 499 u_int get_stackptr __P((u_int mode)); 500 501 /* 502 * Miscellany 503 */ 504 505 int get_pc_str_offset __P((void)); 506 507 /* 508 * CPU functions from locore.S 509 */ 510 511 void cpu_reset __P((void)) __attribute__((__noreturn__)); 512 513 /* 514 * Cache info variables. 515 */ 516 517 /* PRIMARY CACHE VARIABLES */ 518 extern int arm_picache_size; 519 extern int arm_picache_line_size; 520 extern int arm_picache_ways; 521 522 extern int arm_pdcache_size; /* and unified */ 523 extern int arm_pdcache_line_size; 524 extern int arm_pdcache_ways; 525 526 extern int arm_pcache_type; 527 extern int arm_pcache_unified; 528 529 extern int arm_dcache_align; 530 extern int arm_dcache_align_mask; 531 532 #endif /* _KERNEL */ 533 #endif /* _MACHINE_CPUFUNC_H_ */ 534 535 /* End of cpufunc.h */ 536