1 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3 /* 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * 41 * $FreeBSD$ 42 */ 43 44 #ifndef _MACHINE_CPUFUNC_H_ 45 #define _MACHINE_CPUFUNC_H_ 46 47 #ifdef _KERNEL 48 49 #include <sys/types.h> 50 #include <machine/cpuconf.h> 51 #include <machine/katelib.h> /* For in[bwl] and out[bwl] */ 52 53 static __inline void 54 breakpoint(void) 55 { 56 } 57 58 static __inline register_t 59 intr_disable(void) 60 { 61 int s = 0, tmp; 62 63 __asm __volatile("mrs %0, cpsr; \ 64 orr %1, %0, %2;\ 65 msr cpsr_all, %1;" 66 : "=r" (s), "=r" (tmp) 67 : "I" (I32_bit) 68 : "cc"); 69 return (s); 70 } 71 72 static __inline void 73 intr_restore(int s) 74 { 75 __asm __volatile("msr cpsr_all, %0 " 76 : /* no output */ 77 : "r" (s) 78 : "cc"); 79 } 80 struct cpu_functions { 81 82 /* CPU functions */ 83 84 u_int (*cf_id) (void); 85 void (*cf_cpwait) (void); 86 87 /* MMU functions */ 88 89 u_int (*cf_control) (u_int bic, u_int eor); 90 void (*cf_domains) (u_int domains); 91 void (*cf_setttb) (u_int ttb); 92 u_int (*cf_faultstatus) (void); 93 u_int (*cf_faultaddress) (void); 94 95 /* TLB functions */ 96 97 void (*cf_tlb_flushID) (void); 98 void (*cf_tlb_flushID_SE) (u_int va); 99 void (*cf_tlb_flushI) (void); 100 void (*cf_tlb_flushI_SE) (u_int va); 101 void (*cf_tlb_flushD) (void); 102 void (*cf_tlb_flushD_SE) (u_int va); 103 104 /* 105 * Cache operations: 106 * 107 * We define the following primitives: 108 * 109 * icache_sync_all Synchronize I-cache 110 * icache_sync_range Synchronize I-cache range 111 * 112 * dcache_wbinv_all Write-back and Invalidate D-cache 113 * dcache_wbinv_range Write-back and Invalidate D-cache range 114 * dcache_inv_range Invalidate D-cache range 115 * dcache_wb_range Write-back D-cache range 116 * 117 * idcache_wbinv_all Write-back and Invalidate D-cache, 118 * Invalidate I-cache 119 * idcache_wbinv_range Write-back and Invalidate D-cache, 120 * Invalidate I-cache range 121 * 122 * Note that the ARM term for "write-back" is "clean". We use 123 * the term "write-back" since it's a more common way to describe 124 * the operation. 125 * 126 * There are some rules that must be followed: 127 * 128 * I-cache Synch (all or range): 129 * The goal is to synchronize the instruction stream, 130 * so you may beed to write-back dirty D-cache blocks 131 * first. If a range is requested, and you can't 132 * synchronize just a range, you have to hit the whole 133 * thing. 134 * 135 * D-cache Write-Back and Invalidate range: 136 * If you can't WB-Inv a range, you must WB-Inv the 137 * entire D-cache. 138 * 139 * D-cache Invalidate: 140 * If you can't Inv the D-cache, you must Write-Back 141 * and Invalidate. Code that uses this operation 142 * MUST NOT assume that the D-cache will not be written 143 * back to memory. 144 * 145 * D-cache Write-Back: 146 * If you can't Write-back without doing an Inv, 147 * that's fine. Then treat this as a WB-Inv. 148 * Skipping the invalidate is merely an optimization. 149 * 150 * All operations: 151 * Valid virtual addresses must be passed to each 152 * cache operation. 153 */ 154 void (*cf_icache_sync_all) (void); 155 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 156 157 void (*cf_dcache_wbinv_all) (void); 158 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 159 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 160 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 161 162 void (*cf_idcache_wbinv_all) (void); 163 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 164 165 /* Other functions */ 166 167 void (*cf_flush_prefetchbuf) (void); 168 void (*cf_drain_writebuf) (void); 169 void (*cf_flush_brnchtgt_C) (void); 170 void (*cf_flush_brnchtgt_E) (u_int va); 171 172 void (*cf_sleep) (int mode); 173 174 /* Soft functions */ 175 176 int (*cf_dataabt_fixup) (void *arg); 177 int (*cf_prefetchabt_fixup) (void *arg); 178 179 void (*cf_context_switch) (void); 180 181 void (*cf_setup) (char *string); 182 }; 183 184 extern struct cpu_functions cpufuncs; 185 extern u_int cputype; 186 187 #define cpu_id() cpufuncs.cf_id() 188 #define cpu_cpwait() cpufuncs.cf_cpwait() 189 190 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 191 #define cpu_domains(d) cpufuncs.cf_domains(d) 192 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 193 #define cpu_faultstatus() cpufuncs.cf_faultstatus() 194 #define cpu_faultaddress() cpufuncs.cf_faultaddress() 195 196 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 197 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 198 #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 199 #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 200 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 201 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 202 203 #define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 204 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 205 206 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 207 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 208 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 209 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 210 211 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 212 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 213 214 #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 215 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 216 #define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 217 #define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 218 219 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 220 221 #define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 222 #define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 223 #define ABORT_FIXUP_OK 0 /* fixup succeeded */ 224 #define ABORT_FIXUP_FAILED 1 /* fixup failed */ 225 #define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 226 227 #define cpu_setup(a) cpufuncs.cf_setup(a) 228 229 int set_cpufuncs (void); 230 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 231 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 232 233 void cpufunc_nullop (void); 234 int cpufunc_null_fixup (void *); 235 int early_abort_fixup (void *); 236 int late_abort_fixup (void *); 237 u_int cpufunc_id (void); 238 u_int cpufunc_control (u_int clear, u_int bic); 239 void cpufunc_domains (u_int domains); 240 u_int cpufunc_faultstatus (void); 241 u_int cpufunc_faultaddress (void); 242 243 #ifdef CPU_ARM3 244 u_int arm3_control (u_int clear, u_int bic); 245 void arm3_cache_flush (void); 246 #endif /* CPU_ARM3 */ 247 248 #if defined(CPU_ARM6) || defined(CPU_ARM7) 249 void arm67_setttb (u_int ttb); 250 void arm67_tlb_flush (void); 251 void arm67_tlb_purge (u_int va); 252 void arm67_cache_flush (void); 253 void arm67_context_switch (void); 254 #endif /* CPU_ARM6 || CPU_ARM7 */ 255 256 #ifdef CPU_ARM6 257 void arm6_setup (char *string); 258 #endif /* CPU_ARM6 */ 259 260 #ifdef CPU_ARM7 261 void arm7_setup (char *string); 262 #endif /* CPU_ARM7 */ 263 264 #ifdef CPU_ARM7TDMI 265 int arm7_dataabt_fixup (void *arg); 266 void arm7tdmi_setup (char *string); 267 void arm7tdmi_setttb (u_int ttb); 268 void arm7tdmi_tlb_flushID (void); 269 void arm7tdmi_tlb_flushID_SE (u_int va); 270 void arm7tdmi_cache_flushID (void); 271 void arm7tdmi_context_switch (void); 272 #endif /* CPU_ARM7TDMI */ 273 274 #ifdef CPU_ARM8 275 void arm8_setttb (u_int ttb); 276 void arm8_tlb_flushID (void); 277 void arm8_tlb_flushID_SE (u_int va); 278 void arm8_cache_flushID (void); 279 void arm8_cache_flushID_E (u_int entry); 280 void arm8_cache_cleanID (void); 281 void arm8_cache_cleanID_E (u_int entry); 282 void arm8_cache_purgeID (void); 283 void arm8_cache_purgeID_E (u_int entry); 284 285 void arm8_cache_syncI (void); 286 void arm8_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 287 void arm8_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 288 void arm8_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 289 void arm8_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 290 void arm8_cache_syncI_rng (vm_offset_t start, vm_size_t end); 291 292 void arm8_context_switch (void); 293 294 void arm8_setup (char *string); 295 296 u_int arm8_clock_config (u_int, u_int); 297 #endif 298 299 #ifdef CPU_SA110 300 void sa110_setup (char *string); 301 void sa110_context_switch (void); 302 #endif /* CPU_SA110 */ 303 304 #if defined(CPU_SA1100) || defined(CPU_SA1110) 305 void sa11x0_drain_readbuf (void); 306 307 void sa11x0_context_switch (void); 308 void sa11x0_cpu_sleep (int mode); 309 310 void sa11x0_setup (char *string); 311 #endif 312 313 #if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) 314 void sa1_setttb (u_int ttb); 315 316 void sa1_tlb_flushID_SE (u_int va); 317 318 void sa1_cache_flushID (void); 319 void sa1_cache_flushI (void); 320 void sa1_cache_flushD (void); 321 void sa1_cache_flushD_SE (u_int entry); 322 323 void sa1_cache_cleanID (void); 324 void sa1_cache_cleanD (void); 325 void sa1_cache_cleanD_E (u_int entry); 326 327 void sa1_cache_purgeID (void); 328 void sa1_cache_purgeID_E (u_int entry); 329 void sa1_cache_purgeD (void); 330 void sa1_cache_purgeD_E (u_int entry); 331 332 void sa1_cache_syncI (void); 333 void sa1_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 334 void sa1_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 335 void sa1_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 336 void sa1_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 337 void sa1_cache_syncI_rng (vm_offset_t start, vm_size_t end); 338 339 #endif 340 341 #ifdef CPU_ARM9 342 void arm9_setttb (u_int); 343 344 void arm9_tlb_flushID_SE (u_int va); 345 346 void arm9_cache_flushID (void); 347 void arm9_cache_flushID_SE (u_int); 348 void arm9_cache_flushI (void); 349 void arm9_cache_flushI_SE (u_int); 350 void arm9_cache_flushD (void); 351 void arm9_cache_flushD_SE (u_int); 352 353 void arm9_cache_cleanID (void); 354 355 void arm9_cache_syncI (void); 356 void arm9_cache_flushID_rng (vm_offset_t, vm_size_t); 357 void arm9_cache_flushD_rng (vm_offset_t, vm_size_t); 358 void arm9_cache_syncI_rng (vm_offset_t, vm_size_t); 359 360 void arm9_context_switch (void); 361 362 void arm9_setup (char *string); 363 #endif 364 365 #ifdef CPU_ARM10 366 void arm10_setttb (u_int); 367 368 void arm10_tlb_flushID_SE (u_int); 369 void arm10_tlb_flushI_SE (u_int); 370 371 void arm10_icache_sync_all (void); 372 void arm10_icache_sync_range (vm_offset_t, vm_size_t); 373 374 void arm10_dcache_wbinv_all (void); 375 void arm10_dcache_wbinv_range (vm_offset_t, vm_size_t); 376 void arm10_dcache_inv_range (vm_offset_t, vm_size_t); 377 void arm10_dcache_wb_range (vm_offset_t, vm_size_t); 378 379 void arm10_idcache_wbinv_all (void); 380 void arm10_idcache_wbinv_range (vm_offset_t, vm_size_t); 381 382 void arm10_context_switch (void); 383 384 void arm10_setup (char *string); 385 386 extern unsigned arm10_dcache_sets_max; 387 extern unsigned arm10_dcache_sets_inc; 388 extern unsigned arm10_dcache_index_max; 389 extern unsigned arm10_dcache_index_inc; 390 #endif 391 392 #if defined(CPU_ARM9) || defined(CPU_ARM10) || defined(CPU_SA110) || \ 393 defined(CPU_SA1100) || defined(CPU_SA1110) || \ 394 defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 395 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) 396 397 void armv4_tlb_flushID (void); 398 void armv4_tlb_flushI (void); 399 void armv4_tlb_flushD (void); 400 void armv4_tlb_flushD_SE (u_int va); 401 402 void armv4_drain_writebuf (void); 403 #endif 404 405 #if defined(CPU_IXP12X0) 406 void ixp12x0_drain_readbuf (void); 407 void ixp12x0_context_switch (void); 408 void ixp12x0_setup (char *string); 409 #endif 410 411 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 412 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) 413 void xscale_cpwait (void); 414 415 void xscale_cpu_sleep (int mode); 416 417 u_int xscale_control (u_int clear, u_int bic); 418 419 void xscale_setttb (u_int ttb); 420 421 void xscale_tlb_flushID_SE (u_int va); 422 423 void xscale_cache_flushID (void); 424 void xscale_cache_flushI (void); 425 void xscale_cache_flushD (void); 426 void xscale_cache_flushD_SE (u_int entry); 427 428 void xscale_cache_cleanID (void); 429 void xscale_cache_cleanD (void); 430 void xscale_cache_cleanD_E (u_int entry); 431 432 void xscale_cache_clean_minidata (void); 433 434 void xscale_cache_purgeID (void); 435 void xscale_cache_purgeID_E (u_int entry); 436 void xscale_cache_purgeD (void); 437 void xscale_cache_purgeD_E (u_int entry); 438 439 void xscale_cache_syncI (void); 440 void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 441 void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 442 void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 443 void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 444 void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 445 void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 446 447 void xscale_context_switch (void); 448 449 void xscale_setup (char *string); 450 #endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ 451 452 #define tlb_flush cpu_tlb_flushID 453 #define setttb cpu_setttb 454 #define drain_writebuf cpu_drain_writebuf 455 456 /* 457 * Macros for manipulating CPU interrupts 458 */ 459 static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__)); 460 461 static __inline u_int32_t 462 __set_cpsr_c(u_int bic, u_int eor) 463 { 464 u_int32_t tmp, ret; 465 466 __asm __volatile( 467 "mrs %0, cpsr\n" /* Get the CPSR */ 468 "bic %1, %0, %2\n" /* Clear bits */ 469 "eor %1, %1, %3\n" /* XOR bits */ 470 "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 471 : "=&r" (ret), "=&r" (tmp) 472 : "r" (bic), "r" (eor)); 473 474 return ret; 475 } 476 477 #define disable_interrupts(mask) \ 478 (__set_cpsr_c((mask) & (I32_bit | F32_bit), \ 479 (mask) & (I32_bit | F32_bit))) 480 481 #define enable_interrupts(mask) \ 482 (__set_cpsr_c((mask) & (I32_bit | F32_bit), 0)) 483 484 #define restore_interrupts(old_cpsr) \ 485 (__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit))) 486 487 /* Functions to manipulate the CPSR. */ 488 u_int SetCPSR(u_int bic, u_int eor); 489 u_int GetCPSR(void); 490 491 /* 492 * Functions to manipulate cpu r13 493 * (in arm/arm32/setstack.S) 494 */ 495 496 void set_stackptr __P((u_int mode, u_int address)); 497 u_int get_stackptr __P((u_int mode)); 498 499 /* 500 * Miscellany 501 */ 502 503 int get_pc_str_offset __P((void)); 504 505 /* 506 * CPU functions from locore.S 507 */ 508 509 void cpu_reset __P((void)) __attribute__((__noreturn__)); 510 511 /* 512 * Cache info variables. 513 */ 514 515 /* PRIMARY CACHE VARIABLES */ 516 extern int arm_picache_size; 517 extern int arm_picache_line_size; 518 extern int arm_picache_ways; 519 520 extern int arm_pdcache_size; /* and unified */ 521 extern int arm_pdcache_line_size; 522 extern int arm_pdcache_ways; 523 524 extern int arm_pcache_type; 525 extern int arm_pcache_unified; 526 527 extern int arm_dcache_align; 528 extern int arm_dcache_align_mask; 529 530 #endif /* _KERNEL */ 531 #endif /* _MACHINE_CPUFUNC_H_ */ 532 533 /* End of cpufunc.h */ 534