1 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright (c) 1997 Mark Brinicombe. 7 * Copyright (c) 1997 Causality Limited 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Causality Limited. 21 * 4. The name of Causality Limited may not be used to endorse or promote 22 * products derived from this software without specific prior written 23 * permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * cpufunc.h 40 * 41 * Prototypes for cpu, mmu and tlb related functions. 42 * 43 * $FreeBSD$ 44 */ 45 46 #ifndef _MACHINE_CPUFUNC_H_ 47 #define _MACHINE_CPUFUNC_H_ 48 49 #ifdef _KERNEL 50 51 #include <sys/types.h> 52 #include <machine/armreg.h> 53 54 static __inline void 55 breakpoint(void) 56 { 57 __asm("udf 0xffff"); 58 } 59 60 struct cpu_functions { 61 /* CPU functions */ 62 #if __ARM_ARCH < 6 63 void (*cf_cpwait) (void); 64 65 /* MMU functions */ 66 67 u_int (*cf_control) (u_int bic, u_int eor); 68 void (*cf_setttb) (u_int ttb); 69 70 /* TLB functions */ 71 72 void (*cf_tlb_flushID) (void); 73 void (*cf_tlb_flushID_SE) (u_int va); 74 void (*cf_tlb_flushD) (void); 75 void (*cf_tlb_flushD_SE) (u_int va); 76 77 /* 78 * Cache operations: 79 * 80 * We define the following primitives: 81 * 82 * icache_sync_range Synchronize I-cache range 83 * 84 * dcache_wbinv_all Write-back and Invalidate D-cache 85 * dcache_wbinv_range Write-back and Invalidate D-cache range 86 * dcache_inv_range Invalidate D-cache range 87 * dcache_wb_range Write-back D-cache range 88 * 89 * idcache_wbinv_all Write-back and Invalidate D-cache, 90 * Invalidate I-cache 91 * idcache_wbinv_range Write-back and Invalidate D-cache, 92 * Invalidate I-cache range 93 * 94 * Note that the ARM term for "write-back" is "clean". We use 95 * the term "write-back" since it's a more common way to describe 96 * the operation. 97 * 98 * There are some rules that must be followed: 99 * 100 * ID-cache Invalidate All: 101 * Unlike other functions, this one must never write back. 102 * It is used to intialize the MMU when it is in an unknown 103 * state (such as when it may have lines tagged as valid 104 * that belong to a previous set of mappings). 105 * 106 * I-cache Sync range: 107 * The goal is to synchronize the instruction stream, 108 * so you may beed to write-back dirty D-cache blocks 109 * first. If a range is requested, and you can't 110 * synchronize just a range, you have to hit the whole 111 * thing. 112 * 113 * D-cache Write-Back and Invalidate range: 114 * If you can't WB-Inv a range, you must WB-Inv the 115 * entire D-cache. 116 * 117 * D-cache Invalidate: 118 * If you can't Inv the D-cache, you must Write-Back 119 * and Invalidate. Code that uses this operation 120 * MUST NOT assume that the D-cache will not be written 121 * back to memory. 122 * 123 * D-cache Write-Back: 124 * If you can't Write-back without doing an Inv, 125 * that's fine. Then treat this as a WB-Inv. 126 * Skipping the invalidate is merely an optimization. 127 * 128 * All operations: 129 * Valid virtual addresses must be passed to each 130 * cache operation. 131 */ 132 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 133 134 void (*cf_dcache_wbinv_all) (void); 135 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 136 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 137 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 138 139 void (*cf_idcache_inv_all) (void); 140 void (*cf_idcache_wbinv_all) (void); 141 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 142 #endif 143 void (*cf_l2cache_wbinv_all) (void); 144 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 145 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 146 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 147 void (*cf_l2cache_drain_writebuf) (void); 148 149 /* Other functions */ 150 151 #if __ARM_ARCH < 6 152 void (*cf_drain_writebuf) (void); 153 #endif 154 155 void (*cf_sleep) (int mode); 156 157 #if __ARM_ARCH < 6 158 /* Soft functions */ 159 160 void (*cf_context_switch) (void); 161 #endif 162 163 void (*cf_setup) (void); 164 }; 165 166 extern struct cpu_functions cpufuncs; 167 extern u_int cputype; 168 169 #if __ARM_ARCH < 6 170 #define cpu_cpwait() cpufuncs.cf_cpwait() 171 172 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 173 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 174 175 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 176 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 177 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 178 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 179 180 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 181 182 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 183 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 184 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 185 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 186 187 #define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all() 188 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 189 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 190 #endif 191 192 #define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 193 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 194 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 195 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 196 #define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf() 197 198 #if __ARM_ARCH < 6 199 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 200 #endif 201 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 202 203 #define cpu_setup() cpufuncs.cf_setup() 204 205 int set_cpufuncs (void); 206 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 207 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 208 209 void cpufunc_nullop (void); 210 u_int cpufunc_control (u_int clear, u_int bic); 211 void cpu_domains (u_int domains); 212 213 #if defined(CPU_ARM9E) 214 void arm9_tlb_flushID_SE (u_int va); 215 void arm9_context_switch (void); 216 217 u_int sheeva_control_ext (u_int, u_int); 218 void sheeva_cpu_sleep (int); 219 void sheeva_setttb (u_int); 220 void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); 221 void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); 222 void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); 223 void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); 224 225 void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); 226 void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); 227 void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); 228 void sheeva_l2cache_wbinv_all (void); 229 #endif 230 231 #if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) 232 void armv7_cpu_sleep (int); 233 #endif 234 #if defined(CPU_MV_PJ4B) 235 void pj4b_config (void); 236 #endif 237 238 #if defined(CPU_ARM1176) 239 void arm11x6_sleep (int); /* no ref. for errata */ 240 #endif 241 242 #if defined(CPU_ARM9E) 243 void armv5_ec_setttb(u_int); 244 245 void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); 246 247 void armv5_ec_dcache_wbinv_all(void); 248 void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); 249 void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); 250 void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); 251 252 void armv5_ec_idcache_wbinv_all(void); 253 void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); 254 255 void armv4_tlb_flushID (void); 256 void armv4_tlb_flushD (void); 257 void armv4_tlb_flushD_SE (u_int va); 258 259 void armv4_drain_writebuf (void); 260 void armv4_idcache_inv_all (void); 261 #endif 262 263 /* 264 * Macros for manipulating CPU interrupts 265 */ 266 #if __ARM_ARCH < 6 267 #define __ARM_INTR_BITS (PSR_I | PSR_F) 268 #else 269 #define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A) 270 #endif 271 272 static __inline uint32_t 273 __set_cpsr(uint32_t bic, uint32_t eor) 274 { 275 uint32_t tmp, ret; 276 277 __asm __volatile( 278 "mrs %0, cpsr\n" /* Get the CPSR */ 279 "bic %1, %0, %2\n" /* Clear bits */ 280 "eor %1, %1, %3\n" /* XOR bits */ 281 "msr cpsr_xc, %1\n" /* Set the CPSR */ 282 : "=&r" (ret), "=&r" (tmp) 283 : "r" (bic), "r" (eor) : "memory"); 284 285 return ret; 286 } 287 288 static __inline uint32_t 289 disable_interrupts(uint32_t mask) 290 { 291 292 return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS)); 293 } 294 295 static __inline uint32_t 296 enable_interrupts(uint32_t mask) 297 { 298 299 return (__set_cpsr(mask & __ARM_INTR_BITS, 0)); 300 } 301 302 static __inline uint32_t 303 restore_interrupts(uint32_t old_cpsr) 304 { 305 306 return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS)); 307 } 308 309 static __inline register_t 310 intr_disable(void) 311 { 312 313 return (disable_interrupts(PSR_I | PSR_F)); 314 } 315 316 static __inline void 317 intr_restore(register_t s) 318 { 319 320 restore_interrupts(s); 321 } 322 #undef __ARM_INTR_BITS 323 324 /* 325 * Functions to manipulate cpu r13 326 * (in arm/arm32/setstack.S) 327 */ 328 329 void set_stackptr (u_int mode, u_int address); 330 u_int get_stackptr (u_int mode); 331 332 /* 333 * CPU functions from locore.S 334 */ 335 336 void cpu_reset (void) __attribute__((__noreturn__)); 337 338 /* 339 * Cache info variables. 340 */ 341 342 /* PRIMARY CACHE VARIABLES */ 343 extern int arm_picache_size; 344 extern int arm_picache_line_size; 345 extern int arm_picache_ways; 346 347 extern int arm_pdcache_size; /* and unified */ 348 extern int arm_pdcache_line_size; 349 extern int arm_pdcache_ways; 350 351 extern int arm_pcache_type; 352 extern int arm_pcache_unified; 353 354 extern int arm_dcache_align; 355 extern int arm_dcache_align_mask; 356 357 extern u_int arm_cache_level; 358 extern u_int arm_cache_loc; 359 extern u_int arm_cache_type[14]; 360 361 #if __ARM_ARCH >= 6 362 #define HAVE_INLINE_FFS 363 364 static __inline __pure2 int 365 ffs(int mask) 366 { 367 368 return (__builtin_ffs(mask)); 369 } 370 371 #define HAVE_INLINE_FFSL 372 373 static __inline __pure2 int 374 ffsl(long mask) 375 { 376 377 return (__builtin_ffsl(mask)); 378 } 379 380 #define HAVE_INLINE_FFSLL 381 382 static __inline __pure2 int 383 ffsll(long long mask) 384 { 385 386 return (__builtin_ffsll(mask)); 387 } 388 389 #define HAVE_INLINE_FLS 390 391 static __inline __pure2 int 392 fls(int mask) 393 { 394 395 return (mask == 0 ? 0 : 396 8 * sizeof(mask) - __builtin_clz((u_int)mask)); 397 } 398 399 #define HAVE_INLINE_FLSL 400 401 static __inline __pure2 int 402 flsl(long mask) 403 { 404 405 return (mask == 0 ? 0 : 406 8 * sizeof(mask) - __builtin_clzl((u_long)mask)); 407 } 408 409 #define HAVE_INLINE_FLSLL 410 411 static __inline __pure2 int 412 flsll(long long mask) 413 { 414 415 return (mask == 0 ? 0 : 416 8 * sizeof(mask) - __builtin_clzll((unsigned long long)mask)); 417 } 418 #endif 419 #else /* !_KERNEL */ 420 421 static __inline void 422 breakpoint(void) 423 { 424 425 /* 426 * This matches the instruction used by GDB for software 427 * breakpoints. 428 */ 429 __asm("udf 0xfdee"); 430 } 431 432 #endif /* _KERNEL */ 433 #endif /* _MACHINE_CPUFUNC_H_ */ 434 435 /* End of cpufunc.h */ 436