xref: /freebsd/sys/arm/include/cpufunc.h (revision 2be1a816b9ff69588e55be0a84cbe2a31efc0f2f)
1 /*	$NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $	*/
2 
3 /*-
4  * Copyright (c) 1997 Mark Brinicombe.
5  * Copyright (c) 1997 Causality Limited
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product includes software developed by Causality Limited.
19  * 4. The name of Causality Limited may not be used to endorse or promote
20  *    products derived from this software without specific prior written
21  *    permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
24  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26  * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
27  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33  * SUCH DAMAGE.
34  *
35  * RiscBSD kernel project
36  *
37  * cpufunc.h
38  *
39  * Prototypes for cpu, mmu and tlb related functions.
40  *
41  * $FreeBSD$
42  */
43 
44 #ifndef _MACHINE_CPUFUNC_H_
45 #define _MACHINE_CPUFUNC_H_
46 
47 #ifdef _KERNEL
48 
49 #include <sys/types.h>
50 #include <machine/cpuconf.h>
51 #include <machine/katelib.h> /* For in[bwl] and out[bwl] */
52 
53 static __inline void
54 breakpoint(void)
55 {
56 	__asm(".word      0xe7ffffff");
57 }
58 
59 struct cpu_functions {
60 
61 	/* CPU functions */
62 
63 	u_int	(*cf_id)		(void);
64 	void	(*cf_cpwait)		(void);
65 
66 	/* MMU functions */
67 
68 	u_int	(*cf_control)		(u_int bic, u_int eor);
69 	void	(*cf_domains)		(u_int domains);
70 	void	(*cf_setttb)		(u_int ttb);
71 	u_int	(*cf_faultstatus)	(void);
72 	u_int	(*cf_faultaddress)	(void);
73 
74 	/* TLB functions */
75 
76 	void	(*cf_tlb_flushID)	(void);
77 	void	(*cf_tlb_flushID_SE)	(u_int va);
78 	void	(*cf_tlb_flushI)	(void);
79 	void	(*cf_tlb_flushI_SE)	(u_int va);
80 	void	(*cf_tlb_flushD)	(void);
81 	void	(*cf_tlb_flushD_SE)	(u_int va);
82 
83 	/*
84 	 * Cache operations:
85 	 *
86 	 * We define the following primitives:
87 	 *
88 	 *	icache_sync_all		Synchronize I-cache
89 	 *	icache_sync_range	Synchronize I-cache range
90 	 *
91 	 *	dcache_wbinv_all	Write-back and Invalidate D-cache
92 	 *	dcache_wbinv_range	Write-back and Invalidate D-cache range
93 	 *	dcache_inv_range	Invalidate D-cache range
94 	 *	dcache_wb_range		Write-back D-cache range
95 	 *
96 	 *	idcache_wbinv_all	Write-back and Invalidate D-cache,
97 	 *				Invalidate I-cache
98 	 *	idcache_wbinv_range	Write-back and Invalidate D-cache,
99 	 *				Invalidate I-cache range
100 	 *
101 	 * Note that the ARM term for "write-back" is "clean".  We use
102 	 * the term "write-back" since it's a more common way to describe
103 	 * the operation.
104 	 *
105 	 * There are some rules that must be followed:
106 	 *
107 	 *	I-cache Synch (all or range):
108 	 *		The goal is to synchronize the instruction stream,
109 	 *		so you may beed to write-back dirty D-cache blocks
110 	 *		first.  If a range is requested, and you can't
111 	 *		synchronize just a range, you have to hit the whole
112 	 *		thing.
113 	 *
114 	 *	D-cache Write-Back and Invalidate range:
115 	 *		If you can't WB-Inv a range, you must WB-Inv the
116 	 *		entire D-cache.
117 	 *
118 	 *	D-cache Invalidate:
119 	 *		If you can't Inv the D-cache, you must Write-Back
120 	 *		and Invalidate.  Code that uses this operation
121 	 *		MUST NOT assume that the D-cache will not be written
122 	 *		back to memory.
123 	 *
124 	 *	D-cache Write-Back:
125 	 *		If you can't Write-back without doing an Inv,
126 	 *		that's fine.  Then treat this as a WB-Inv.
127 	 *		Skipping the invalidate is merely an optimization.
128 	 *
129 	 *	All operations:
130 	 *		Valid virtual addresses must be passed to each
131 	 *		cache operation.
132 	 */
133 	void	(*cf_icache_sync_all)	(void);
134 	void	(*cf_icache_sync_range)	(vm_offset_t, vm_size_t);
135 
136 	void	(*cf_dcache_wbinv_all)	(void);
137 	void	(*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t);
138 	void	(*cf_dcache_inv_range)	(vm_offset_t, vm_size_t);
139 	void	(*cf_dcache_wb_range)	(vm_offset_t, vm_size_t);
140 
141 	void	(*cf_idcache_wbinv_all)	(void);
142 	void	(*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
143 	void	(*cf_l2cache_wbinv_all) (void);
144 	void	(*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
145 	void	(*cf_l2cache_inv_range)	  (vm_offset_t, vm_size_t);
146 	void	(*cf_l2cache_wb_range)	  (vm_offset_t, vm_size_t);
147 
148 	/* Other functions */
149 
150 	void	(*cf_flush_prefetchbuf)	(void);
151 	void	(*cf_drain_writebuf)	(void);
152 	void	(*cf_flush_brnchtgt_C)	(void);
153 	void	(*cf_flush_brnchtgt_E)	(u_int va);
154 
155 	void	(*cf_sleep)		(int mode);
156 
157 	/* Soft functions */
158 
159 	int	(*cf_dataabt_fixup)	(void *arg);
160 	int	(*cf_prefetchabt_fixup)	(void *arg);
161 
162 	void	(*cf_context_switch)	(void);
163 
164 	void	(*cf_setup)		(char *string);
165 };
166 
167 extern struct cpu_functions cpufuncs;
168 extern u_int cputype;
169 
170 #define cpu_id()		cpufuncs.cf_id()
171 #define	cpu_cpwait()		cpufuncs.cf_cpwait()
172 
173 #define cpu_control(c, e)	cpufuncs.cf_control(c, e)
174 #define cpu_domains(d)		cpufuncs.cf_domains(d)
175 #define cpu_setttb(t)		cpufuncs.cf_setttb(t)
176 #define cpu_faultstatus()	cpufuncs.cf_faultstatus()
177 #define cpu_faultaddress()	cpufuncs.cf_faultaddress()
178 
179 #define	cpu_tlb_flushID()	cpufuncs.cf_tlb_flushID()
180 #define	cpu_tlb_flushID_SE(e)	cpufuncs.cf_tlb_flushID_SE(e)
181 #define	cpu_tlb_flushI()	cpufuncs.cf_tlb_flushI()
182 #define	cpu_tlb_flushI_SE(e)	cpufuncs.cf_tlb_flushI_SE(e)
183 #define	cpu_tlb_flushD()	cpufuncs.cf_tlb_flushD()
184 #define	cpu_tlb_flushD_SE(e)	cpufuncs.cf_tlb_flushD_SE(e)
185 
186 #define	cpu_icache_sync_all()	cpufuncs.cf_icache_sync_all()
187 #define	cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
188 
189 #define	cpu_dcache_wbinv_all()	cpufuncs.cf_dcache_wbinv_all()
190 #define	cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
191 #define	cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
192 #define	cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
193 
194 #define	cpu_idcache_wbinv_all()	cpufuncs.cf_idcache_wbinv_all()
195 #define	cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
196 #define cpu_l2cache_wbinv_all()	cpufuncs.cf_l2cache_wbinv_all()
197 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
198 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
199 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
200 
201 #define	cpu_flush_prefetchbuf()	cpufuncs.cf_flush_prefetchbuf()
202 #define	cpu_drain_writebuf()	cpufuncs.cf_drain_writebuf()
203 #define	cpu_flush_brnchtgt_C()	cpufuncs.cf_flush_brnchtgt_C()
204 #define	cpu_flush_brnchtgt_E(e)	cpufuncs.cf_flush_brnchtgt_E(e)
205 
206 #define cpu_sleep(m)		cpufuncs.cf_sleep(m)
207 
208 #define cpu_dataabt_fixup(a)		cpufuncs.cf_dataabt_fixup(a)
209 #define cpu_prefetchabt_fixup(a)	cpufuncs.cf_prefetchabt_fixup(a)
210 #define ABORT_FIXUP_OK		0	/* fixup succeeded */
211 #define ABORT_FIXUP_FAILED	1	/* fixup failed */
212 #define ABORT_FIXUP_RETURN	2	/* abort handler should return */
213 
214 #define cpu_setup(a)			cpufuncs.cf_setup(a)
215 
216 int	set_cpufuncs		(void);
217 #define ARCHITECTURE_NOT_PRESENT	1	/* known but not configured */
218 #define ARCHITECTURE_NOT_SUPPORTED	2	/* not known */
219 
220 void	cpufunc_nullop		(void);
221 int	cpufunc_null_fixup	(void *);
222 int	early_abort_fixup	(void *);
223 int	late_abort_fixup	(void *);
224 u_int	cpufunc_id		(void);
225 u_int	cpufunc_control		(u_int clear, u_int bic);
226 void	cpufunc_domains		(u_int domains);
227 u_int	cpufunc_faultstatus	(void);
228 u_int	cpufunc_faultaddress	(void);
229 
230 #ifdef CPU_ARM3
231 u_int	arm3_control		(u_int clear, u_int bic);
232 void	arm3_cache_flush	(void);
233 #endif	/* CPU_ARM3 */
234 
235 #if defined(CPU_ARM6) || defined(CPU_ARM7)
236 void	arm67_setttb		(u_int ttb);
237 void	arm67_tlb_flush		(void);
238 void	arm67_tlb_purge		(u_int va);
239 void	arm67_cache_flush	(void);
240 void	arm67_context_switch	(void);
241 #endif	/* CPU_ARM6 || CPU_ARM7 */
242 
243 #ifdef CPU_ARM6
244 void	arm6_setup		(char *string);
245 #endif	/* CPU_ARM6 */
246 
247 #ifdef CPU_ARM7
248 void	arm7_setup		(char *string);
249 #endif	/* CPU_ARM7 */
250 
251 #ifdef CPU_ARM7TDMI
252 int	arm7_dataabt_fixup	(void *arg);
253 void	arm7tdmi_setup		(char *string);
254 void	arm7tdmi_setttb		(u_int ttb);
255 void	arm7tdmi_tlb_flushID	(void);
256 void	arm7tdmi_tlb_flushID_SE	(u_int va);
257 void	arm7tdmi_cache_flushID	(void);
258 void	arm7tdmi_context_switch	(void);
259 #endif /* CPU_ARM7TDMI */
260 
261 #ifdef CPU_ARM8
262 void	arm8_setttb		(u_int ttb);
263 void	arm8_tlb_flushID	(void);
264 void	arm8_tlb_flushID_SE	(u_int va);
265 void	arm8_cache_flushID	(void);
266 void	arm8_cache_flushID_E	(u_int entry);
267 void	arm8_cache_cleanID	(void);
268 void	arm8_cache_cleanID_E	(u_int entry);
269 void	arm8_cache_purgeID	(void);
270 void	arm8_cache_purgeID_E	(u_int entry);
271 
272 void	arm8_cache_syncI	(void);
273 void	arm8_cache_cleanID_rng	(vm_offset_t start, vm_size_t end);
274 void	arm8_cache_cleanD_rng	(vm_offset_t start, vm_size_t end);
275 void	arm8_cache_purgeID_rng	(vm_offset_t start, vm_size_t end);
276 void	arm8_cache_purgeD_rng	(vm_offset_t start, vm_size_t end);
277 void	arm8_cache_syncI_rng	(vm_offset_t start, vm_size_t end);
278 
279 void	arm8_context_switch	(void);
280 
281 void	arm8_setup		(char *string);
282 
283 u_int	arm8_clock_config	(u_int, u_int);
284 #endif
285 
286 #ifdef CPU_SA110
287 void	sa110_setup		(char *string);
288 void	sa110_context_switch	(void);
289 #endif	/* CPU_SA110 */
290 
291 #if defined(CPU_SA1100) || defined(CPU_SA1110)
292 void	sa11x0_drain_readbuf	(void);
293 
294 void	sa11x0_context_switch	(void);
295 void	sa11x0_cpu_sleep	(int mode);
296 
297 void	sa11x0_setup		(char *string);
298 #endif
299 
300 #if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
301 void	sa1_setttb		(u_int ttb);
302 
303 void	sa1_tlb_flushID_SE	(u_int va);
304 
305 void	sa1_cache_flushID	(void);
306 void	sa1_cache_flushI	(void);
307 void	sa1_cache_flushD	(void);
308 void	sa1_cache_flushD_SE	(u_int entry);
309 
310 void	sa1_cache_cleanID	(void);
311 void	sa1_cache_cleanD	(void);
312 void	sa1_cache_cleanD_E	(u_int entry);
313 
314 void	sa1_cache_purgeID	(void);
315 void	sa1_cache_purgeID_E	(u_int entry);
316 void	sa1_cache_purgeD	(void);
317 void	sa1_cache_purgeD_E	(u_int entry);
318 
319 void	sa1_cache_syncI		(void);
320 void	sa1_cache_cleanID_rng	(vm_offset_t start, vm_size_t end);
321 void	sa1_cache_cleanD_rng	(vm_offset_t start, vm_size_t end);
322 void	sa1_cache_purgeID_rng	(vm_offset_t start, vm_size_t end);
323 void	sa1_cache_purgeD_rng	(vm_offset_t start, vm_size_t end);
324 void	sa1_cache_syncI_rng	(vm_offset_t start, vm_size_t end);
325 
326 #endif
327 
328 #ifdef CPU_ARM9
329 void	arm9_setttb		(u_int);
330 
331 void	arm9_tlb_flushID_SE	(u_int va);
332 
333 void	arm9_icache_sync_all	(void);
334 void	arm9_icache_sync_range	(vm_offset_t, vm_size_t);
335 
336 void	arm9_dcache_wbinv_all	(void);
337 void	arm9_dcache_wbinv_range (vm_offset_t, vm_size_t);
338 void	arm9_dcache_inv_range	(vm_offset_t, vm_size_t);
339 void	arm9_dcache_wb_range	(vm_offset_t, vm_size_t);
340 
341 void	arm9_idcache_wbinv_all	(void);
342 void	arm9_idcache_wbinv_range (vm_offset_t, vm_size_t);
343 
344 void	arm9_context_switch	(void);
345 
346 void	arm9_setup		(char *string);
347 
348 extern unsigned arm9_dcache_sets_max;
349 extern unsigned arm9_dcache_sets_inc;
350 extern unsigned arm9_dcache_index_max;
351 extern unsigned arm9_dcache_index_inc;
352 #endif
353 
354 #if defined(CPU_ARM9E) || defined(CPU_ARM10)
355 void	arm10_setttb		(u_int);
356 
357 void	arm10_tlb_flushID_SE	(u_int);
358 void	arm10_tlb_flushI_SE	(u_int);
359 
360 void	arm10_icache_sync_all	(void);
361 void	arm10_icache_sync_range	(vm_offset_t, vm_size_t);
362 
363 void	arm10_dcache_wbinv_all	(void);
364 void	arm10_dcache_wbinv_range (vm_offset_t, vm_size_t);
365 void	arm10_dcache_inv_range	(vm_offset_t, vm_size_t);
366 void	arm10_dcache_wb_range	(vm_offset_t, vm_size_t);
367 
368 void	arm10_idcache_wbinv_all	(void);
369 void	arm10_idcache_wbinv_range (vm_offset_t, vm_size_t);
370 
371 void	arm10_context_switch	(void);
372 
373 void	arm10_setup		(char *string);
374 
375 extern unsigned arm10_dcache_sets_max;
376 extern unsigned arm10_dcache_sets_inc;
377 extern unsigned arm10_dcache_index_max;
378 extern unsigned arm10_dcache_index_inc;
379 #endif
380 
381 #ifdef CPU_ARM11
382 void	arm11_setttb		(u_int);
383 
384 void	arm11_tlb_flushID_SE	(u_int);
385 void	arm11_tlb_flushI_SE	(u_int);
386 
387 void	arm11_context_switch	(void);
388 
389 void	arm11_setup		(char *string);
390 void	arm11_tlb_flushID	(void);
391 void	arm11_tlb_flushI	(void);
392 void	arm11_tlb_flushD	(void);
393 void	arm11_tlb_flushD_SE	(u_int va);
394 
395 void	arm11_drain_writebuf	(void);
396 #endif
397 
398 #if defined(CPU_ARM9E) || defined (CPU_ARM10)
399 void	armv5_ec_setttb(u_int);
400 
401 void	armv5_ec_icache_sync_all(void);
402 void	armv5_ec_icache_sync_range(vm_offset_t, vm_size_t);
403 
404 void	armv5_ec_dcache_wbinv_all(void);
405 void	armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t);
406 void	armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t);
407 void	armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t);
408 
409 void	armv5_ec_idcache_wbinv_all(void);
410 void	armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t);
411 #endif
412 
413 #if defined (CPU_ARM10) || defined (CPU_ARM11)
414 void	armv5_setttb(u_int);
415 
416 void	armv5_icache_sync_all(void);
417 void	armv5_icache_sync_range(vm_offset_t, vm_size_t);
418 
419 void	armv5_dcache_wbinv_all(void);
420 void	armv5_dcache_wbinv_range(vm_offset_t, vm_size_t);
421 void	armv5_dcache_inv_range(vm_offset_t, vm_size_t);
422 void	armv5_dcache_wb_range(vm_offset_t, vm_size_t);
423 
424 void	armv5_idcache_wbinv_all(void);
425 void	armv5_idcache_wbinv_range(vm_offset_t, vm_size_t);
426 
427 extern unsigned armv5_dcache_sets_max;
428 extern unsigned armv5_dcache_sets_inc;
429 extern unsigned armv5_dcache_index_max;
430 extern unsigned armv5_dcache_index_inc;
431 #endif
432 
433 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \
434   defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \
435   defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||	     \
436   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||	     \
437   defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
438 
439 void	armv4_tlb_flushID	(void);
440 void	armv4_tlb_flushI	(void);
441 void	armv4_tlb_flushD	(void);
442 void	armv4_tlb_flushD_SE	(u_int va);
443 
444 void	armv4_drain_writebuf	(void);
445 #endif
446 
447 #if defined(CPU_IXP12X0)
448 void	ixp12x0_drain_readbuf	(void);
449 void	ixp12x0_context_switch	(void);
450 void	ixp12x0_setup		(char *string);
451 #endif
452 
453 #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||	\
454   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||	\
455   defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
456 void	xscale_cpwait		(void);
457 
458 void	xscale_cpu_sleep	(int mode);
459 
460 u_int	xscale_control		(u_int clear, u_int bic);
461 
462 void	xscale_setttb		(u_int ttb);
463 
464 void	xscale_tlb_flushID_SE	(u_int va);
465 
466 void	xscale_cache_flushID	(void);
467 void	xscale_cache_flushI	(void);
468 void	xscale_cache_flushD	(void);
469 void	xscale_cache_flushD_SE	(u_int entry);
470 
471 void	xscale_cache_cleanID	(void);
472 void	xscale_cache_cleanD	(void);
473 void	xscale_cache_cleanD_E	(u_int entry);
474 
475 void	xscale_cache_clean_minidata (void);
476 
477 void	xscale_cache_purgeID	(void);
478 void	xscale_cache_purgeID_E	(u_int entry);
479 void	xscale_cache_purgeD	(void);
480 void	xscale_cache_purgeD_E	(u_int entry);
481 
482 void	xscale_cache_syncI	(void);
483 void	xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
484 void	xscale_cache_cleanD_rng	(vm_offset_t start, vm_size_t end);
485 void	xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
486 void	xscale_cache_purgeD_rng	(vm_offset_t start, vm_size_t end);
487 void	xscale_cache_syncI_rng	(vm_offset_t start, vm_size_t end);
488 void	xscale_cache_flushD_rng	(vm_offset_t start, vm_size_t end);
489 
490 void	xscale_context_switch	(void);
491 
492 void	xscale_setup		(char *string);
493 #endif	/* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
494 	   CPU_XSCALE_80219 */
495 
496 #ifdef	CPU_XSCALE_81342
497 
498 void	xscalec3_l2cache_purge	(void);
499 void	xscalec3_cache_purgeID	(void);
500 void	xscalec3_cache_purgeD	(void);
501 void	xscalec3_cache_cleanID	(void);
502 void	xscalec3_cache_cleanD	(void);
503 void	xscalec3_cache_syncI	(void);
504 
505 void	xscalec3_cache_purgeID_rng 	(vm_offset_t start, vm_size_t end);
506 void	xscalec3_cache_purgeD_rng	(vm_offset_t start, vm_size_t end);
507 void	xscalec3_cache_cleanID_rng	(vm_offset_t start, vm_size_t end);
508 void	xscalec3_cache_cleanD_rng	(vm_offset_t start, vm_size_t end);
509 void	xscalec3_cache_syncI_rng	(vm_offset_t start, vm_size_t end);
510 
511 void	xscalec3_l2cache_flush_rng	(vm_offset_t, vm_size_t);
512 void	xscalec3_l2cache_clean_rng	(vm_offset_t start, vm_size_t end);
513 void	xscalec3_l2cache_purge_rng	(vm_offset_t start, vm_size_t end);
514 
515 
516 void	xscalec3_setttb		(u_int ttb);
517 void	xscalec3_context_switch	(void);
518 
519 #endif /* CPU_XSCALE_81342 */
520 
521 #define tlb_flush	cpu_tlb_flushID
522 #define setttb		cpu_setttb
523 #define drain_writebuf	cpu_drain_writebuf
524 
525 /*
526  * Macros for manipulating CPU interrupts
527  */
528 static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__));
529 
530 static __inline u_int32_t
531 __set_cpsr_c(u_int bic, u_int eor)
532 {
533 	u_int32_t	tmp, ret;
534 
535 	__asm __volatile(
536 		"mrs     %0, cpsr\n"	/* Get the CPSR */
537 		"bic	 %1, %0, %2\n"	/* Clear bits */
538 		"eor	 %1, %1, %3\n"	/* XOR bits */
539 		"msr     cpsr_c, %1\n"	/* Set the control field of CPSR */
540 	: "=&r" (ret), "=&r" (tmp)
541 	: "r" (bic), "r" (eor) : "memory");
542 
543 	return ret;
544 }
545 
546 #define disable_interrupts(mask)					\
547 	(__set_cpsr_c((mask) & (I32_bit | F32_bit), \
548 		      (mask) & (I32_bit | F32_bit)))
549 
550 #define enable_interrupts(mask)						\
551 	(__set_cpsr_c((mask) & (I32_bit | F32_bit), 0))
552 
553 #define restore_interrupts(old_cpsr)					\
554 	(__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))
555 
556 #define intr_disable()	\
557     disable_interrupts(I32_bit | F32_bit)
558 #define intr_restore(s)	\
559     restore_interrupts(s)
560 /* Functions to manipulate the CPSR. */
561 u_int	SetCPSR(u_int bic, u_int eor);
562 u_int	GetCPSR(void);
563 
564 /*
565  * Functions to manipulate cpu r13
566  * (in arm/arm32/setstack.S)
567  */
568 
569 void set_stackptr	(u_int mode, u_int address);
570 u_int get_stackptr	(u_int mode);
571 
572 /*
573  * Miscellany
574  */
575 
576 int get_pc_str_offset	(void);
577 
578 /*
579  * CPU functions from locore.S
580  */
581 
582 void cpu_reset		(void) __attribute__((__noreturn__));
583 
584 /*
585  * Cache info variables.
586  */
587 
588 /* PRIMARY CACHE VARIABLES */
589 extern int	arm_picache_size;
590 extern int	arm_picache_line_size;
591 extern int	arm_picache_ways;
592 
593 extern int	arm_pdcache_size;	/* and unified */
594 extern int	arm_pdcache_line_size;
595 extern int	arm_pdcache_ways;
596 
597 extern int	arm_pcache_type;
598 extern int	arm_pcache_unified;
599 
600 extern int	arm_dcache_align;
601 extern int	arm_dcache_align_mask;
602 
603 #endif	/* _KERNEL */
604 #endif	/* _MACHINE_CPUFUNC_H_ */
605 
606 /* End of cpufunc.h */
607