1 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * 41 * $FreeBSD$ 42 */ 43 44 #ifndef _MACHINE_CPUFUNC_H_ 45 #define _MACHINE_CPUFUNC_H_ 46 47 #ifdef _KERNEL 48 49 #include <sys/types.h> 50 #include <machine/armreg.h> 51 #include <machine/cpuconf.h> 52 #include <machine/katelib.h> /* For in[bwl] and out[bwl] */ 53 54 static __inline void 55 breakpoint(void) 56 { 57 __asm(".word 0xe7ffffff"); 58 } 59 60 struct cpu_functions { 61 62 /* CPU functions */ 63 64 u_int (*cf_id) (void); 65 void (*cf_cpwait) (void); 66 67 /* MMU functions */ 68 69 u_int (*cf_control) (u_int bic, u_int eor); 70 void (*cf_domains) (u_int domains); 71 void (*cf_setttb) (u_int ttb); 72 u_int (*cf_faultstatus) (void); 73 u_int (*cf_faultaddress) (void); 74 75 /* TLB functions */ 76 77 void (*cf_tlb_flushID) (void); 78 void (*cf_tlb_flushID_SE) (u_int va); 79 void (*cf_tlb_flushI) (void); 80 void (*cf_tlb_flushI_SE) (u_int va); 81 void (*cf_tlb_flushD) (void); 82 void (*cf_tlb_flushD_SE) (u_int va); 83 84 /* 85 * Cache operations: 86 * 87 * We define the following primitives: 88 * 89 * icache_sync_all Synchronize I-cache 90 * icache_sync_range Synchronize I-cache range 91 * 92 * dcache_wbinv_all Write-back and Invalidate D-cache 93 * dcache_wbinv_range Write-back and Invalidate D-cache range 94 * dcache_inv_range Invalidate D-cache range 95 * dcache_wb_range Write-back D-cache range 96 * 97 * idcache_wbinv_all Write-back and Invalidate D-cache, 98 * Invalidate I-cache 99 * idcache_wbinv_range Write-back and Invalidate D-cache, 100 * Invalidate I-cache range 101 * 102 * Note that the ARM term for "write-back" is "clean". We use 103 * the term "write-back" since it's a more common way to describe 104 * the operation. 105 * 106 * There are some rules that must be followed: 107 * 108 * ID-cache Invalidate All: 109 * Unlike other functions, this one must never write back. 110 * It is used to intialize the MMU when it is in an unknown 111 * state (such as when it may have lines tagged as valid 112 * that belong to a previous set of mappings). 113 * 114 * I-cache Synch (all or range): 115 * The goal is to synchronize the instruction stream, 116 * so you may beed to write-back dirty D-cache blocks 117 * first. If a range is requested, and you can't 118 * synchronize just a range, you have to hit the whole 119 * thing. 120 * 121 * D-cache Write-Back and Invalidate range: 122 * If you can't WB-Inv a range, you must WB-Inv the 123 * entire D-cache. 124 * 125 * D-cache Invalidate: 126 * If you can't Inv the D-cache, you must Write-Back 127 * and Invalidate. Code that uses this operation 128 * MUST NOT assume that the D-cache will not be written 129 * back to memory. 130 * 131 * D-cache Write-Back: 132 * If you can't Write-back without doing an Inv, 133 * that's fine. Then treat this as a WB-Inv. 134 * Skipping the invalidate is merely an optimization. 135 * 136 * All operations: 137 * Valid virtual addresses must be passed to each 138 * cache operation. 139 */ 140 void (*cf_icache_sync_all) (void); 141 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 142 143 void (*cf_dcache_wbinv_all) (void); 144 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 145 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 146 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 147 148 void (*cf_idcache_inv_all) (void); 149 void (*cf_idcache_wbinv_all) (void); 150 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 151 void (*cf_l2cache_wbinv_all) (void); 152 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 153 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 154 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 155 void (*cf_l2cache_drain_writebuf) (void); 156 157 /* Other functions */ 158 159 void (*cf_flush_prefetchbuf) (void); 160 void (*cf_drain_writebuf) (void); 161 void (*cf_flush_brnchtgt_C) (void); 162 void (*cf_flush_brnchtgt_E) (u_int va); 163 164 void (*cf_sleep) (int mode); 165 166 /* Soft functions */ 167 168 int (*cf_dataabt_fixup) (void *arg); 169 int (*cf_prefetchabt_fixup) (void *arg); 170 171 void (*cf_context_switch) (void); 172 173 void (*cf_setup) (void); 174 }; 175 176 extern struct cpu_functions cpufuncs; 177 extern u_int cputype; 178 179 #define cpu_ident() cpufuncs.cf_id() 180 #define cpu_cpwait() cpufuncs.cf_cpwait() 181 182 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 183 #define cpu_domains(d) cpufuncs.cf_domains(d) 184 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 185 #define cpu_faultstatus() cpufuncs.cf_faultstatus() 186 #define cpu_faultaddress() cpufuncs.cf_faultaddress() 187 188 #ifndef SMP 189 190 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 191 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 192 #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 193 #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 194 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 195 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 196 197 #else 198 void tlb_broadcast(int); 199 200 #if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) 201 #define TLB_BROADCAST /* No need to explicitely send an IPI */ 202 #else 203 #define TLB_BROADCAST tlb_broadcast(7) 204 #endif 205 206 #define cpu_tlb_flushID() do { \ 207 cpufuncs.cf_tlb_flushID(); \ 208 TLB_BROADCAST; \ 209 } while(0) 210 211 #define cpu_tlb_flushID_SE(e) do { \ 212 cpufuncs.cf_tlb_flushID_SE(e); \ 213 TLB_BROADCAST; \ 214 } while(0) 215 216 217 #define cpu_tlb_flushI() do { \ 218 cpufuncs.cf_tlb_flushI(); \ 219 TLB_BROADCAST; \ 220 } while(0) 221 222 223 #define cpu_tlb_flushI_SE(e) do { \ 224 cpufuncs.cf_tlb_flushI_SE(e); \ 225 TLB_BROADCAST; \ 226 } while(0) 227 228 229 #define cpu_tlb_flushD() do { \ 230 cpufuncs.cf_tlb_flushD(); \ 231 TLB_BROADCAST; \ 232 } while(0) 233 234 235 #define cpu_tlb_flushD_SE(e) do { \ 236 cpufuncs.cf_tlb_flushD_SE(e); \ 237 TLB_BROADCAST; \ 238 } while(0) 239 240 #endif 241 242 #define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 243 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 244 245 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 246 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 247 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 248 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 249 250 #define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all() 251 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 252 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 253 #define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 254 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 255 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 256 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 257 #define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf() 258 259 #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 260 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 261 #define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 262 #define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 263 264 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 265 266 #define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 267 #define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 268 #define ABORT_FIXUP_OK 0 /* fixup succeeded */ 269 #define ABORT_FIXUP_FAILED 1 /* fixup failed */ 270 #define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 271 272 #define cpu_setup() cpufuncs.cf_setup() 273 274 int set_cpufuncs (void); 275 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 276 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 277 278 void cpufunc_nullop (void); 279 int cpufunc_null_fixup (void *); 280 int early_abort_fixup (void *); 281 int late_abort_fixup (void *); 282 u_int cpufunc_id (void); 283 u_int cpufunc_cpuid (void); 284 u_int cpufunc_control (u_int clear, u_int bic); 285 void cpufunc_domains (u_int domains); 286 u_int cpufunc_faultstatus (void); 287 u_int cpufunc_faultaddress (void); 288 u_int cpu_pfr (int); 289 290 #if defined(CPU_FA526) 291 void fa526_setup (void); 292 void fa526_setttb (u_int ttb); 293 void fa526_context_switch (void); 294 void fa526_cpu_sleep (int); 295 void fa526_tlb_flushI_SE (u_int); 296 void fa526_tlb_flushID_SE (u_int); 297 void fa526_flush_prefetchbuf (void); 298 void fa526_flush_brnchtgt_E (u_int); 299 300 void fa526_icache_sync_all (void); 301 void fa526_icache_sync_range(vm_offset_t start, vm_size_t end); 302 void fa526_dcache_wbinv_all (void); 303 void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end); 304 void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end); 305 void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end); 306 void fa526_idcache_wbinv_all(void); 307 void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end); 308 #endif 309 310 311 #ifdef CPU_ARM9 312 void arm9_setttb (u_int); 313 314 void arm9_tlb_flushID_SE (u_int va); 315 316 void arm9_icache_sync_all (void); 317 void arm9_icache_sync_range (vm_offset_t, vm_size_t); 318 319 void arm9_dcache_wbinv_all (void); 320 void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); 321 void arm9_dcache_inv_range (vm_offset_t, vm_size_t); 322 void arm9_dcache_wb_range (vm_offset_t, vm_size_t); 323 324 void arm9_idcache_wbinv_all (void); 325 void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); 326 327 void arm9_context_switch (void); 328 329 void arm9_setup (void); 330 331 extern unsigned arm9_dcache_sets_max; 332 extern unsigned arm9_dcache_sets_inc; 333 extern unsigned arm9_dcache_index_max; 334 extern unsigned arm9_dcache_index_inc; 335 #endif 336 337 #if defined(CPU_ARM9E) 338 void arm10_tlb_flushID_SE (u_int); 339 void arm10_tlb_flushI_SE (u_int); 340 341 void arm10_context_switch (void); 342 343 void arm10_setup (void); 344 345 u_int sheeva_control_ext (u_int, u_int); 346 void sheeva_cpu_sleep (int); 347 void sheeva_setttb (u_int); 348 void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); 349 void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); 350 void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); 351 void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); 352 353 void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); 354 void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); 355 void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); 356 void sheeva_l2cache_wbinv_all (void); 357 #endif 358 359 #if defined(CPU_MV_PJ4B) 360 void armv6_idcache_wbinv_all (void); 361 #endif 362 #if defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT) 363 void armv7_setttb (u_int); 364 void armv7_tlb_flushID (void); 365 void armv7_tlb_flushID_SE (u_int); 366 void armv7_icache_sync_all (void); 367 void armv7_icache_sync_range (vm_offset_t, vm_size_t); 368 void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); 369 void armv7_idcache_inv_all (void); 370 void armv7_dcache_wbinv_all (void); 371 void armv7_idcache_wbinv_all (void); 372 void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t); 373 void armv7_dcache_inv_range (vm_offset_t, vm_size_t); 374 void armv7_dcache_wb_range (vm_offset_t, vm_size_t); 375 void armv7_cpu_sleep (int); 376 void armv7_setup (void); 377 void armv7_context_switch (void); 378 void armv7_drain_writebuf (void); 379 void armv7_sev (void); 380 u_int armv7_auxctrl (u_int, u_int); 381 382 void armadaxp_idcache_wbinv_all (void); 383 384 void cortexa_setup (void); 385 #endif 386 #if defined(CPU_MV_PJ4B) 387 void pj4b_config (void); 388 void pj4bv7_setup (void); 389 #endif 390 391 #if defined(CPU_ARM1176) 392 void arm11_tlb_flushID (void); 393 void arm11_tlb_flushID_SE (u_int); 394 void arm11_tlb_flushI (void); 395 void arm11_tlb_flushI_SE (u_int); 396 void arm11_tlb_flushD (void); 397 void arm11_tlb_flushD_SE (u_int va); 398 399 void arm11_context_switch (void); 400 401 void arm11_drain_writebuf (void); 402 403 void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t); 404 void armv6_dcache_inv_range (vm_offset_t, vm_size_t); 405 void armv6_dcache_wb_range (vm_offset_t, vm_size_t); 406 407 void armv6_idcache_inv_all (void); 408 409 void arm11x6_setttb (u_int); 410 void arm11x6_idcache_wbinv_all (void); 411 void arm11x6_dcache_wbinv_all (void); 412 void arm11x6_icache_sync_all (void); 413 void arm11x6_flush_prefetchbuf (void); 414 void arm11x6_icache_sync_range (vm_offset_t, vm_size_t); 415 void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t); 416 void arm11x6_setup (void); 417 void arm11x6_sleep (int); /* no ref. for errata */ 418 #endif 419 420 #if defined(CPU_ARM9E) 421 void armv5_ec_setttb(u_int); 422 423 void armv5_ec_icache_sync_all(void); 424 void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); 425 426 void armv5_ec_dcache_wbinv_all(void); 427 void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); 428 void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); 429 void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); 430 431 void armv5_ec_idcache_wbinv_all(void); 432 void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); 433 #endif 434 435 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 436 defined(CPU_XSCALE_80321) || \ 437 defined(CPU_FA526) || \ 438 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 439 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 440 441 void armv4_tlb_flushID (void); 442 void armv4_tlb_flushI (void); 443 void armv4_tlb_flushD (void); 444 void armv4_tlb_flushD_SE (u_int va); 445 446 void armv4_drain_writebuf (void); 447 void armv4_idcache_inv_all (void); 448 #endif 449 450 #if defined(CPU_XSCALE_80321) || \ 451 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 452 defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 453 void xscale_cpwait (void); 454 455 void xscale_cpu_sleep (int mode); 456 457 u_int xscale_control (u_int clear, u_int bic); 458 459 void xscale_setttb (u_int ttb); 460 461 void xscale_tlb_flushID_SE (u_int va); 462 463 void xscale_cache_flushID (void); 464 void xscale_cache_flushI (void); 465 void xscale_cache_flushD (void); 466 void xscale_cache_flushD_SE (u_int entry); 467 468 void xscale_cache_cleanID (void); 469 void xscale_cache_cleanD (void); 470 void xscale_cache_cleanD_E (u_int entry); 471 472 void xscale_cache_clean_minidata (void); 473 474 void xscale_cache_purgeID (void); 475 void xscale_cache_purgeID_E (u_int entry); 476 void xscale_cache_purgeD (void); 477 void xscale_cache_purgeD_E (u_int entry); 478 479 void xscale_cache_syncI (void); 480 void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 481 void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 482 void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 483 void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 484 void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 485 void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 486 487 void xscale_context_switch (void); 488 489 void xscale_setup (void); 490 #endif /* CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 491 CPU_XSCALE_80219 */ 492 493 #ifdef CPU_XSCALE_81342 494 495 void xscalec3_l2cache_purge (void); 496 void xscalec3_cache_purgeID (void); 497 void xscalec3_cache_purgeD (void); 498 void xscalec3_cache_cleanID (void); 499 void xscalec3_cache_cleanD (void); 500 void xscalec3_cache_syncI (void); 501 502 void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 503 void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 504 void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 505 void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 506 void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end); 507 508 void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t); 509 void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end); 510 void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end); 511 512 513 void xscalec3_setttb (u_int ttb); 514 void xscalec3_context_switch (void); 515 516 #endif /* CPU_XSCALE_81342 */ 517 518 #define setttb cpu_setttb 519 #define drain_writebuf cpu_drain_writebuf 520 521 /* 522 * Macros for manipulating CPU interrupts 523 */ 524 #if __ARM_ARCH < 6 525 #define __ARM_INTR_BITS (PSR_I | PSR_F) 526 #else 527 #define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A) 528 #endif 529 530 static __inline uint32_t 531 __set_cpsr(uint32_t bic, uint32_t eor) 532 { 533 uint32_t tmp, ret; 534 535 __asm __volatile( 536 "mrs %0, cpsr\n" /* Get the CPSR */ 537 "bic %1, %0, %2\n" /* Clear bits */ 538 "eor %1, %1, %3\n" /* XOR bits */ 539 "msr cpsr_xc, %1\n" /* Set the CPSR */ 540 : "=&r" (ret), "=&r" (tmp) 541 : "r" (bic), "r" (eor) : "memory"); 542 543 return ret; 544 } 545 546 static __inline uint32_t 547 disable_interrupts(uint32_t mask) 548 { 549 550 return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS)); 551 } 552 553 static __inline uint32_t 554 enable_interrupts(uint32_t mask) 555 { 556 557 return (__set_cpsr(mask & __ARM_INTR_BITS, 0)); 558 } 559 560 static __inline uint32_t 561 restore_interrupts(uint32_t old_cpsr) 562 { 563 564 return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS)); 565 } 566 567 static __inline register_t 568 intr_disable(void) 569 { 570 571 return (disable_interrupts(PSR_I | PSR_F)); 572 } 573 574 static __inline void 575 intr_restore(register_t s) 576 { 577 578 restore_interrupts(s); 579 } 580 #undef __ARM_INTR_BITS 581 582 /* 583 * Functions to manipulate cpu r13 584 * (in arm/arm32/setstack.S) 585 */ 586 587 void set_stackptr (u_int mode, u_int address); 588 u_int get_stackptr (u_int mode); 589 590 /* 591 * Miscellany 592 */ 593 594 int get_pc_str_offset (void); 595 596 /* 597 * CPU functions from locore.S 598 */ 599 600 void cpu_reset (void) __attribute__((__noreturn__)); 601 602 /* 603 * Cache info variables. 604 */ 605 606 /* PRIMARY CACHE VARIABLES */ 607 extern int arm_picache_size; 608 extern int arm_picache_line_size; 609 extern int arm_picache_ways; 610 611 extern int arm_pdcache_size; /* and unified */ 612 extern int arm_pdcache_line_size; 613 extern int arm_pdcache_ways; 614 615 extern int arm_pcache_type; 616 extern int arm_pcache_unified; 617 618 extern int arm_dcache_align; 619 extern int arm_dcache_align_mask; 620 621 extern u_int arm_cache_level; 622 extern u_int arm_cache_loc; 623 extern u_int arm_cache_type[14]; 624 625 #endif /* _KERNEL */ 626 #endif /* _MACHINE_CPUFUNC_H_ */ 627 628 /* End of cpufunc.h */ 629