xref: /freebsd/sys/arm/include/cpufunc.h (revision 276da39af92f48350aa01091a2b8b3e735217eea)
1 /*	$NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $	*/
2 
3 /*-
4  * Copyright (c) 1997 Mark Brinicombe.
5  * Copyright (c) 1997 Causality Limited
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product includes software developed by Causality Limited.
19  * 4. The name of Causality Limited may not be used to endorse or promote
20  *    products derived from this software without specific prior written
21  *    permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
24  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26  * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
27  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33  * SUCH DAMAGE.
34  *
35  * RiscBSD kernel project
36  *
37  * cpufunc.h
38  *
39  * Prototypes for cpu, mmu and tlb related functions.
40  *
41  * $FreeBSD$
42  */
43 
44 #ifndef _MACHINE_CPUFUNC_H_
45 #define _MACHINE_CPUFUNC_H_
46 
47 #ifdef _KERNEL
48 
49 #include <sys/types.h>
50 #include <machine/cpuconf.h>
51 #include <machine/katelib.h> /* For in[bwl] and out[bwl] */
52 
53 static __inline void
54 breakpoint(void)
55 {
56 	__asm(".word      0xe7ffffff");
57 }
58 
59 struct cpu_functions {
60 
61 	/* CPU functions */
62 
63 	u_int	(*cf_id)		(void);
64 	void	(*cf_cpwait)		(void);
65 
66 	/* MMU functions */
67 
68 	u_int	(*cf_control)		(u_int bic, u_int eor);
69 	void	(*cf_domains)		(u_int domains);
70 	void	(*cf_setttb)		(u_int ttb);
71 	u_int	(*cf_faultstatus)	(void);
72 	u_int	(*cf_faultaddress)	(void);
73 
74 	/* TLB functions */
75 
76 	void	(*cf_tlb_flushID)	(void);
77 	void	(*cf_tlb_flushID_SE)	(u_int va);
78 	void	(*cf_tlb_flushI)	(void);
79 	void	(*cf_tlb_flushI_SE)	(u_int va);
80 	void	(*cf_tlb_flushD)	(void);
81 	void	(*cf_tlb_flushD_SE)	(u_int va);
82 
83 	/*
84 	 * Cache operations:
85 	 *
86 	 * We define the following primitives:
87 	 *
88 	 *	icache_sync_all		Synchronize I-cache
89 	 *	icache_sync_range	Synchronize I-cache range
90 	 *
91 	 *	dcache_wbinv_all	Write-back and Invalidate D-cache
92 	 *	dcache_wbinv_range	Write-back and Invalidate D-cache range
93 	 *	dcache_inv_range	Invalidate D-cache range
94 	 *	dcache_wb_range		Write-back D-cache range
95 	 *
96 	 *	idcache_wbinv_all	Write-back and Invalidate D-cache,
97 	 *				Invalidate I-cache
98 	 *	idcache_wbinv_range	Write-back and Invalidate D-cache,
99 	 *				Invalidate I-cache range
100 	 *
101 	 * Note that the ARM term for "write-back" is "clean".  We use
102 	 * the term "write-back" since it's a more common way to describe
103 	 * the operation.
104 	 *
105 	 * There are some rules that must be followed:
106 	 *
107 	 *	ID-cache Invalidate All:
108 	 *		Unlike other functions, this one must never write back.
109 	 *		It is used to intialize the MMU when it is in an unknown
110 	 *		state (such as when it may have lines tagged as valid
111 	 *		that belong to a previous set of mappings).
112 	 *
113 	 *	I-cache Synch (all or range):
114 	 *		The goal is to synchronize the instruction stream,
115 	 *		so you may beed to write-back dirty D-cache blocks
116 	 *		first.  If a range is requested, and you can't
117 	 *		synchronize just a range, you have to hit the whole
118 	 *		thing.
119 	 *
120 	 *	D-cache Write-Back and Invalidate range:
121 	 *		If you can't WB-Inv a range, you must WB-Inv the
122 	 *		entire D-cache.
123 	 *
124 	 *	D-cache Invalidate:
125 	 *		If you can't Inv the D-cache, you must Write-Back
126 	 *		and Invalidate.  Code that uses this operation
127 	 *		MUST NOT assume that the D-cache will not be written
128 	 *		back to memory.
129 	 *
130 	 *	D-cache Write-Back:
131 	 *		If you can't Write-back without doing an Inv,
132 	 *		that's fine.  Then treat this as a WB-Inv.
133 	 *		Skipping the invalidate is merely an optimization.
134 	 *
135 	 *	All operations:
136 	 *		Valid virtual addresses must be passed to each
137 	 *		cache operation.
138 	 */
139 	void	(*cf_icache_sync_all)	(void);
140 	void	(*cf_icache_sync_range)	(vm_offset_t, vm_size_t);
141 
142 	void	(*cf_dcache_wbinv_all)	(void);
143 	void	(*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t);
144 	void	(*cf_dcache_inv_range)	(vm_offset_t, vm_size_t);
145 	void	(*cf_dcache_wb_range)	(vm_offset_t, vm_size_t);
146 
147 	void	(*cf_idcache_inv_all)	(void);
148 	void	(*cf_idcache_wbinv_all)	(void);
149 	void	(*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
150 	void	(*cf_l2cache_wbinv_all) (void);
151 	void	(*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
152 	void	(*cf_l2cache_inv_range)	  (vm_offset_t, vm_size_t);
153 	void	(*cf_l2cache_wb_range)	  (vm_offset_t, vm_size_t);
154 	void	(*cf_l2cache_drain_writebuf)	  (void);
155 
156 	/* Other functions */
157 
158 	void	(*cf_flush_prefetchbuf)	(void);
159 	void	(*cf_drain_writebuf)	(void);
160 	void	(*cf_flush_brnchtgt_C)	(void);
161 	void	(*cf_flush_brnchtgt_E)	(u_int va);
162 
163 	void	(*cf_sleep)		(int mode);
164 
165 	/* Soft functions */
166 
167 	int	(*cf_dataabt_fixup)	(void *arg);
168 	int	(*cf_prefetchabt_fixup)	(void *arg);
169 
170 	void	(*cf_context_switch)	(void);
171 
172 	void	(*cf_setup)		(void);
173 };
174 
175 extern struct cpu_functions cpufuncs;
176 extern u_int cputype;
177 
178 #define cpu_ident()		cpufuncs.cf_id()
179 #define	cpu_cpwait()		cpufuncs.cf_cpwait()
180 
181 #define cpu_control(c, e)	cpufuncs.cf_control(c, e)
182 #define cpu_domains(d)		cpufuncs.cf_domains(d)
183 #define cpu_setttb(t)		cpufuncs.cf_setttb(t)
184 #define cpu_faultstatus()	cpufuncs.cf_faultstatus()
185 #define cpu_faultaddress()	cpufuncs.cf_faultaddress()
186 
187 #ifndef SMP
188 
189 #define	cpu_tlb_flushID()	cpufuncs.cf_tlb_flushID()
190 #define	cpu_tlb_flushID_SE(e)	cpufuncs.cf_tlb_flushID_SE(e)
191 #define	cpu_tlb_flushI()	cpufuncs.cf_tlb_flushI()
192 #define	cpu_tlb_flushI_SE(e)	cpufuncs.cf_tlb_flushI_SE(e)
193 #define	cpu_tlb_flushD()	cpufuncs.cf_tlb_flushD()
194 #define	cpu_tlb_flushD_SE(e)	cpufuncs.cf_tlb_flushD_SE(e)
195 
196 #else
197 void tlb_broadcast(int);
198 
199 #if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT)
200 #define TLB_BROADCAST	/* No need to explicitely send an IPI */
201 #else
202 #define TLB_BROADCAST	tlb_broadcast(7)
203 #endif
204 
205 #define	cpu_tlb_flushID() do { \
206 	cpufuncs.cf_tlb_flushID(); \
207 	TLB_BROADCAST; \
208 } while(0)
209 
210 #define	cpu_tlb_flushID_SE(e) do { \
211 	cpufuncs.cf_tlb_flushID_SE(e); \
212 	TLB_BROADCAST; \
213 } while(0)
214 
215 
216 #define	cpu_tlb_flushI() do { \
217 	cpufuncs.cf_tlb_flushI(); \
218 	TLB_BROADCAST; \
219 } while(0)
220 
221 
222 #define	cpu_tlb_flushI_SE(e) do { \
223 	cpufuncs.cf_tlb_flushI_SE(e); \
224 	TLB_BROADCAST; \
225 } while(0)
226 
227 
228 #define	cpu_tlb_flushD() do { \
229 	cpufuncs.cf_tlb_flushD(); \
230 	TLB_BROADCAST; \
231 } while(0)
232 
233 
234 #define	cpu_tlb_flushD_SE(e) do { \
235 	cpufuncs.cf_tlb_flushD_SE(e); \
236 	TLB_BROADCAST; \
237 } while(0)
238 
239 #endif
240 
241 #define	cpu_icache_sync_all()	cpufuncs.cf_icache_sync_all()
242 #define	cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
243 
244 #define	cpu_dcache_wbinv_all()	cpufuncs.cf_dcache_wbinv_all()
245 #define	cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
246 #define	cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
247 #define	cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
248 
249 #define	cpu_idcache_inv_all()	cpufuncs.cf_idcache_inv_all()
250 #define	cpu_idcache_wbinv_all()	cpufuncs.cf_idcache_wbinv_all()
251 #define	cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
252 #define cpu_l2cache_wbinv_all()	cpufuncs.cf_l2cache_wbinv_all()
253 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
254 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
255 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
256 #define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf()
257 
258 #define	cpu_flush_prefetchbuf()	cpufuncs.cf_flush_prefetchbuf()
259 #define	cpu_drain_writebuf()	cpufuncs.cf_drain_writebuf()
260 #define	cpu_flush_brnchtgt_C()	cpufuncs.cf_flush_brnchtgt_C()
261 #define	cpu_flush_brnchtgt_E(e)	cpufuncs.cf_flush_brnchtgt_E(e)
262 
263 #define cpu_sleep(m)		cpufuncs.cf_sleep(m)
264 
265 #define cpu_dataabt_fixup(a)		cpufuncs.cf_dataabt_fixup(a)
266 #define cpu_prefetchabt_fixup(a)	cpufuncs.cf_prefetchabt_fixup(a)
267 #define ABORT_FIXUP_OK		0	/* fixup succeeded */
268 #define ABORT_FIXUP_FAILED	1	/* fixup failed */
269 #define ABORT_FIXUP_RETURN	2	/* abort handler should return */
270 
271 #define cpu_setup()			cpufuncs.cf_setup()
272 
273 int	set_cpufuncs		(void);
274 #define ARCHITECTURE_NOT_PRESENT	1	/* known but not configured */
275 #define ARCHITECTURE_NOT_SUPPORTED	2	/* not known */
276 
277 void	cpufunc_nullop		(void);
278 int	cpufunc_null_fixup	(void *);
279 int	early_abort_fixup	(void *);
280 int	late_abort_fixup	(void *);
281 u_int	cpufunc_id		(void);
282 u_int	cpufunc_cpuid		(void);
283 u_int	cpufunc_control		(u_int clear, u_int bic);
284 void	cpufunc_domains		(u_int domains);
285 u_int	cpufunc_faultstatus	(void);
286 u_int	cpufunc_faultaddress	(void);
287 u_int	cpu_pfr			(int);
288 
289 #if defined(CPU_FA526)
290 void	fa526_setup		(void);
291 void	fa526_setttb		(u_int ttb);
292 void	fa526_context_switch	(void);
293 void	fa526_cpu_sleep		(int);
294 void	fa526_tlb_flushI_SE	(u_int);
295 void	fa526_tlb_flushID_SE	(u_int);
296 void	fa526_flush_prefetchbuf	(void);
297 void	fa526_flush_brnchtgt_E	(u_int);
298 
299 void	fa526_icache_sync_all	(void);
300 void	fa526_icache_sync_range(vm_offset_t start, vm_size_t end);
301 void	fa526_dcache_wbinv_all	(void);
302 void	fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end);
303 void	fa526_dcache_inv_range	(vm_offset_t start, vm_size_t end);
304 void	fa526_dcache_wb_range	(vm_offset_t start, vm_size_t end);
305 void	fa526_idcache_wbinv_all(void);
306 void	fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end);
307 #endif
308 
309 
310 #ifdef CPU_ARM9
311 void	arm9_setttb		(u_int);
312 
313 void	arm9_tlb_flushID_SE	(u_int va);
314 
315 void	arm9_icache_sync_all	(void);
316 void	arm9_icache_sync_range	(vm_offset_t, vm_size_t);
317 
318 void	arm9_dcache_wbinv_all	(void);
319 void	arm9_dcache_wbinv_range (vm_offset_t, vm_size_t);
320 void	arm9_dcache_inv_range	(vm_offset_t, vm_size_t);
321 void	arm9_dcache_wb_range	(vm_offset_t, vm_size_t);
322 
323 void	arm9_idcache_wbinv_all	(void);
324 void	arm9_idcache_wbinv_range (vm_offset_t, vm_size_t);
325 
326 void	arm9_context_switch	(void);
327 
328 void	arm9_setup		(void);
329 
330 extern unsigned arm9_dcache_sets_max;
331 extern unsigned arm9_dcache_sets_inc;
332 extern unsigned arm9_dcache_index_max;
333 extern unsigned arm9_dcache_index_inc;
334 #endif
335 
336 #if defined(CPU_ARM9E)
337 void	arm10_tlb_flushID_SE	(u_int);
338 void	arm10_tlb_flushI_SE	(u_int);
339 
340 void	arm10_context_switch	(void);
341 
342 void	arm10_setup		(void);
343 
344 u_int	sheeva_control_ext 		(u_int, u_int);
345 void	sheeva_cpu_sleep		(int);
346 void	sheeva_setttb			(u_int);
347 void	sheeva_dcache_wbinv_range	(vm_offset_t, vm_size_t);
348 void	sheeva_dcache_inv_range		(vm_offset_t, vm_size_t);
349 void	sheeva_dcache_wb_range		(vm_offset_t, vm_size_t);
350 void	sheeva_idcache_wbinv_range	(vm_offset_t, vm_size_t);
351 
352 void	sheeva_l2cache_wbinv_range	(vm_offset_t, vm_size_t);
353 void	sheeva_l2cache_inv_range	(vm_offset_t, vm_size_t);
354 void	sheeva_l2cache_wb_range		(vm_offset_t, vm_size_t);
355 void	sheeva_l2cache_wbinv_all	(void);
356 #endif
357 
358 #if defined(CPU_MV_PJ4B)
359 void	armv6_idcache_wbinv_all		(void);
360 #endif
361 #if defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
362 void	armv7_setttb			(u_int);
363 void	armv7_tlb_flushID		(void);
364 void	armv7_tlb_flushID_SE		(u_int);
365 void	armv7_icache_sync_all		(void);
366 void	armv7_icache_sync_range		(vm_offset_t, vm_size_t);
367 void	armv7_idcache_wbinv_range	(vm_offset_t, vm_size_t);
368 void	armv7_idcache_inv_all		(void);
369 void	armv7_dcache_wbinv_all		(void);
370 void	armv7_idcache_wbinv_all		(void);
371 void	armv7_dcache_wbinv_range	(vm_offset_t, vm_size_t);
372 void	armv7_dcache_inv_range		(vm_offset_t, vm_size_t);
373 void	armv7_dcache_wb_range		(vm_offset_t, vm_size_t);
374 void	armv7_cpu_sleep			(int);
375 void	armv7_setup			(void);
376 void	armv7_context_switch		(void);
377 void	armv7_drain_writebuf		(void);
378 void	armv7_sev			(void);
379 u_int	armv7_auxctrl			(u_int, u_int);
380 
381 void	armadaxp_idcache_wbinv_all	(void);
382 
383 void 	cortexa_setup			(void);
384 #endif
385 #if defined(CPU_MV_PJ4B)
386 void	pj4b_config			(void);
387 void	pj4bv7_setup			(void);
388 #endif
389 
390 #if defined(CPU_ARM1176)
391 void	arm11_tlb_flushID	(void);
392 void	arm11_tlb_flushID_SE	(u_int);
393 void	arm11_tlb_flushI	(void);
394 void	arm11_tlb_flushI_SE	(u_int);
395 void	arm11_tlb_flushD	(void);
396 void	arm11_tlb_flushD_SE	(u_int va);
397 
398 void	arm11_context_switch	(void);
399 
400 void	arm11_drain_writebuf	(void);
401 
402 void	armv6_dcache_wbinv_range	(vm_offset_t, vm_size_t);
403 void	armv6_dcache_inv_range		(vm_offset_t, vm_size_t);
404 void	armv6_dcache_wb_range		(vm_offset_t, vm_size_t);
405 
406 void	armv6_idcache_inv_all		(void);
407 
408 void    arm11x6_setttb                  (u_int);
409 void    arm11x6_idcache_wbinv_all       (void);
410 void    arm11x6_dcache_wbinv_all        (void);
411 void    arm11x6_icache_sync_all         (void);
412 void    arm11x6_flush_prefetchbuf       (void);
413 void    arm11x6_icache_sync_range       (vm_offset_t, vm_size_t);
414 void    arm11x6_idcache_wbinv_range     (vm_offset_t, vm_size_t);
415 void    arm11x6_setup                   (void);
416 void    arm11x6_sleep                   (int);  /* no ref. for errata */
417 #endif
418 
419 #if defined(CPU_ARM9E)
420 void	armv5_ec_setttb(u_int);
421 
422 void	armv5_ec_icache_sync_all(void);
423 void	armv5_ec_icache_sync_range(vm_offset_t, vm_size_t);
424 
425 void	armv5_ec_dcache_wbinv_all(void);
426 void	armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t);
427 void	armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t);
428 void	armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t);
429 
430 void	armv5_ec_idcache_wbinv_all(void);
431 void	armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t);
432 #endif
433 
434 #if defined(CPU_ARM9) || defined(CPU_ARM9E) ||				\
435   defined(CPU_XSCALE_80321) ||						\
436   defined(CPU_FA526) ||							\
437   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||		\
438   defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
439 
440 void	armv4_tlb_flushID	(void);
441 void	armv4_tlb_flushI	(void);
442 void	armv4_tlb_flushD	(void);
443 void	armv4_tlb_flushD_SE	(u_int va);
444 
445 void	armv4_drain_writebuf	(void);
446 void	armv4_idcache_inv_all	(void);
447 #endif
448 
449 #if defined(CPU_XSCALE_80321) ||				\
450   defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) ||	\
451   defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
452 void	xscale_cpwait		(void);
453 
454 void	xscale_cpu_sleep	(int mode);
455 
456 u_int	xscale_control		(u_int clear, u_int bic);
457 
458 void	xscale_setttb		(u_int ttb);
459 
460 void	xscale_tlb_flushID_SE	(u_int va);
461 
462 void	xscale_cache_flushID	(void);
463 void	xscale_cache_flushI	(void);
464 void	xscale_cache_flushD	(void);
465 void	xscale_cache_flushD_SE	(u_int entry);
466 
467 void	xscale_cache_cleanID	(void);
468 void	xscale_cache_cleanD	(void);
469 void	xscale_cache_cleanD_E	(u_int entry);
470 
471 void	xscale_cache_clean_minidata (void);
472 
473 void	xscale_cache_purgeID	(void);
474 void	xscale_cache_purgeID_E	(u_int entry);
475 void	xscale_cache_purgeD	(void);
476 void	xscale_cache_purgeD_E	(u_int entry);
477 
478 void	xscale_cache_syncI	(void);
479 void	xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
480 void	xscale_cache_cleanD_rng	(vm_offset_t start, vm_size_t end);
481 void	xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
482 void	xscale_cache_purgeD_rng	(vm_offset_t start, vm_size_t end);
483 void	xscale_cache_syncI_rng	(vm_offset_t start, vm_size_t end);
484 void	xscale_cache_flushD_rng	(vm_offset_t start, vm_size_t end);
485 
486 void	xscale_context_switch	(void);
487 
488 void	xscale_setup		(void);
489 #endif	/* CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
490 	   CPU_XSCALE_80219 */
491 
492 #ifdef	CPU_XSCALE_81342
493 
494 void	xscalec3_l2cache_purge	(void);
495 void	xscalec3_cache_purgeID	(void);
496 void	xscalec3_cache_purgeD	(void);
497 void	xscalec3_cache_cleanID	(void);
498 void	xscalec3_cache_cleanD	(void);
499 void	xscalec3_cache_syncI	(void);
500 
501 void	xscalec3_cache_purgeID_rng 	(vm_offset_t start, vm_size_t end);
502 void	xscalec3_cache_purgeD_rng	(vm_offset_t start, vm_size_t end);
503 void	xscalec3_cache_cleanID_rng	(vm_offset_t start, vm_size_t end);
504 void	xscalec3_cache_cleanD_rng	(vm_offset_t start, vm_size_t end);
505 void	xscalec3_cache_syncI_rng	(vm_offset_t start, vm_size_t end);
506 
507 void	xscalec3_l2cache_flush_rng	(vm_offset_t, vm_size_t);
508 void	xscalec3_l2cache_clean_rng	(vm_offset_t start, vm_size_t end);
509 void	xscalec3_l2cache_purge_rng	(vm_offset_t start, vm_size_t end);
510 
511 
512 void	xscalec3_setttb		(u_int ttb);
513 void	xscalec3_context_switch	(void);
514 
515 #endif /* CPU_XSCALE_81342 */
516 
517 #define setttb		cpu_setttb
518 #define drain_writebuf	cpu_drain_writebuf
519 
520 /*
521  * Macros for manipulating CPU interrupts
522  */
523 static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__));
524 
525 static __inline u_int32_t
526 __set_cpsr_c(u_int bic, u_int eor)
527 {
528 	u_int32_t	tmp, ret;
529 
530 	__asm __volatile(
531 		"mrs     %0, cpsr\n"	/* Get the CPSR */
532 		"bic	 %1, %0, %2\n"	/* Clear bits */
533 		"eor	 %1, %1, %3\n"	/* XOR bits */
534 		"msr     cpsr_c, %1\n"	/* Set the control field of CPSR */
535 	: "=&r" (ret), "=&r" (tmp)
536 	: "r" (bic), "r" (eor) : "memory");
537 
538 	return ret;
539 }
540 
541 #define	ARM_CPSR_F32	(1 << 6)	/* FIQ disable */
542 #define	ARM_CPSR_I32	(1 << 7)	/* IRQ disable */
543 
544 #define disable_interrupts(mask)					\
545 	(__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32),		\
546 		      (mask) & (ARM_CPSR_I32 | ARM_CPSR_F32)))
547 
548 #define enable_interrupts(mask)						\
549 	(__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), 0))
550 
551 #define restore_interrupts(old_cpsr)					\
552 	(__set_cpsr_c((ARM_CPSR_I32 | ARM_CPSR_F32),			\
553 		      (old_cpsr) & (ARM_CPSR_I32 | ARM_CPSR_F32)))
554 
555 static __inline register_t
556 intr_disable(void)
557 {
558 	register_t s;
559 
560 	s = disable_interrupts(ARM_CPSR_I32 | ARM_CPSR_F32);
561 	return (s);
562 }
563 
564 static __inline void
565 intr_restore(register_t s)
566 {
567 
568 	restore_interrupts(s);
569 }
570 
571 /* Functions to manipulate the CPSR. */
572 u_int	SetCPSR(u_int bic, u_int eor);
573 u_int	GetCPSR(void);
574 
575 /*
576  * Functions to manipulate cpu r13
577  * (in arm/arm32/setstack.S)
578  */
579 
580 void set_stackptr	(u_int mode, u_int address);
581 u_int get_stackptr	(u_int mode);
582 
583 /*
584  * Miscellany
585  */
586 
587 int get_pc_str_offset	(void);
588 
589 /*
590  * CPU functions from locore.S
591  */
592 
593 void cpu_reset		(void) __attribute__((__noreturn__));
594 
595 /*
596  * Cache info variables.
597  */
598 
599 /* PRIMARY CACHE VARIABLES */
600 extern int	arm_picache_size;
601 extern int	arm_picache_line_size;
602 extern int	arm_picache_ways;
603 
604 extern int	arm_pdcache_size;	/* and unified */
605 extern int	arm_pdcache_line_size;
606 extern int	arm_pdcache_ways;
607 
608 extern int	arm_pcache_type;
609 extern int	arm_pcache_unified;
610 
611 extern int	arm_dcache_align;
612 extern int	arm_dcache_align_mask;
613 
614 extern u_int	arm_cache_level;
615 extern u_int	arm_cache_loc;
616 extern u_int	arm_cache_type[14];
617 
618 #endif	/* _KERNEL */
619 #endif	/* _MACHINE_CPUFUNC_H_ */
620 
621 /* End of cpufunc.h */
622