1 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright (c) 1997 Mark Brinicombe. 7 * Copyright (c) 1997 Causality Limited 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by Causality Limited. 21 * 4. The name of Causality Limited may not be used to endorse or promote 22 * products derived from this software without specific prior written 23 * permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 26 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 28 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 30 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * RiscBSD kernel project 38 * 39 * cpufunc.h 40 * 41 * Prototypes for cpu, mmu and tlb related functions. 42 * 43 * $FreeBSD$ 44 */ 45 46 #ifndef _MACHINE_CPUFUNC_H_ 47 #define _MACHINE_CPUFUNC_H_ 48 49 #ifdef _KERNEL 50 51 #include <sys/types.h> 52 #include <machine/armreg.h> 53 54 static __inline void 55 breakpoint(void) 56 { 57 __asm("udf 0xffff"); 58 } 59 60 struct cpu_functions { 61 62 /* CPU functions */ 63 #if __ARM_ARCH < 6 64 void (*cf_cpwait) (void); 65 66 /* MMU functions */ 67 68 u_int (*cf_control) (u_int bic, u_int eor); 69 void (*cf_setttb) (u_int ttb); 70 71 /* TLB functions */ 72 73 void (*cf_tlb_flushID) (void); 74 void (*cf_tlb_flushID_SE) (u_int va); 75 void (*cf_tlb_flushD) (void); 76 void (*cf_tlb_flushD_SE) (u_int va); 77 78 /* 79 * Cache operations: 80 * 81 * We define the following primitives: 82 * 83 * icache_sync_range Synchronize I-cache range 84 * 85 * dcache_wbinv_all Write-back and Invalidate D-cache 86 * dcache_wbinv_range Write-back and Invalidate D-cache range 87 * dcache_inv_range Invalidate D-cache range 88 * dcache_wb_range Write-back D-cache range 89 * 90 * idcache_wbinv_all Write-back and Invalidate D-cache, 91 * Invalidate I-cache 92 * idcache_wbinv_range Write-back and Invalidate D-cache, 93 * Invalidate I-cache range 94 * 95 * Note that the ARM term for "write-back" is "clean". We use 96 * the term "write-back" since it's a more common way to describe 97 * the operation. 98 * 99 * There are some rules that must be followed: 100 * 101 * ID-cache Invalidate All: 102 * Unlike other functions, this one must never write back. 103 * It is used to intialize the MMU when it is in an unknown 104 * state (such as when it may have lines tagged as valid 105 * that belong to a previous set of mappings). 106 * 107 * I-cache Sync range: 108 * The goal is to synchronize the instruction stream, 109 * so you may beed to write-back dirty D-cache blocks 110 * first. If a range is requested, and you can't 111 * synchronize just a range, you have to hit the whole 112 * thing. 113 * 114 * D-cache Write-Back and Invalidate range: 115 * If you can't WB-Inv a range, you must WB-Inv the 116 * entire D-cache. 117 * 118 * D-cache Invalidate: 119 * If you can't Inv the D-cache, you must Write-Back 120 * and Invalidate. Code that uses this operation 121 * MUST NOT assume that the D-cache will not be written 122 * back to memory. 123 * 124 * D-cache Write-Back: 125 * If you can't Write-back without doing an Inv, 126 * that's fine. Then treat this as a WB-Inv. 127 * Skipping the invalidate is merely an optimization. 128 * 129 * All operations: 130 * Valid virtual addresses must be passed to each 131 * cache operation. 132 */ 133 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 134 135 void (*cf_dcache_wbinv_all) (void); 136 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 137 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 138 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 139 140 void (*cf_idcache_inv_all) (void); 141 void (*cf_idcache_wbinv_all) (void); 142 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 143 #endif 144 void (*cf_l2cache_wbinv_all) (void); 145 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 146 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 147 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 148 void (*cf_l2cache_drain_writebuf) (void); 149 150 /* Other functions */ 151 152 #if __ARM_ARCH < 6 153 void (*cf_drain_writebuf) (void); 154 #endif 155 156 void (*cf_sleep) (int mode); 157 158 #if __ARM_ARCH < 6 159 /* Soft functions */ 160 161 void (*cf_context_switch) (void); 162 #endif 163 164 void (*cf_setup) (void); 165 }; 166 167 extern struct cpu_functions cpufuncs; 168 extern u_int cputype; 169 170 #if __ARM_ARCH < 6 171 #define cpu_cpwait() cpufuncs.cf_cpwait() 172 173 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 174 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 175 176 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 177 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 178 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 179 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 180 181 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 182 183 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 184 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 185 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 186 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 187 188 #define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all() 189 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 190 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 191 #endif 192 193 #define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 194 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 195 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 196 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 197 #define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf() 198 199 #if __ARM_ARCH < 6 200 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 201 #endif 202 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 203 204 #define cpu_setup() cpufuncs.cf_setup() 205 206 int set_cpufuncs (void); 207 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 208 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 209 210 void cpufunc_nullop (void); 211 u_int cpu_ident (void); 212 u_int cpufunc_control (u_int clear, u_int bic); 213 void cpu_domains (u_int domains); 214 u_int cpu_faultstatus (void); 215 u_int cpu_faultaddress (void); 216 u_int cpu_get_control (void); 217 u_int cpu_pfr (int); 218 219 #if defined(CPU_FA526) 220 void fa526_setup (void); 221 void fa526_setttb (u_int ttb); 222 void fa526_context_switch (void); 223 void fa526_cpu_sleep (int); 224 void fa526_tlb_flushID_SE (u_int); 225 226 void fa526_icache_sync_range(vm_offset_t start, vm_size_t end); 227 void fa526_dcache_wbinv_all (void); 228 void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end); 229 void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end); 230 void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end); 231 void fa526_idcache_wbinv_all(void); 232 void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end); 233 #endif 234 235 236 #if defined(CPU_ARM9) || defined(CPU_ARM9E) 237 void arm9_setttb (u_int); 238 void arm9_tlb_flushID_SE (u_int va); 239 void arm9_context_switch (void); 240 #endif 241 242 #if defined(CPU_ARM9) 243 void arm9_icache_sync_range (vm_offset_t, vm_size_t); 244 245 void arm9_dcache_wbinv_all (void); 246 void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); 247 void arm9_dcache_inv_range (vm_offset_t, vm_size_t); 248 void arm9_dcache_wb_range (vm_offset_t, vm_size_t); 249 250 void arm9_idcache_wbinv_all (void); 251 void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); 252 253 void arm9_setup (void); 254 255 extern unsigned arm9_dcache_sets_max; 256 extern unsigned arm9_dcache_sets_inc; 257 extern unsigned arm9_dcache_index_max; 258 extern unsigned arm9_dcache_index_inc; 259 #endif 260 261 #if defined(CPU_ARM9E) 262 void arm10_setup (void); 263 264 u_int sheeva_control_ext (u_int, u_int); 265 void sheeva_cpu_sleep (int); 266 void sheeva_setttb (u_int); 267 void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); 268 void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); 269 void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); 270 void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); 271 272 void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); 273 void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); 274 void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); 275 void sheeva_l2cache_wbinv_all (void); 276 #endif 277 278 #if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) 279 void armv7_cpu_sleep (int); 280 void armv7_setup (void); 281 282 void cortexa_setup (void); 283 #endif 284 #if defined(CPU_MV_PJ4B) 285 void pj4b_config (void); 286 void pj4bv7_setup (void); 287 #endif 288 289 #if defined(CPU_ARM1176) 290 void arm11x6_setup (void); 291 void arm11x6_sleep (int); /* no ref. for errata */ 292 #endif 293 294 #if defined(CPU_ARM9E) 295 void armv5_ec_setttb(u_int); 296 297 void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); 298 299 void armv5_ec_dcache_wbinv_all(void); 300 void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); 301 void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); 302 void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); 303 304 void armv5_ec_idcache_wbinv_all(void); 305 void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); 306 #endif 307 308 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 309 defined(CPU_FA526) || \ 310 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_81342) 311 312 void armv4_tlb_flushID (void); 313 void armv4_tlb_flushD (void); 314 void armv4_tlb_flushD_SE (u_int va); 315 316 void armv4_drain_writebuf (void); 317 void armv4_idcache_inv_all (void); 318 #endif 319 320 #if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_81342) 321 void xscale_cpwait (void); 322 323 void xscale_cpu_sleep (int mode); 324 325 u_int xscale_control (u_int clear, u_int bic); 326 327 void xscale_setttb (u_int ttb); 328 329 void xscale_tlb_flushID_SE (u_int va); 330 331 void xscale_cache_flushID (void); 332 void xscale_cache_flushI (void); 333 void xscale_cache_flushD (void); 334 void xscale_cache_flushD_SE (u_int entry); 335 336 void xscale_cache_cleanID (void); 337 void xscale_cache_cleanD (void); 338 void xscale_cache_cleanD_E (u_int entry); 339 340 void xscale_cache_clean_minidata (void); 341 342 void xscale_cache_purgeID (void); 343 void xscale_cache_purgeID_E (u_int entry); 344 void xscale_cache_purgeD (void); 345 void xscale_cache_purgeD_E (u_int entry); 346 347 void xscale_cache_syncI (void); 348 void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 349 void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 350 void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 351 void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 352 void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 353 void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 354 355 void xscale_context_switch (void); 356 357 void xscale_setup (void); 358 #endif /* CPU_XSCALE_PXA2X0 */ 359 360 #ifdef CPU_XSCALE_81342 361 362 void xscalec3_l2cache_purge (void); 363 void xscalec3_cache_purgeID (void); 364 void xscalec3_cache_purgeD (void); 365 void xscalec3_cache_cleanID (void); 366 void xscalec3_cache_cleanD (void); 367 void xscalec3_cache_syncI (void); 368 369 void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 370 void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 371 void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 372 void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 373 void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end); 374 375 void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t); 376 void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end); 377 void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end); 378 379 380 void xscalec3_setttb (u_int ttb); 381 void xscalec3_context_switch (void); 382 383 #endif /* CPU_XSCALE_81342 */ 384 385 /* 386 * Macros for manipulating CPU interrupts 387 */ 388 #if __ARM_ARCH < 6 389 #define __ARM_INTR_BITS (PSR_I | PSR_F) 390 #else 391 #define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A) 392 #endif 393 394 static __inline uint32_t 395 __set_cpsr(uint32_t bic, uint32_t eor) 396 { 397 uint32_t tmp, ret; 398 399 __asm __volatile( 400 "mrs %0, cpsr\n" /* Get the CPSR */ 401 "bic %1, %0, %2\n" /* Clear bits */ 402 "eor %1, %1, %3\n" /* XOR bits */ 403 "msr cpsr_xc, %1\n" /* Set the CPSR */ 404 : "=&r" (ret), "=&r" (tmp) 405 : "r" (bic), "r" (eor) : "memory"); 406 407 return ret; 408 } 409 410 static __inline uint32_t 411 disable_interrupts(uint32_t mask) 412 { 413 414 return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS)); 415 } 416 417 static __inline uint32_t 418 enable_interrupts(uint32_t mask) 419 { 420 421 return (__set_cpsr(mask & __ARM_INTR_BITS, 0)); 422 } 423 424 static __inline uint32_t 425 restore_interrupts(uint32_t old_cpsr) 426 { 427 428 return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS)); 429 } 430 431 static __inline register_t 432 intr_disable(void) 433 { 434 435 return (disable_interrupts(PSR_I | PSR_F)); 436 } 437 438 static __inline void 439 intr_restore(register_t s) 440 { 441 442 restore_interrupts(s); 443 } 444 #undef __ARM_INTR_BITS 445 446 /* 447 * Functions to manipulate cpu r13 448 * (in arm/arm32/setstack.S) 449 */ 450 451 void set_stackptr (u_int mode, u_int address); 452 u_int get_stackptr (u_int mode); 453 454 /* 455 * CPU functions from locore.S 456 */ 457 458 void cpu_reset (void) __attribute__((__noreturn__)); 459 460 /* 461 * Cache info variables. 462 */ 463 464 /* PRIMARY CACHE VARIABLES */ 465 extern int arm_picache_size; 466 extern int arm_picache_line_size; 467 extern int arm_picache_ways; 468 469 extern int arm_pdcache_size; /* and unified */ 470 extern int arm_pdcache_line_size; 471 extern int arm_pdcache_ways; 472 473 extern int arm_pcache_type; 474 extern int arm_pcache_unified; 475 476 extern int arm_dcache_align; 477 extern int arm_dcache_align_mask; 478 479 extern u_int arm_cache_level; 480 extern u_int arm_cache_loc; 481 extern u_int arm_cache_type[14]; 482 483 #else /* !_KERNEL */ 484 485 static __inline void 486 breakpoint(void) 487 { 488 489 /* 490 * This matches the instruction used by GDB for software 491 * breakpoints. 492 */ 493 __asm("udf 0xfdee"); 494 } 495 496 #endif /* _KERNEL */ 497 #endif /* _MACHINE_CPUFUNC_H_ */ 498 499 /* End of cpufunc.h */ 500