1 /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 Mark Brinicombe. 5 * Copyright (c) 1997 Causality Limited 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Causality Limited. 19 * 4. The name of Causality Limited may not be used to endorse or promote 20 * products derived from this software without specific prior written 21 * permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 24 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 26 * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * RiscBSD kernel project 36 * 37 * cpufunc.h 38 * 39 * Prototypes for cpu, mmu and tlb related functions. 40 * 41 * $FreeBSD$ 42 */ 43 44 #ifndef _MACHINE_CPUFUNC_H_ 45 #define _MACHINE_CPUFUNC_H_ 46 47 #ifdef _KERNEL 48 49 #include <sys/types.h> 50 #include <machine/armreg.h> 51 #include <machine/cpuconf.h> 52 53 static __inline void 54 breakpoint(void) 55 { 56 __asm(".word 0xe7ffffff"); 57 } 58 59 struct cpu_functions { 60 61 /* CPU functions */ 62 #if __ARM_ARCH < 6 63 void (*cf_cpwait) (void); 64 #endif 65 66 /* MMU functions */ 67 68 u_int (*cf_control) (u_int bic, u_int eor); 69 void (*cf_setttb) (u_int ttb); 70 71 #if __ARM_ARCH < 6 72 /* TLB functions */ 73 74 void (*cf_tlb_flushID) (void); 75 void (*cf_tlb_flushID_SE) (u_int va); 76 void (*cf_tlb_flushD) (void); 77 void (*cf_tlb_flushD_SE) (u_int va); 78 79 /* 80 * Cache operations: 81 * 82 * We define the following primitives: 83 * 84 * icache_sync_range Synchronize I-cache range 85 * 86 * dcache_wbinv_all Write-back and Invalidate D-cache 87 * dcache_wbinv_range Write-back and Invalidate D-cache range 88 * dcache_inv_range Invalidate D-cache range 89 * dcache_wb_range Write-back D-cache range 90 * 91 * idcache_wbinv_all Write-back and Invalidate D-cache, 92 * Invalidate I-cache 93 * idcache_wbinv_range Write-back and Invalidate D-cache, 94 * Invalidate I-cache range 95 * 96 * Note that the ARM term for "write-back" is "clean". We use 97 * the term "write-back" since it's a more common way to describe 98 * the operation. 99 * 100 * There are some rules that must be followed: 101 * 102 * ID-cache Invalidate All: 103 * Unlike other functions, this one must never write back. 104 * It is used to intialize the MMU when it is in an unknown 105 * state (such as when it may have lines tagged as valid 106 * that belong to a previous set of mappings). 107 * 108 * I-cache Sync range: 109 * The goal is to synchronize the instruction stream, 110 * so you may beed to write-back dirty D-cache blocks 111 * first. If a range is requested, and you can't 112 * synchronize just a range, you have to hit the whole 113 * thing. 114 * 115 * D-cache Write-Back and Invalidate range: 116 * If you can't WB-Inv a range, you must WB-Inv the 117 * entire D-cache. 118 * 119 * D-cache Invalidate: 120 * If you can't Inv the D-cache, you must Write-Back 121 * and Invalidate. Code that uses this operation 122 * MUST NOT assume that the D-cache will not be written 123 * back to memory. 124 * 125 * D-cache Write-Back: 126 * If you can't Write-back without doing an Inv, 127 * that's fine. Then treat this as a WB-Inv. 128 * Skipping the invalidate is merely an optimization. 129 * 130 * All operations: 131 * Valid virtual addresses must be passed to each 132 * cache operation. 133 */ 134 void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 135 136 void (*cf_dcache_wbinv_all) (void); 137 void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 138 void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 139 void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 140 141 void (*cf_idcache_inv_all) (void); 142 void (*cf_idcache_wbinv_all) (void); 143 void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 144 #endif 145 void (*cf_l2cache_wbinv_all) (void); 146 void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 147 void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 148 void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 149 void (*cf_l2cache_drain_writebuf) (void); 150 151 /* Other functions */ 152 153 void (*cf_drain_writebuf) (void); 154 155 void (*cf_sleep) (int mode); 156 157 #if __ARM_ARCH < 6 158 /* Soft functions */ 159 160 void (*cf_context_switch) (void); 161 #endif 162 163 void (*cf_setup) (void); 164 }; 165 166 extern struct cpu_functions cpufuncs; 167 extern u_int cputype; 168 169 #if __ARM_ARCH < 6 170 #define cpu_cpwait() cpufuncs.cf_cpwait() 171 #endif 172 173 #define cpu_control(c, e) cpufuncs.cf_control(c, e) 174 #if __ARM_ARCH < 6 175 #define cpu_setttb(t) cpufuncs.cf_setttb(t) 176 177 #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 178 #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 179 #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 180 #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 181 182 #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 183 184 #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 185 #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 186 #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 187 #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 188 189 #define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all() 190 #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 191 #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 192 #endif 193 #define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 194 #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 195 #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 196 #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 197 #define cpu_l2cache_drain_writebuf() cpufuncs.cf_l2cache_drain_writebuf() 198 199 #if __ARM_ARCH < 6 200 #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 201 #endif 202 #define cpu_sleep(m) cpufuncs.cf_sleep(m) 203 204 #define cpu_setup() cpufuncs.cf_setup() 205 206 int set_cpufuncs (void); 207 #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 208 #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 209 210 void cpufunc_nullop (void); 211 u_int cpu_ident (void); 212 u_int cpufunc_control (u_int clear, u_int bic); 213 void cpu_domains (u_int domains); 214 u_int cpu_faultstatus (void); 215 u_int cpu_faultaddress (void); 216 u_int cpu_get_control (void); 217 u_int cpu_pfr (int); 218 219 #if defined(CPU_FA526) 220 void fa526_setup (void); 221 void fa526_setttb (u_int ttb); 222 void fa526_context_switch (void); 223 void fa526_cpu_sleep (int); 224 void fa526_tlb_flushID_SE (u_int); 225 226 void fa526_icache_sync_range(vm_offset_t start, vm_size_t end); 227 void fa526_dcache_wbinv_all (void); 228 void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end); 229 void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end); 230 void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end); 231 void fa526_idcache_wbinv_all(void); 232 void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end); 233 #endif 234 235 236 #if defined(CPU_ARM9) || defined(CPU_ARM9E) 237 void arm9_setttb (u_int); 238 void arm9_tlb_flushID_SE (u_int va); 239 void arm9_context_switch (void); 240 #endif 241 242 #if defined(CPU_ARM9) 243 void arm9_icache_sync_range (vm_offset_t, vm_size_t); 244 245 void arm9_dcache_wbinv_all (void); 246 void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); 247 void arm9_dcache_inv_range (vm_offset_t, vm_size_t); 248 void arm9_dcache_wb_range (vm_offset_t, vm_size_t); 249 250 void arm9_idcache_wbinv_all (void); 251 void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); 252 253 void arm9_setup (void); 254 255 extern unsigned arm9_dcache_sets_max; 256 extern unsigned arm9_dcache_sets_inc; 257 extern unsigned arm9_dcache_index_max; 258 extern unsigned arm9_dcache_index_inc; 259 #endif 260 261 #if defined(CPU_ARM9E) 262 void arm10_setup (void); 263 264 u_int sheeva_control_ext (u_int, u_int); 265 void sheeva_cpu_sleep (int); 266 void sheeva_setttb (u_int); 267 void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); 268 void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); 269 void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); 270 void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); 271 272 void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); 273 void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); 274 void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); 275 void sheeva_l2cache_wbinv_all (void); 276 #endif 277 278 #if defined(CPU_MV_PJ4B) 279 void armv6_idcache_wbinv_all (void); 280 #endif 281 #if defined(CPU_CORTEXA8) || defined(CPU_CORTEXA_MP) || \ 282 defined(CPU_MV_PJ4B) || defined(CPU_KRAIT) 283 void armv7_setttb (u_int); 284 void armv7_idcache_wbinv_all (void); 285 void armv7_cpu_sleep (int); 286 void armv7_setup (void); 287 void armv7_drain_writebuf (void); 288 void armv7_sev (void); 289 290 void armadaxp_idcache_wbinv_all (void); 291 292 void cortexa_setup (void); 293 #endif 294 #if defined(CPU_MV_PJ4B) 295 void pj4b_config (void); 296 void pj4bv7_setup (void); 297 #endif 298 299 #if defined(CPU_ARM1176) 300 void arm11_drain_writebuf (void); 301 302 void arm11x6_setttb (u_int); 303 void arm11x6_setup (void); 304 void arm11x6_sleep (int); /* no ref. for errata */ 305 #endif 306 307 #if defined(CPU_ARM9E) 308 void armv5_ec_setttb(u_int); 309 310 void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); 311 312 void armv5_ec_dcache_wbinv_all(void); 313 void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); 314 void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); 315 void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); 316 317 void armv5_ec_idcache_wbinv_all(void); 318 void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); 319 #endif 320 321 #if defined(CPU_ARM9) || defined(CPU_ARM9E) || \ 322 defined(CPU_FA526) || \ 323 defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 324 defined(CPU_XSCALE_81342) 325 326 void armv4_tlb_flushID (void); 327 void armv4_tlb_flushD (void); 328 void armv4_tlb_flushD_SE (u_int va); 329 330 void armv4_drain_writebuf (void); 331 void armv4_idcache_inv_all (void); 332 #endif 333 334 #if defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 335 defined(CPU_XSCALE_81342) 336 void xscale_cpwait (void); 337 338 void xscale_cpu_sleep (int mode); 339 340 u_int xscale_control (u_int clear, u_int bic); 341 342 void xscale_setttb (u_int ttb); 343 344 void xscale_tlb_flushID_SE (u_int va); 345 346 void xscale_cache_flushID (void); 347 void xscale_cache_flushI (void); 348 void xscale_cache_flushD (void); 349 void xscale_cache_flushD_SE (u_int entry); 350 351 void xscale_cache_cleanID (void); 352 void xscale_cache_cleanD (void); 353 void xscale_cache_cleanD_E (u_int entry); 354 355 void xscale_cache_clean_minidata (void); 356 357 void xscale_cache_purgeID (void); 358 void xscale_cache_purgeID_E (u_int entry); 359 void xscale_cache_purgeD (void); 360 void xscale_cache_purgeD_E (u_int entry); 361 362 void xscale_cache_syncI (void); 363 void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 364 void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 365 void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 366 void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 367 void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 368 void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 369 370 void xscale_context_switch (void); 371 372 void xscale_setup (void); 373 #endif /* CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */ 374 375 #ifdef CPU_XSCALE_81342 376 377 void xscalec3_l2cache_purge (void); 378 void xscalec3_cache_purgeID (void); 379 void xscalec3_cache_purgeD (void); 380 void xscalec3_cache_cleanID (void); 381 void xscalec3_cache_cleanD (void); 382 void xscalec3_cache_syncI (void); 383 384 void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 385 void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 386 void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 387 void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 388 void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end); 389 390 void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t); 391 void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end); 392 void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end); 393 394 395 void xscalec3_setttb (u_int ttb); 396 void xscalec3_context_switch (void); 397 398 #endif /* CPU_XSCALE_81342 */ 399 400 /* 401 * Macros for manipulating CPU interrupts 402 */ 403 #if __ARM_ARCH < 6 404 #define __ARM_INTR_BITS (PSR_I | PSR_F) 405 #else 406 #define __ARM_INTR_BITS (PSR_I | PSR_F | PSR_A) 407 #endif 408 409 static __inline uint32_t 410 __set_cpsr(uint32_t bic, uint32_t eor) 411 { 412 uint32_t tmp, ret; 413 414 __asm __volatile( 415 "mrs %0, cpsr\n" /* Get the CPSR */ 416 "bic %1, %0, %2\n" /* Clear bits */ 417 "eor %1, %1, %3\n" /* XOR bits */ 418 "msr cpsr_xc, %1\n" /* Set the CPSR */ 419 : "=&r" (ret), "=&r" (tmp) 420 : "r" (bic), "r" (eor) : "memory"); 421 422 return ret; 423 } 424 425 static __inline uint32_t 426 disable_interrupts(uint32_t mask) 427 { 428 429 return (__set_cpsr(mask & __ARM_INTR_BITS, mask & __ARM_INTR_BITS)); 430 } 431 432 static __inline uint32_t 433 enable_interrupts(uint32_t mask) 434 { 435 436 return (__set_cpsr(mask & __ARM_INTR_BITS, 0)); 437 } 438 439 static __inline uint32_t 440 restore_interrupts(uint32_t old_cpsr) 441 { 442 443 return (__set_cpsr(__ARM_INTR_BITS, old_cpsr & __ARM_INTR_BITS)); 444 } 445 446 static __inline register_t 447 intr_disable(void) 448 { 449 450 return (disable_interrupts(PSR_I | PSR_F)); 451 } 452 453 static __inline void 454 intr_restore(register_t s) 455 { 456 457 restore_interrupts(s); 458 } 459 #undef __ARM_INTR_BITS 460 461 /* 462 * Functions to manipulate cpu r13 463 * (in arm/arm32/setstack.S) 464 */ 465 466 void set_stackptr (u_int mode, u_int address); 467 u_int get_stackptr (u_int mode); 468 469 /* 470 * Miscellany 471 */ 472 473 int get_pc_str_offset (void); 474 475 /* 476 * CPU functions from locore.S 477 */ 478 479 void cpu_reset (void) __attribute__((__noreturn__)); 480 481 /* 482 * Cache info variables. 483 */ 484 485 /* PRIMARY CACHE VARIABLES */ 486 extern int arm_picache_size; 487 extern int arm_picache_line_size; 488 extern int arm_picache_ways; 489 490 extern int arm_pdcache_size; /* and unified */ 491 extern int arm_pdcache_line_size; 492 extern int arm_pdcache_ways; 493 494 extern int arm_pcache_type; 495 extern int arm_pcache_unified; 496 497 extern int arm_dcache_align; 498 extern int arm_dcache_align_mask; 499 500 extern u_int arm_cache_level; 501 extern u_int arm_cache_loc; 502 extern u_int arm_cache_type[14]; 503 504 #endif /* _KERNEL */ 505 #endif /* _MACHINE_CPUFUNC_H_ */ 506 507 /* End of cpufunc.h */ 508