16fc729afSOlivier Houchard /* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */ 26fc729afSOlivier Houchard 3d8315c79SWarner Losh /*- 46fc729afSOlivier Houchard * Copyright (c) 1997 Mark Brinicombe. 56fc729afSOlivier Houchard * Copyright (c) 1997 Causality Limited 66fc729afSOlivier Houchard * All rights reserved. 76fc729afSOlivier Houchard * 86fc729afSOlivier Houchard * Redistribution and use in source and binary forms, with or without 96fc729afSOlivier Houchard * modification, are permitted provided that the following conditions 106fc729afSOlivier Houchard * are met: 116fc729afSOlivier Houchard * 1. Redistributions of source code must retain the above copyright 126fc729afSOlivier Houchard * notice, this list of conditions and the following disclaimer. 136fc729afSOlivier Houchard * 2. Redistributions in binary form must reproduce the above copyright 146fc729afSOlivier Houchard * notice, this list of conditions and the following disclaimer in the 156fc729afSOlivier Houchard * documentation and/or other materials provided with the distribution. 166fc729afSOlivier Houchard * 3. All advertising materials mentioning features or use of this software 176fc729afSOlivier Houchard * must display the following acknowledgement: 186fc729afSOlivier Houchard * This product includes software developed by Causality Limited. 196fc729afSOlivier Houchard * 4. The name of Causality Limited may not be used to endorse or promote 206fc729afSOlivier Houchard * products derived from this software without specific prior written 216fc729afSOlivier Houchard * permission. 226fc729afSOlivier Houchard * 236fc729afSOlivier Houchard * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS 246fc729afSOlivier Houchard * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 256fc729afSOlivier Houchard * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 266fc729afSOlivier Houchard * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT, 276fc729afSOlivier Houchard * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 286fc729afSOlivier Houchard * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 296fc729afSOlivier Houchard * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 306fc729afSOlivier Houchard * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 316fc729afSOlivier Houchard * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 326fc729afSOlivier Houchard * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 336fc729afSOlivier Houchard * SUCH DAMAGE. 346fc729afSOlivier Houchard * 356fc729afSOlivier Houchard * RiscBSD kernel project 366fc729afSOlivier Houchard * 376fc729afSOlivier Houchard * cpufunc.h 386fc729afSOlivier Houchard * 396fc729afSOlivier Houchard * Prototypes for cpu, mmu and tlb related functions. 406fc729afSOlivier Houchard * 416fc729afSOlivier Houchard * $FreeBSD$ 426fc729afSOlivier Houchard */ 436fc729afSOlivier Houchard 446fc729afSOlivier Houchard #ifndef _MACHINE_CPUFUNC_H_ 456fc729afSOlivier Houchard #define _MACHINE_CPUFUNC_H_ 466fc729afSOlivier Houchard 476fc729afSOlivier Houchard #ifdef _KERNEL 486fc729afSOlivier Houchard 496fc729afSOlivier Houchard #include <sys/types.h> 506fc729afSOlivier Houchard #include <machine/cpuconf.h> 514628245bSOlivier Houchard #include <machine/katelib.h> /* For in[bwl] and out[bwl] */ 526fc729afSOlivier Houchard 534628245bSOlivier Houchard static __inline void 544628245bSOlivier Houchard breakpoint(void) 554628245bSOlivier Houchard { 563488a2f7SOlivier Houchard __asm(".word 0xe7ffffff"); 574628245bSOlivier Houchard } 58be687a0dSOlivier Houchard 596fc729afSOlivier Houchard struct cpu_functions { 606fc729afSOlivier Houchard 616fc729afSOlivier Houchard /* CPU functions */ 626fc729afSOlivier Houchard 636fc729afSOlivier Houchard u_int (*cf_id) (void); 646fc729afSOlivier Houchard void (*cf_cpwait) (void); 656fc729afSOlivier Houchard 666fc729afSOlivier Houchard /* MMU functions */ 676fc729afSOlivier Houchard 686fc729afSOlivier Houchard u_int (*cf_control) (u_int bic, u_int eor); 696fc729afSOlivier Houchard void (*cf_domains) (u_int domains); 706fc729afSOlivier Houchard void (*cf_setttb) (u_int ttb); 716fc729afSOlivier Houchard u_int (*cf_faultstatus) (void); 726fc729afSOlivier Houchard u_int (*cf_faultaddress) (void); 736fc729afSOlivier Houchard 746fc729afSOlivier Houchard /* TLB functions */ 756fc729afSOlivier Houchard 766fc729afSOlivier Houchard void (*cf_tlb_flushID) (void); 776fc729afSOlivier Houchard void (*cf_tlb_flushID_SE) (u_int va); 786fc729afSOlivier Houchard void (*cf_tlb_flushI) (void); 796fc729afSOlivier Houchard void (*cf_tlb_flushI_SE) (u_int va); 806fc729afSOlivier Houchard void (*cf_tlb_flushD) (void); 816fc729afSOlivier Houchard void (*cf_tlb_flushD_SE) (u_int va); 826fc729afSOlivier Houchard 836fc729afSOlivier Houchard /* 846fc729afSOlivier Houchard * Cache operations: 856fc729afSOlivier Houchard * 866fc729afSOlivier Houchard * We define the following primitives: 876fc729afSOlivier Houchard * 886fc729afSOlivier Houchard * icache_sync_all Synchronize I-cache 896fc729afSOlivier Houchard * icache_sync_range Synchronize I-cache range 906fc729afSOlivier Houchard * 916fc729afSOlivier Houchard * dcache_wbinv_all Write-back and Invalidate D-cache 926fc729afSOlivier Houchard * dcache_wbinv_range Write-back and Invalidate D-cache range 936fc729afSOlivier Houchard * dcache_inv_range Invalidate D-cache range 946fc729afSOlivier Houchard * dcache_wb_range Write-back D-cache range 956fc729afSOlivier Houchard * 966fc729afSOlivier Houchard * idcache_wbinv_all Write-back and Invalidate D-cache, 976fc729afSOlivier Houchard * Invalidate I-cache 986fc729afSOlivier Houchard * idcache_wbinv_range Write-back and Invalidate D-cache, 996fc729afSOlivier Houchard * Invalidate I-cache range 1006fc729afSOlivier Houchard * 1016fc729afSOlivier Houchard * Note that the ARM term for "write-back" is "clean". We use 1026fc729afSOlivier Houchard * the term "write-back" since it's a more common way to describe 1036fc729afSOlivier Houchard * the operation. 1046fc729afSOlivier Houchard * 1056fc729afSOlivier Houchard * There are some rules that must be followed: 1066fc729afSOlivier Houchard * 1076fc729afSOlivier Houchard * I-cache Synch (all or range): 1086fc729afSOlivier Houchard * The goal is to synchronize the instruction stream, 1096fc729afSOlivier Houchard * so you may beed to write-back dirty D-cache blocks 1106fc729afSOlivier Houchard * first. If a range is requested, and you can't 1116fc729afSOlivier Houchard * synchronize just a range, you have to hit the whole 1126fc729afSOlivier Houchard * thing. 1136fc729afSOlivier Houchard * 1146fc729afSOlivier Houchard * D-cache Write-Back and Invalidate range: 1156fc729afSOlivier Houchard * If you can't WB-Inv a range, you must WB-Inv the 1166fc729afSOlivier Houchard * entire D-cache. 1176fc729afSOlivier Houchard * 1186fc729afSOlivier Houchard * D-cache Invalidate: 1196fc729afSOlivier Houchard * If you can't Inv the D-cache, you must Write-Back 1206fc729afSOlivier Houchard * and Invalidate. Code that uses this operation 1216fc729afSOlivier Houchard * MUST NOT assume that the D-cache will not be written 1226fc729afSOlivier Houchard * back to memory. 1236fc729afSOlivier Houchard * 1246fc729afSOlivier Houchard * D-cache Write-Back: 1256fc729afSOlivier Houchard * If you can't Write-back without doing an Inv, 1266fc729afSOlivier Houchard * that's fine. Then treat this as a WB-Inv. 1276fc729afSOlivier Houchard * Skipping the invalidate is merely an optimization. 1286fc729afSOlivier Houchard * 1296fc729afSOlivier Houchard * All operations: 1306fc729afSOlivier Houchard * Valid virtual addresses must be passed to each 1316fc729afSOlivier Houchard * cache operation. 1326fc729afSOlivier Houchard */ 1336fc729afSOlivier Houchard void (*cf_icache_sync_all) (void); 1346fc729afSOlivier Houchard void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); 1356fc729afSOlivier Houchard 1366fc729afSOlivier Houchard void (*cf_dcache_wbinv_all) (void); 1376fc729afSOlivier Houchard void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t); 1386fc729afSOlivier Houchard void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t); 1396fc729afSOlivier Houchard void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t); 1406fc729afSOlivier Houchard 1416fc729afSOlivier Houchard void (*cf_idcache_wbinv_all) (void); 1426fc729afSOlivier Houchard void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t); 143425b5be3SOlivier Houchard void (*cf_l2cache_wbinv_all) (void); 144425b5be3SOlivier Houchard void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t); 145425b5be3SOlivier Houchard void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t); 146425b5be3SOlivier Houchard void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t); 1476fc729afSOlivier Houchard 1486fc729afSOlivier Houchard /* Other functions */ 1496fc729afSOlivier Houchard 1506fc729afSOlivier Houchard void (*cf_flush_prefetchbuf) (void); 1516fc729afSOlivier Houchard void (*cf_drain_writebuf) (void); 1526fc729afSOlivier Houchard void (*cf_flush_brnchtgt_C) (void); 1536fc729afSOlivier Houchard void (*cf_flush_brnchtgt_E) (u_int va); 1546fc729afSOlivier Houchard 1556fc729afSOlivier Houchard void (*cf_sleep) (int mode); 1566fc729afSOlivier Houchard 1576fc729afSOlivier Houchard /* Soft functions */ 1586fc729afSOlivier Houchard 1596fc729afSOlivier Houchard int (*cf_dataabt_fixup) (void *arg); 1606fc729afSOlivier Houchard int (*cf_prefetchabt_fixup) (void *arg); 1616fc729afSOlivier Houchard 1626fc729afSOlivier Houchard void (*cf_context_switch) (void); 1636fc729afSOlivier Houchard 1646fc729afSOlivier Houchard void (*cf_setup) (char *string); 1656fc729afSOlivier Houchard }; 1666fc729afSOlivier Houchard 1676fc729afSOlivier Houchard extern struct cpu_functions cpufuncs; 1686fc729afSOlivier Houchard extern u_int cputype; 1696fc729afSOlivier Houchard 1706fc729afSOlivier Houchard #define cpu_id() cpufuncs.cf_id() 1716fc729afSOlivier Houchard #define cpu_cpwait() cpufuncs.cf_cpwait() 1726fc729afSOlivier Houchard 1736fc729afSOlivier Houchard #define cpu_control(c, e) cpufuncs.cf_control(c, e) 1746fc729afSOlivier Houchard #define cpu_domains(d) cpufuncs.cf_domains(d) 1756fc729afSOlivier Houchard #define cpu_setttb(t) cpufuncs.cf_setttb(t) 1766fc729afSOlivier Houchard #define cpu_faultstatus() cpufuncs.cf_faultstatus() 1776fc729afSOlivier Houchard #define cpu_faultaddress() cpufuncs.cf_faultaddress() 1786fc729afSOlivier Houchard 179cf1a573fSOleksandr Tymoshenko #ifndef SMP 180cf1a573fSOleksandr Tymoshenko 1816fc729afSOlivier Houchard #define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID() 1826fc729afSOlivier Houchard #define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e) 1836fc729afSOlivier Houchard #define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI() 1846fc729afSOlivier Houchard #define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e) 1856fc729afSOlivier Houchard #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() 1866fc729afSOlivier Houchard #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) 1876fc729afSOlivier Houchard 188cf1a573fSOleksandr Tymoshenko #else 189cf1a573fSOleksandr Tymoshenko void tlb_broadcast(int); 190cf1a573fSOleksandr Tymoshenko 191cf1a573fSOleksandr Tymoshenko #ifdef CPU_CORTEXA 192cf1a573fSOleksandr Tymoshenko #define TLB_BROADCAST /* No need to explicitely send an IPI */ 193cf1a573fSOleksandr Tymoshenko #else 194cf1a573fSOleksandr Tymoshenko #define TLB_BROADCAST tlb_broadcast(7) 195cf1a573fSOleksandr Tymoshenko #endif 196cf1a573fSOleksandr Tymoshenko 197cf1a573fSOleksandr Tymoshenko #define cpu_tlb_flushID() do { \ 198cf1a573fSOleksandr Tymoshenko cpufuncs.cf_tlb_flushID(); \ 199cf1a573fSOleksandr Tymoshenko TLB_BROADCAST; \ 200cf1a573fSOleksandr Tymoshenko } while(0) 201cf1a573fSOleksandr Tymoshenko 202cf1a573fSOleksandr Tymoshenko #define cpu_tlb_flushID_SE(e) do { \ 203cf1a573fSOleksandr Tymoshenko cpufuncs.cf_tlb_flushID_SE(e); \ 204cf1a573fSOleksandr Tymoshenko TLB_BROADCAST; \ 205cf1a573fSOleksandr Tymoshenko } while(0) 206cf1a573fSOleksandr Tymoshenko 207cf1a573fSOleksandr Tymoshenko 208cf1a573fSOleksandr Tymoshenko #define cpu_tlb_flushI() do { \ 209cf1a573fSOleksandr Tymoshenko cpufuncs.cf_tlb_flushI(); \ 210cf1a573fSOleksandr Tymoshenko TLB_BROADCAST; \ 211cf1a573fSOleksandr Tymoshenko } while(0) 212cf1a573fSOleksandr Tymoshenko 213cf1a573fSOleksandr Tymoshenko 214cf1a573fSOleksandr Tymoshenko #define cpu_tlb_flushI_SE(e) do { \ 215cf1a573fSOleksandr Tymoshenko cpufuncs.cf_tlb_flushI_SE(e); \ 216cf1a573fSOleksandr Tymoshenko TLB_BROADCAST; \ 217cf1a573fSOleksandr Tymoshenko } while(0) 218cf1a573fSOleksandr Tymoshenko 219cf1a573fSOleksandr Tymoshenko 220cf1a573fSOleksandr Tymoshenko #define cpu_tlb_flushD() do { \ 221cf1a573fSOleksandr Tymoshenko cpufuncs.cf_tlb_flushD(); \ 222cf1a573fSOleksandr Tymoshenko TLB_BROADCAST; \ 223cf1a573fSOleksandr Tymoshenko } while(0) 224cf1a573fSOleksandr Tymoshenko 225cf1a573fSOleksandr Tymoshenko 226cf1a573fSOleksandr Tymoshenko #define cpu_tlb_flushD_SE(e) do { \ 227cf1a573fSOleksandr Tymoshenko cpufuncs.cf_tlb_flushD_SE(e); \ 228cf1a573fSOleksandr Tymoshenko TLB_BROADCAST; \ 229cf1a573fSOleksandr Tymoshenko } while(0) 230cf1a573fSOleksandr Tymoshenko 231cf1a573fSOleksandr Tymoshenko #endif 232cf1a573fSOleksandr Tymoshenko 2336fc729afSOlivier Houchard #define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() 2346fc729afSOlivier Houchard #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) 2356fc729afSOlivier Houchard 2366fc729afSOlivier Houchard #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() 2376fc729afSOlivier Houchard #define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s)) 2386fc729afSOlivier Houchard #define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s)) 2396fc729afSOlivier Houchard #define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s)) 2406fc729afSOlivier Houchard 2416fc729afSOlivier Houchard #define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all() 2426fc729afSOlivier Houchard #define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s)) 243425b5be3SOlivier Houchard #define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all() 244425b5be3SOlivier Houchard #define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s)) 245425b5be3SOlivier Houchard #define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s)) 246425b5be3SOlivier Houchard #define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s)) 2476fc729afSOlivier Houchard 2486fc729afSOlivier Houchard #define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf() 2496fc729afSOlivier Houchard #define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf() 2506fc729afSOlivier Houchard #define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C() 2516fc729afSOlivier Houchard #define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e) 2526fc729afSOlivier Houchard 2536fc729afSOlivier Houchard #define cpu_sleep(m) cpufuncs.cf_sleep(m) 2546fc729afSOlivier Houchard 2556fc729afSOlivier Houchard #define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a) 2566fc729afSOlivier Houchard #define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a) 2576fc729afSOlivier Houchard #define ABORT_FIXUP_OK 0 /* fixup succeeded */ 2586fc729afSOlivier Houchard #define ABORT_FIXUP_FAILED 1 /* fixup failed */ 2596fc729afSOlivier Houchard #define ABORT_FIXUP_RETURN 2 /* abort handler should return */ 2606fc729afSOlivier Houchard 2616fc729afSOlivier Houchard #define cpu_setup(a) cpufuncs.cf_setup(a) 2626fc729afSOlivier Houchard 2636fc729afSOlivier Houchard int set_cpufuncs (void); 2646fc729afSOlivier Houchard #define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */ 2656fc729afSOlivier Houchard #define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */ 2666fc729afSOlivier Houchard 2676fc729afSOlivier Houchard void cpufunc_nullop (void); 2686fc729afSOlivier Houchard int cpufunc_null_fixup (void *); 2696fc729afSOlivier Houchard int early_abort_fixup (void *); 2706fc729afSOlivier Houchard int late_abort_fixup (void *); 2716fc729afSOlivier Houchard u_int cpufunc_id (void); 272cf1a573fSOleksandr Tymoshenko u_int cpufunc_cpuid (void); 2736fc729afSOlivier Houchard u_int cpufunc_control (u_int clear, u_int bic); 2746fc729afSOlivier Houchard void cpufunc_domains (u_int domains); 2756fc729afSOlivier Houchard u_int cpufunc_faultstatus (void); 2766fc729afSOlivier Houchard u_int cpufunc_faultaddress (void); 277cf1a573fSOleksandr Tymoshenko u_int cpu_pfr (int); 2786fc729afSOlivier Houchard 2796fc729afSOlivier Houchard #ifdef CPU_ARM3 2806fc729afSOlivier Houchard u_int arm3_control (u_int clear, u_int bic); 2816fc729afSOlivier Houchard void arm3_cache_flush (void); 2826fc729afSOlivier Houchard #endif /* CPU_ARM3 */ 2836fc729afSOlivier Houchard 2846fc729afSOlivier Houchard #if defined(CPU_ARM6) || defined(CPU_ARM7) 2856fc729afSOlivier Houchard void arm67_setttb (u_int ttb); 2866fc729afSOlivier Houchard void arm67_tlb_flush (void); 2876fc729afSOlivier Houchard void arm67_tlb_purge (u_int va); 2886fc729afSOlivier Houchard void arm67_cache_flush (void); 2896fc729afSOlivier Houchard void arm67_context_switch (void); 2906fc729afSOlivier Houchard #endif /* CPU_ARM6 || CPU_ARM7 */ 2916fc729afSOlivier Houchard 2926fc729afSOlivier Houchard #ifdef CPU_ARM6 2936fc729afSOlivier Houchard void arm6_setup (char *string); 2946fc729afSOlivier Houchard #endif /* CPU_ARM6 */ 2956fc729afSOlivier Houchard 2966fc729afSOlivier Houchard #ifdef CPU_ARM7 2976fc729afSOlivier Houchard void arm7_setup (char *string); 2986fc729afSOlivier Houchard #endif /* CPU_ARM7 */ 2996fc729afSOlivier Houchard 3006fc729afSOlivier Houchard #ifdef CPU_ARM7TDMI 3016fc729afSOlivier Houchard int arm7_dataabt_fixup (void *arg); 3026fc729afSOlivier Houchard void arm7tdmi_setup (char *string); 3036fc729afSOlivier Houchard void arm7tdmi_setttb (u_int ttb); 3046fc729afSOlivier Houchard void arm7tdmi_tlb_flushID (void); 3056fc729afSOlivier Houchard void arm7tdmi_tlb_flushID_SE (u_int va); 3066fc729afSOlivier Houchard void arm7tdmi_cache_flushID (void); 3076fc729afSOlivier Houchard void arm7tdmi_context_switch (void); 3086fc729afSOlivier Houchard #endif /* CPU_ARM7TDMI */ 3096fc729afSOlivier Houchard 3106fc729afSOlivier Houchard #ifdef CPU_ARM8 3116fc729afSOlivier Houchard void arm8_setttb (u_int ttb); 3126fc729afSOlivier Houchard void arm8_tlb_flushID (void); 3136fc729afSOlivier Houchard void arm8_tlb_flushID_SE (u_int va); 3146fc729afSOlivier Houchard void arm8_cache_flushID (void); 3156fc729afSOlivier Houchard void arm8_cache_flushID_E (u_int entry); 3166fc729afSOlivier Houchard void arm8_cache_cleanID (void); 3176fc729afSOlivier Houchard void arm8_cache_cleanID_E (u_int entry); 3186fc729afSOlivier Houchard void arm8_cache_purgeID (void); 3196fc729afSOlivier Houchard void arm8_cache_purgeID_E (u_int entry); 3206fc729afSOlivier Houchard 3216fc729afSOlivier Houchard void arm8_cache_syncI (void); 3226fc729afSOlivier Houchard void arm8_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 3236fc729afSOlivier Houchard void arm8_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 3246fc729afSOlivier Houchard void arm8_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 3256fc729afSOlivier Houchard void arm8_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 3266fc729afSOlivier Houchard void arm8_cache_syncI_rng (vm_offset_t start, vm_size_t end); 3276fc729afSOlivier Houchard 3286fc729afSOlivier Houchard void arm8_context_switch (void); 3296fc729afSOlivier Houchard 3306fc729afSOlivier Houchard void arm8_setup (char *string); 3316fc729afSOlivier Houchard 3326fc729afSOlivier Houchard u_int arm8_clock_config (u_int, u_int); 3336fc729afSOlivier Houchard #endif 3346fc729afSOlivier Houchard 335381a19ccSRui Paulo 33664c68f1cSKevin Lo #if defined(CPU_FA526) || defined(CPU_FA626TE) 337381a19ccSRui Paulo void fa526_setup (char *arg); 338381a19ccSRui Paulo void fa526_setttb (u_int ttb); 339381a19ccSRui Paulo void fa526_context_switch (void); 340381a19ccSRui Paulo void fa526_cpu_sleep (int); 341381a19ccSRui Paulo void fa526_tlb_flushI_SE (u_int); 342381a19ccSRui Paulo void fa526_tlb_flushID_SE (u_int); 343381a19ccSRui Paulo void fa526_flush_prefetchbuf (void); 344381a19ccSRui Paulo void fa526_flush_brnchtgt_E (u_int); 345381a19ccSRui Paulo 346381a19ccSRui Paulo void fa526_icache_sync_all (void); 347381a19ccSRui Paulo void fa526_icache_sync_range(vm_offset_t start, vm_size_t end); 348381a19ccSRui Paulo void fa526_dcache_wbinv_all (void); 349381a19ccSRui Paulo void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end); 350381a19ccSRui Paulo void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end); 351381a19ccSRui Paulo void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end); 352381a19ccSRui Paulo void fa526_idcache_wbinv_all(void); 353381a19ccSRui Paulo void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end); 354381a19ccSRui Paulo #endif 355381a19ccSRui Paulo 356381a19ccSRui Paulo 3576fc729afSOlivier Houchard #ifdef CPU_SA110 3586fc729afSOlivier Houchard void sa110_setup (char *string); 3596fc729afSOlivier Houchard void sa110_context_switch (void); 3606fc729afSOlivier Houchard #endif /* CPU_SA110 */ 3616fc729afSOlivier Houchard 3626fc729afSOlivier Houchard #if defined(CPU_SA1100) || defined(CPU_SA1110) 3636fc729afSOlivier Houchard void sa11x0_drain_readbuf (void); 3646fc729afSOlivier Houchard 3656fc729afSOlivier Houchard void sa11x0_context_switch (void); 3666fc729afSOlivier Houchard void sa11x0_cpu_sleep (int mode); 3676fc729afSOlivier Houchard 3686fc729afSOlivier Houchard void sa11x0_setup (char *string); 3696fc729afSOlivier Houchard #endif 3706fc729afSOlivier Houchard 3716fc729afSOlivier Houchard #if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) 3726fc729afSOlivier Houchard void sa1_setttb (u_int ttb); 3736fc729afSOlivier Houchard 3746fc729afSOlivier Houchard void sa1_tlb_flushID_SE (u_int va); 3756fc729afSOlivier Houchard 3766fc729afSOlivier Houchard void sa1_cache_flushID (void); 3776fc729afSOlivier Houchard void sa1_cache_flushI (void); 3786fc729afSOlivier Houchard void sa1_cache_flushD (void); 3796fc729afSOlivier Houchard void sa1_cache_flushD_SE (u_int entry); 3806fc729afSOlivier Houchard 3816fc729afSOlivier Houchard void sa1_cache_cleanID (void); 3826fc729afSOlivier Houchard void sa1_cache_cleanD (void); 3836fc729afSOlivier Houchard void sa1_cache_cleanD_E (u_int entry); 3846fc729afSOlivier Houchard 3856fc729afSOlivier Houchard void sa1_cache_purgeID (void); 3866fc729afSOlivier Houchard void sa1_cache_purgeID_E (u_int entry); 3876fc729afSOlivier Houchard void sa1_cache_purgeD (void); 3886fc729afSOlivier Houchard void sa1_cache_purgeD_E (u_int entry); 3896fc729afSOlivier Houchard 3906fc729afSOlivier Houchard void sa1_cache_syncI (void); 3916fc729afSOlivier Houchard void sa1_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 3926fc729afSOlivier Houchard void sa1_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 3936fc729afSOlivier Houchard void sa1_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 3946fc729afSOlivier Houchard void sa1_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 3956fc729afSOlivier Houchard void sa1_cache_syncI_rng (vm_offset_t start, vm_size_t end); 3966fc729afSOlivier Houchard 3976fc729afSOlivier Houchard #endif 3986fc729afSOlivier Houchard 3996fc729afSOlivier Houchard #ifdef CPU_ARM9 4006fc729afSOlivier Houchard void arm9_setttb (u_int); 4016fc729afSOlivier Houchard 4026fc729afSOlivier Houchard void arm9_tlb_flushID_SE (u_int va); 4036fc729afSOlivier Houchard 4044eaa43e6SKevin Lo void arm9_icache_sync_all (void); 4054eaa43e6SKevin Lo void arm9_icache_sync_range (vm_offset_t, vm_size_t); 4066fc729afSOlivier Houchard 4074eaa43e6SKevin Lo void arm9_dcache_wbinv_all (void); 4084eaa43e6SKevin Lo void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t); 4094eaa43e6SKevin Lo void arm9_dcache_inv_range (vm_offset_t, vm_size_t); 4104eaa43e6SKevin Lo void arm9_dcache_wb_range (vm_offset_t, vm_size_t); 4116fc729afSOlivier Houchard 4124eaa43e6SKevin Lo void arm9_idcache_wbinv_all (void); 4134eaa43e6SKevin Lo void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t); 4146fc729afSOlivier Houchard 4156fc729afSOlivier Houchard void arm9_context_switch (void); 4166fc729afSOlivier Houchard 4176fc729afSOlivier Houchard void arm9_setup (char *string); 418094df973SOlivier Houchard 419094df973SOlivier Houchard extern unsigned arm9_dcache_sets_max; 420094df973SOlivier Houchard extern unsigned arm9_dcache_sets_inc; 421094df973SOlivier Houchard extern unsigned arm9_dcache_index_max; 422094df973SOlivier Houchard extern unsigned arm9_dcache_index_inc; 4236fc729afSOlivier Houchard #endif 4246fc729afSOlivier Houchard 42563b25978SWarner Losh #if defined(CPU_ARM9E) || defined(CPU_ARM10) 4266fc729afSOlivier Houchard void arm10_setttb (u_int); 4276fc729afSOlivier Houchard 4286fc729afSOlivier Houchard void arm10_tlb_flushID_SE (u_int); 4296fc729afSOlivier Houchard void arm10_tlb_flushI_SE (u_int); 4306fc729afSOlivier Houchard 4316fc729afSOlivier Houchard void arm10_icache_sync_all (void); 4326fc729afSOlivier Houchard void arm10_icache_sync_range (vm_offset_t, vm_size_t); 4336fc729afSOlivier Houchard 4346fc729afSOlivier Houchard void arm10_dcache_wbinv_all (void); 4356fc729afSOlivier Houchard void arm10_dcache_wbinv_range (vm_offset_t, vm_size_t); 4366fc729afSOlivier Houchard void arm10_dcache_inv_range (vm_offset_t, vm_size_t); 4376fc729afSOlivier Houchard void arm10_dcache_wb_range (vm_offset_t, vm_size_t); 4386fc729afSOlivier Houchard 4396fc729afSOlivier Houchard void arm10_idcache_wbinv_all (void); 4406fc729afSOlivier Houchard void arm10_idcache_wbinv_range (vm_offset_t, vm_size_t); 4416fc729afSOlivier Houchard 4426fc729afSOlivier Houchard void arm10_context_switch (void); 4436fc729afSOlivier Houchard 4446fc729afSOlivier Houchard void arm10_setup (char *string); 4456fc729afSOlivier Houchard 4466fc729afSOlivier Houchard extern unsigned arm10_dcache_sets_max; 4476fc729afSOlivier Houchard extern unsigned arm10_dcache_sets_inc; 4486fc729afSOlivier Houchard extern unsigned arm10_dcache_index_max; 4496fc729afSOlivier Houchard extern unsigned arm10_dcache_index_inc; 450ba6faad6SRafal Jaworowski 4511ee5b3b4SRafal Jaworowski u_int sheeva_control_ext (u_int, u_int); 452cfa892b5SAlexander Motin void sheeva_cpu_sleep (int); 4531ee5b3b4SRafal Jaworowski void sheeva_setttb (u_int); 4541ee5b3b4SRafal Jaworowski void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); 4551ee5b3b4SRafal Jaworowski void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); 4561ee5b3b4SRafal Jaworowski void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); 4571ee5b3b4SRafal Jaworowski void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); 458ba6faad6SRafal Jaworowski 4591ee5b3b4SRafal Jaworowski void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); 4601ee5b3b4SRafal Jaworowski void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); 4611ee5b3b4SRafal Jaworowski void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); 4621ee5b3b4SRafal Jaworowski void sheeva_l2cache_wbinv_all (void); 4636fc729afSOlivier Houchard #endif 4646fc729afSOlivier Houchard 465cf1a573fSOleksandr Tymoshenko #if defined(CPU_ARM11) || defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) 46663b25978SWarner Losh void arm11_setttb (u_int); 467cf1a573fSOleksandr Tymoshenko void arm11_sleep (int); 46863b25978SWarner Losh 46963b25978SWarner Losh void arm11_tlb_flushID_SE (u_int); 47063b25978SWarner Losh void arm11_tlb_flushI_SE (u_int); 47163b25978SWarner Losh 47263b25978SWarner Losh void arm11_context_switch (void); 47363b25978SWarner Losh 47463b25978SWarner Losh void arm11_setup (char *string); 47563b25978SWarner Losh void arm11_tlb_flushID (void); 47663b25978SWarner Losh void arm11_tlb_flushI (void); 47763b25978SWarner Losh void arm11_tlb_flushD (void); 47863b25978SWarner Losh void arm11_tlb_flushD_SE (u_int va); 47963b25978SWarner Losh 48063b25978SWarner Losh void arm11_drain_writebuf (void); 481cf1a573fSOleksandr Tymoshenko 482cf1a573fSOleksandr Tymoshenko void pj4b_setttb (u_int); 483cf1a573fSOleksandr Tymoshenko 484cf1a573fSOleksandr Tymoshenko void pj4b_icache_sync_range (vm_offset_t, vm_size_t); 485cf1a573fSOleksandr Tymoshenko 486cf1a573fSOleksandr Tymoshenko void pj4b_dcache_wbinv_range (vm_offset_t, vm_size_t); 487cf1a573fSOleksandr Tymoshenko void pj4b_dcache_inv_range (vm_offset_t, vm_size_t); 488cf1a573fSOleksandr Tymoshenko void pj4b_dcache_wb_range (vm_offset_t, vm_size_t); 489cf1a573fSOleksandr Tymoshenko 490cf1a573fSOleksandr Tymoshenko void pj4b_idcache_wbinv_range (vm_offset_t, vm_size_t); 491cf1a573fSOleksandr Tymoshenko 492cf1a573fSOleksandr Tymoshenko void pj4b_drain_readbuf (void); 493cf1a573fSOleksandr Tymoshenko void pj4b_flush_brnchtgt_all (void); 494cf1a573fSOleksandr Tymoshenko void pj4b_flush_brnchtgt_va (u_int); 495cf1a573fSOleksandr Tymoshenko void pj4b_sleep (int); 496cf1a573fSOleksandr Tymoshenko 497cf1a573fSOleksandr Tymoshenko void armv6_icache_sync_all (void); 4988f2a36c0SOleksandr Tymoshenko void armv6_icache_sync_range (vm_offset_t, vm_size_t); 4998f2a36c0SOleksandr Tymoshenko 500cf1a573fSOleksandr Tymoshenko void armv6_dcache_wbinv_all (void); 5018f2a36c0SOleksandr Tymoshenko void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t); 5028f2a36c0SOleksandr Tymoshenko void armv6_dcache_inv_range (vm_offset_t, vm_size_t); 5038f2a36c0SOleksandr Tymoshenko void armv6_dcache_wb_range (vm_offset_t, vm_size_t); 5048f2a36c0SOleksandr Tymoshenko 505cf1a573fSOleksandr Tymoshenko void armv6_idcache_wbinv_all (void); 5068f2a36c0SOleksandr Tymoshenko void armv6_idcache_wbinv_range (vm_offset_t, vm_size_t); 507cf1a573fSOleksandr Tymoshenko 508cf1a573fSOleksandr Tymoshenko void armv7_setttb (u_int); 509cf1a573fSOleksandr Tymoshenko void armv7_tlb_flushID (void); 510cf1a573fSOleksandr Tymoshenko void armv7_tlb_flushID_SE (u_int); 511cf1a573fSOleksandr Tymoshenko void armv7_icache_sync_range (vm_offset_t, vm_size_t); 512cf1a573fSOleksandr Tymoshenko void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); 513cf1a573fSOleksandr Tymoshenko void armv7_dcache_wbinv_all (void); 514cf1a573fSOleksandr Tymoshenko void armv7_idcache_wbinv_all (void); 515cf1a573fSOleksandr Tymoshenko void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t); 516cf1a573fSOleksandr Tymoshenko void armv7_dcache_inv_range (vm_offset_t, vm_size_t); 517cf1a573fSOleksandr Tymoshenko void armv7_dcache_wb_range (vm_offset_t, vm_size_t); 518cf1a573fSOleksandr Tymoshenko void armv7_cpu_sleep (int); 519cf1a573fSOleksandr Tymoshenko void armv7_setup (char *string); 520cf1a573fSOleksandr Tymoshenko void armv7_context_switch (void); 521cf1a573fSOleksandr Tymoshenko void armv7_drain_writebuf (void); 522cf1a573fSOleksandr Tymoshenko void armv7_sev (void); 523cf1a573fSOleksandr Tymoshenko u_int armv7_auxctrl (u_int, u_int); 524cf1a573fSOleksandr Tymoshenko void pj4bv7_setup (char *string); 525cf1a573fSOleksandr Tymoshenko void pj4bv6_setup (char *string); 526cf1a573fSOleksandr Tymoshenko void pj4b_config (void); 527cf1a573fSOleksandr Tymoshenko 528cf1a573fSOleksandr Tymoshenko int get_core_id (void); 529cf1a573fSOleksandr Tymoshenko 530cf1a573fSOleksandr Tymoshenko void armadaxp_idcache_wbinv_all (void); 531cf1a573fSOleksandr Tymoshenko 532cf1a573fSOleksandr Tymoshenko void cortexa_setup (char *); 53363b25978SWarner Losh #endif 53463b25978SWarner Losh 53563b25978SWarner Losh #if defined(CPU_ARM9E) || defined (CPU_ARM10) 53663b25978SWarner Losh void armv5_ec_setttb(u_int); 53763b25978SWarner Losh 53863b25978SWarner Losh void armv5_ec_icache_sync_all(void); 53963b25978SWarner Losh void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); 54063b25978SWarner Losh 54163b25978SWarner Losh void armv5_ec_dcache_wbinv_all(void); 54263b25978SWarner Losh void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t); 54363b25978SWarner Losh void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t); 54463b25978SWarner Losh void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t); 54563b25978SWarner Losh 54663b25978SWarner Losh void armv5_ec_idcache_wbinv_all(void); 54763b25978SWarner Losh void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t); 54863b25978SWarner Losh #endif 54963b25978SWarner Losh 550cf1a573fSOleksandr Tymoshenko #if defined (CPU_ARM10) 55163b25978SWarner Losh void armv5_setttb(u_int); 55263b25978SWarner Losh 55363b25978SWarner Losh void armv5_icache_sync_all(void); 55463b25978SWarner Losh void armv5_icache_sync_range(vm_offset_t, vm_size_t); 55563b25978SWarner Losh 55663b25978SWarner Losh void armv5_dcache_wbinv_all(void); 55763b25978SWarner Losh void armv5_dcache_wbinv_range(vm_offset_t, vm_size_t); 55863b25978SWarner Losh void armv5_dcache_inv_range(vm_offset_t, vm_size_t); 55963b25978SWarner Losh void armv5_dcache_wb_range(vm_offset_t, vm_size_t); 56063b25978SWarner Losh 56163b25978SWarner Losh void armv5_idcache_wbinv_all(void); 56263b25978SWarner Losh void armv5_idcache_wbinv_range(vm_offset_t, vm_size_t); 56363b25978SWarner Losh 56463b25978SWarner Losh extern unsigned armv5_dcache_sets_max; 56563b25978SWarner Losh extern unsigned armv5_dcache_sets_inc; 56663b25978SWarner Losh extern unsigned armv5_dcache_index_max; 56763b25978SWarner Losh extern unsigned armv5_dcache_index_inc; 56863b25978SWarner Losh #endif 56963b25978SWarner Losh 57063b25978SWarner Losh #if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \ 57163b25978SWarner Losh defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) || \ 5726fc729afSOlivier Houchard defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 57364c68f1cSKevin Lo defined(CPU_FA526) || defined(CPU_FA626TE) || \ 57411d1528cSOlivier Houchard defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 575676b1fbdSOlivier Houchard defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 5766fc729afSOlivier Houchard 5776fc729afSOlivier Houchard void armv4_tlb_flushID (void); 5786fc729afSOlivier Houchard void armv4_tlb_flushI (void); 5796fc729afSOlivier Houchard void armv4_tlb_flushD (void); 5806fc729afSOlivier Houchard void armv4_tlb_flushD_SE (u_int va); 5816fc729afSOlivier Houchard 5826fc729afSOlivier Houchard void armv4_drain_writebuf (void); 5836fc729afSOlivier Houchard #endif 5846fc729afSOlivier Houchard 5856fc729afSOlivier Houchard #if defined(CPU_IXP12X0) 5866fc729afSOlivier Houchard void ixp12x0_drain_readbuf (void); 5876fc729afSOlivier Houchard void ixp12x0_context_switch (void); 5886fc729afSOlivier Houchard void ixp12x0_setup (char *string); 5896fc729afSOlivier Houchard #endif 5906fc729afSOlivier Houchard 5916fc729afSOlivier Houchard #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \ 59211d1528cSOlivier Houchard defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \ 593676b1fbdSOlivier Houchard defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) 5946fc729afSOlivier Houchard void xscale_cpwait (void); 5956fc729afSOlivier Houchard 5966fc729afSOlivier Houchard void xscale_cpu_sleep (int mode); 5976fc729afSOlivier Houchard 5986fc729afSOlivier Houchard u_int xscale_control (u_int clear, u_int bic); 5996fc729afSOlivier Houchard 6006fc729afSOlivier Houchard void xscale_setttb (u_int ttb); 6016fc729afSOlivier Houchard 6026fc729afSOlivier Houchard void xscale_tlb_flushID_SE (u_int va); 6036fc729afSOlivier Houchard 6046fc729afSOlivier Houchard void xscale_cache_flushID (void); 6056fc729afSOlivier Houchard void xscale_cache_flushI (void); 6066fc729afSOlivier Houchard void xscale_cache_flushD (void); 6076fc729afSOlivier Houchard void xscale_cache_flushD_SE (u_int entry); 6086fc729afSOlivier Houchard 6096fc729afSOlivier Houchard void xscale_cache_cleanID (void); 6106fc729afSOlivier Houchard void xscale_cache_cleanD (void); 6116fc729afSOlivier Houchard void xscale_cache_cleanD_E (u_int entry); 6126fc729afSOlivier Houchard 6136fc729afSOlivier Houchard void xscale_cache_clean_minidata (void); 6146fc729afSOlivier Houchard 6156fc729afSOlivier Houchard void xscale_cache_purgeID (void); 6166fc729afSOlivier Houchard void xscale_cache_purgeID_E (u_int entry); 6176fc729afSOlivier Houchard void xscale_cache_purgeD (void); 6186fc729afSOlivier Houchard void xscale_cache_purgeD_E (u_int entry); 6196fc729afSOlivier Houchard 6206fc729afSOlivier Houchard void xscale_cache_syncI (void); 6216fc729afSOlivier Houchard void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 6226fc729afSOlivier Houchard void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 6236fc729afSOlivier Houchard void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 6246fc729afSOlivier Houchard void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 6256fc729afSOlivier Houchard void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end); 6266fc729afSOlivier Houchard void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end); 6276fc729afSOlivier Houchard 6286fc729afSOlivier Houchard void xscale_context_switch (void); 6296fc729afSOlivier Houchard 6306fc729afSOlivier Houchard void xscale_setup (char *string); 63111d1528cSOlivier Houchard #endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 63211d1528cSOlivier Houchard CPU_XSCALE_80219 */ 6336fc729afSOlivier Houchard 634676b1fbdSOlivier Houchard #ifdef CPU_XSCALE_81342 635676b1fbdSOlivier Houchard 636425b5be3SOlivier Houchard void xscalec3_l2cache_purge (void); 637425b5be3SOlivier Houchard void xscalec3_cache_purgeID (void); 638425b5be3SOlivier Houchard void xscalec3_cache_purgeD (void); 639676b1fbdSOlivier Houchard void xscalec3_cache_cleanID (void); 640676b1fbdSOlivier Houchard void xscalec3_cache_cleanD (void); 641676b1fbdSOlivier Houchard void xscalec3_cache_syncI (void); 642425b5be3SOlivier Houchard 643676b1fbdSOlivier Houchard void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end); 644676b1fbdSOlivier Houchard void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end); 645425b5be3SOlivier Houchard void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end); 646425b5be3SOlivier Houchard void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end); 647425b5be3SOlivier Houchard void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end); 648425b5be3SOlivier Houchard 649425b5be3SOlivier Houchard void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t); 650425b5be3SOlivier Houchard void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end); 651425b5be3SOlivier Houchard void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end); 652676b1fbdSOlivier Houchard 653676b1fbdSOlivier Houchard 654676b1fbdSOlivier Houchard void xscalec3_setttb (u_int ttb); 655676b1fbdSOlivier Houchard void xscalec3_context_switch (void); 656676b1fbdSOlivier Houchard 657676b1fbdSOlivier Houchard #endif /* CPU_XSCALE_81342 */ 658676b1fbdSOlivier Houchard 6596fc729afSOlivier Houchard #define tlb_flush cpu_tlb_flushID 6606fc729afSOlivier Houchard #define setttb cpu_setttb 6616fc729afSOlivier Houchard #define drain_writebuf cpu_drain_writebuf 6626fc729afSOlivier Houchard 6636fc729afSOlivier Houchard /* 6646fc729afSOlivier Houchard * Macros for manipulating CPU interrupts 6656fc729afSOlivier Houchard */ 6666fc729afSOlivier Houchard static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__)); 6676fc729afSOlivier Houchard 6686fc729afSOlivier Houchard static __inline u_int32_t 6696fc729afSOlivier Houchard __set_cpsr_c(u_int bic, u_int eor) 6706fc729afSOlivier Houchard { 6716fc729afSOlivier Houchard u_int32_t tmp, ret; 6726fc729afSOlivier Houchard 6736fc729afSOlivier Houchard __asm __volatile( 6746fc729afSOlivier Houchard "mrs %0, cpsr\n" /* Get the CPSR */ 6756fc729afSOlivier Houchard "bic %1, %0, %2\n" /* Clear bits */ 6766fc729afSOlivier Houchard "eor %1, %1, %3\n" /* XOR bits */ 6776fc729afSOlivier Houchard "msr cpsr_c, %1\n" /* Set the control field of CPSR */ 6786fc729afSOlivier Houchard : "=&r" (ret), "=&r" (tmp) 67924e01b0cSOlivier Houchard : "r" (bic), "r" (eor) : "memory"); 6806fc729afSOlivier Houchard 6816fc729afSOlivier Houchard return ret; 6826fc729afSOlivier Houchard } 6836fc729afSOlivier Houchard 684*dfad9244SMarcel Moolenaar #define ARM_CPSR_F32 (1 << 6) /* FIQ disable */ 685*dfad9244SMarcel Moolenaar #define ARM_CPSR_I32 (1 << 7) /* IRQ disable */ 686*dfad9244SMarcel Moolenaar 6876fc729afSOlivier Houchard #define disable_interrupts(mask) \ 688*dfad9244SMarcel Moolenaar (__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), \ 689*dfad9244SMarcel Moolenaar (mask) & (ARM_CPSR_I32 | ARM_CPSR_F32))) 6906fc729afSOlivier Houchard 6916fc729afSOlivier Houchard #define enable_interrupts(mask) \ 692*dfad9244SMarcel Moolenaar (__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), 0)) 6936fc729afSOlivier Houchard 6946fc729afSOlivier Houchard #define restore_interrupts(old_cpsr) \ 695*dfad9244SMarcel Moolenaar (__set_cpsr_c((ARM_CPSR_I32 | ARM_CPSR_F32), \ 696*dfad9244SMarcel Moolenaar (old_cpsr) & (ARM_CPSR_I32 | ARM_CPSR_F32))) 6976fc729afSOlivier Houchard 698*dfad9244SMarcel Moolenaar static __inline register_t 699*dfad9244SMarcel Moolenaar intr_disable(void) 700*dfad9244SMarcel Moolenaar { 701*dfad9244SMarcel Moolenaar register_t s; 702*dfad9244SMarcel Moolenaar 703*dfad9244SMarcel Moolenaar s = disable_interrupts(ARM_CPSR_I32 | ARM_CPSR_F32); 704*dfad9244SMarcel Moolenaar return (s); 705*dfad9244SMarcel Moolenaar } 706*dfad9244SMarcel Moolenaar 707*dfad9244SMarcel Moolenaar static __inline void 708*dfad9244SMarcel Moolenaar intr_restore(register_t s) 709*dfad9244SMarcel Moolenaar { 710*dfad9244SMarcel Moolenaar 711*dfad9244SMarcel Moolenaar restore_interrupts(s); 712*dfad9244SMarcel Moolenaar } 713*dfad9244SMarcel Moolenaar 7146fc729afSOlivier Houchard /* Functions to manipulate the CPSR. */ 7156fc729afSOlivier Houchard u_int SetCPSR(u_int bic, u_int eor); 7166fc729afSOlivier Houchard u_int GetCPSR(void); 7176fc729afSOlivier Houchard 7186fc729afSOlivier Houchard /* 7196fc729afSOlivier Houchard * Functions to manipulate cpu r13 7206fc729afSOlivier Houchard * (in arm/arm32/setstack.S) 7216fc729afSOlivier Houchard */ 7226fc729afSOlivier Houchard 7234eaa43e6SKevin Lo void set_stackptr (u_int mode, u_int address); 7244eaa43e6SKevin Lo u_int get_stackptr (u_int mode); 7256fc729afSOlivier Houchard 7266fc729afSOlivier Houchard /* 7276fc729afSOlivier Houchard * Miscellany 7286fc729afSOlivier Houchard */ 7296fc729afSOlivier Houchard 7304eaa43e6SKevin Lo int get_pc_str_offset (void); 7316fc729afSOlivier Houchard 7326fc729afSOlivier Houchard /* 7336fc729afSOlivier Houchard * CPU functions from locore.S 7346fc729afSOlivier Houchard */ 7356fc729afSOlivier Houchard 7364eaa43e6SKevin Lo void cpu_reset (void) __attribute__((__noreturn__)); 7376fc729afSOlivier Houchard 7386fc729afSOlivier Houchard /* 7396fc729afSOlivier Houchard * Cache info variables. 7406fc729afSOlivier Houchard */ 7416fc729afSOlivier Houchard 7426fc729afSOlivier Houchard /* PRIMARY CACHE VARIABLES */ 7436fc729afSOlivier Houchard extern int arm_picache_size; 7446fc729afSOlivier Houchard extern int arm_picache_line_size; 7456fc729afSOlivier Houchard extern int arm_picache_ways; 7466fc729afSOlivier Houchard 7476fc729afSOlivier Houchard extern int arm_pdcache_size; /* and unified */ 7486fc729afSOlivier Houchard extern int arm_pdcache_line_size; 7496fc729afSOlivier Houchard extern int arm_pdcache_ways; 7506fc729afSOlivier Houchard 7516fc729afSOlivier Houchard extern int arm_pcache_type; 7526fc729afSOlivier Houchard extern int arm_pcache_unified; 7536fc729afSOlivier Houchard 7546fc729afSOlivier Houchard extern int arm_dcache_align; 7556fc729afSOlivier Houchard extern int arm_dcache_align_mask; 7566fc729afSOlivier Houchard 757cf1a573fSOleksandr Tymoshenko extern u_int arm_cache_level; 758cf1a573fSOleksandr Tymoshenko extern u_int arm_cache_loc; 759cf1a573fSOleksandr Tymoshenko extern u_int arm_cache_type[14]; 760cf1a573fSOleksandr Tymoshenko 7616fc729afSOlivier Houchard #endif /* _KERNEL */ 7626fc729afSOlivier Houchard #endif /* _MACHINE_CPUFUNC_H_ */ 7636fc729afSOlivier Houchard 7646fc729afSOlivier Houchard /* End of cpufunc.h */ 765