xref: /freebsd/sys/arm/include/cpufunc.h (revision 24e01b0c593203338c4316e417a04799926b4306)
16fc729afSOlivier Houchard /*	$NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $	*/
26fc729afSOlivier Houchard 
36fc729afSOlivier Houchard /*
46fc729afSOlivier Houchard  * Copyright (c) 1997 Mark Brinicombe.
56fc729afSOlivier Houchard  * Copyright (c) 1997 Causality Limited
66fc729afSOlivier Houchard  * All rights reserved.
76fc729afSOlivier Houchard  *
86fc729afSOlivier Houchard  * Redistribution and use in source and binary forms, with or without
96fc729afSOlivier Houchard  * modification, are permitted provided that the following conditions
106fc729afSOlivier Houchard  * are met:
116fc729afSOlivier Houchard  * 1. Redistributions of source code must retain the above copyright
126fc729afSOlivier Houchard  *    notice, this list of conditions and the following disclaimer.
136fc729afSOlivier Houchard  * 2. Redistributions in binary form must reproduce the above copyright
146fc729afSOlivier Houchard  *    notice, this list of conditions and the following disclaimer in the
156fc729afSOlivier Houchard  *    documentation and/or other materials provided with the distribution.
166fc729afSOlivier Houchard  * 3. All advertising materials mentioning features or use of this software
176fc729afSOlivier Houchard  *    must display the following acknowledgement:
186fc729afSOlivier Houchard  *	This product includes software developed by Causality Limited.
196fc729afSOlivier Houchard  * 4. The name of Causality Limited may not be used to endorse or promote
206fc729afSOlivier Houchard  *    products derived from this software without specific prior written
216fc729afSOlivier Houchard  *    permission.
226fc729afSOlivier Houchard  *
236fc729afSOlivier Houchard  * THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
246fc729afSOlivier Houchard  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
256fc729afSOlivier Houchard  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
266fc729afSOlivier Houchard  * DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
276fc729afSOlivier Houchard  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
286fc729afSOlivier Houchard  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
296fc729afSOlivier Houchard  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
306fc729afSOlivier Houchard  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
316fc729afSOlivier Houchard  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
326fc729afSOlivier Houchard  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
336fc729afSOlivier Houchard  * SUCH DAMAGE.
346fc729afSOlivier Houchard  *
356fc729afSOlivier Houchard  * RiscBSD kernel project
366fc729afSOlivier Houchard  *
376fc729afSOlivier Houchard  * cpufunc.h
386fc729afSOlivier Houchard  *
396fc729afSOlivier Houchard  * Prototypes for cpu, mmu and tlb related functions.
406fc729afSOlivier Houchard  *
416fc729afSOlivier Houchard  * $FreeBSD$
426fc729afSOlivier Houchard  */
436fc729afSOlivier Houchard 
446fc729afSOlivier Houchard #ifndef _MACHINE_CPUFUNC_H_
456fc729afSOlivier Houchard #define _MACHINE_CPUFUNC_H_
466fc729afSOlivier Houchard 
476fc729afSOlivier Houchard #ifdef _KERNEL
486fc729afSOlivier Houchard 
496fc729afSOlivier Houchard #include <sys/types.h>
506fc729afSOlivier Houchard #include <machine/cpuconf.h>
514628245bSOlivier Houchard #include <machine/katelib.h> /* For in[bwl] and out[bwl] */
526fc729afSOlivier Houchard 
534628245bSOlivier Houchard static __inline void
544628245bSOlivier Houchard breakpoint(void)
554628245bSOlivier Houchard {
564628245bSOlivier Houchard }
57be687a0dSOlivier Houchard 
586fc729afSOlivier Houchard struct cpu_functions {
596fc729afSOlivier Houchard 
606fc729afSOlivier Houchard 	/* CPU functions */
616fc729afSOlivier Houchard 
626fc729afSOlivier Houchard 	u_int	(*cf_id)		(void);
636fc729afSOlivier Houchard 	void	(*cf_cpwait)		(void);
646fc729afSOlivier Houchard 
656fc729afSOlivier Houchard 	/* MMU functions */
666fc729afSOlivier Houchard 
676fc729afSOlivier Houchard 	u_int	(*cf_control)		(u_int bic, u_int eor);
686fc729afSOlivier Houchard 	void	(*cf_domains)		(u_int domains);
696fc729afSOlivier Houchard 	void	(*cf_setttb)		(u_int ttb);
706fc729afSOlivier Houchard 	u_int	(*cf_faultstatus)	(void);
716fc729afSOlivier Houchard 	u_int	(*cf_faultaddress)	(void);
726fc729afSOlivier Houchard 
736fc729afSOlivier Houchard 	/* TLB functions */
746fc729afSOlivier Houchard 
756fc729afSOlivier Houchard 	void	(*cf_tlb_flushID)	(void);
766fc729afSOlivier Houchard 	void	(*cf_tlb_flushID_SE)	(u_int va);
776fc729afSOlivier Houchard 	void	(*cf_tlb_flushI)	(void);
786fc729afSOlivier Houchard 	void	(*cf_tlb_flushI_SE)	(u_int va);
796fc729afSOlivier Houchard 	void	(*cf_tlb_flushD)	(void);
806fc729afSOlivier Houchard 	void	(*cf_tlb_flushD_SE)	(u_int va);
816fc729afSOlivier Houchard 
826fc729afSOlivier Houchard 	/*
836fc729afSOlivier Houchard 	 * Cache operations:
846fc729afSOlivier Houchard 	 *
856fc729afSOlivier Houchard 	 * We define the following primitives:
866fc729afSOlivier Houchard 	 *
876fc729afSOlivier Houchard 	 *	icache_sync_all		Synchronize I-cache
886fc729afSOlivier Houchard 	 *	icache_sync_range	Synchronize I-cache range
896fc729afSOlivier Houchard 	 *
906fc729afSOlivier Houchard 	 *	dcache_wbinv_all	Write-back and Invalidate D-cache
916fc729afSOlivier Houchard 	 *	dcache_wbinv_range	Write-back and Invalidate D-cache range
926fc729afSOlivier Houchard 	 *	dcache_inv_range	Invalidate D-cache range
936fc729afSOlivier Houchard 	 *	dcache_wb_range		Write-back D-cache range
946fc729afSOlivier Houchard 	 *
956fc729afSOlivier Houchard 	 *	idcache_wbinv_all	Write-back and Invalidate D-cache,
966fc729afSOlivier Houchard 	 *				Invalidate I-cache
976fc729afSOlivier Houchard 	 *	idcache_wbinv_range	Write-back and Invalidate D-cache,
986fc729afSOlivier Houchard 	 *				Invalidate I-cache range
996fc729afSOlivier Houchard 	 *
1006fc729afSOlivier Houchard 	 * Note that the ARM term for "write-back" is "clean".  We use
1016fc729afSOlivier Houchard 	 * the term "write-back" since it's a more common way to describe
1026fc729afSOlivier Houchard 	 * the operation.
1036fc729afSOlivier Houchard 	 *
1046fc729afSOlivier Houchard 	 * There are some rules that must be followed:
1056fc729afSOlivier Houchard 	 *
1066fc729afSOlivier Houchard 	 *	I-cache Synch (all or range):
1076fc729afSOlivier Houchard 	 *		The goal is to synchronize the instruction stream,
1086fc729afSOlivier Houchard 	 *		so you may beed to write-back dirty D-cache blocks
1096fc729afSOlivier Houchard 	 *		first.  If a range is requested, and you can't
1106fc729afSOlivier Houchard 	 *		synchronize just a range, you have to hit the whole
1116fc729afSOlivier Houchard 	 *		thing.
1126fc729afSOlivier Houchard 	 *
1136fc729afSOlivier Houchard 	 *	D-cache Write-Back and Invalidate range:
1146fc729afSOlivier Houchard 	 *		If you can't WB-Inv a range, you must WB-Inv the
1156fc729afSOlivier Houchard 	 *		entire D-cache.
1166fc729afSOlivier Houchard 	 *
1176fc729afSOlivier Houchard 	 *	D-cache Invalidate:
1186fc729afSOlivier Houchard 	 *		If you can't Inv the D-cache, you must Write-Back
1196fc729afSOlivier Houchard 	 *		and Invalidate.  Code that uses this operation
1206fc729afSOlivier Houchard 	 *		MUST NOT assume that the D-cache will not be written
1216fc729afSOlivier Houchard 	 *		back to memory.
1226fc729afSOlivier Houchard 	 *
1236fc729afSOlivier Houchard 	 *	D-cache Write-Back:
1246fc729afSOlivier Houchard 	 *		If you can't Write-back without doing an Inv,
1256fc729afSOlivier Houchard 	 *		that's fine.  Then treat this as a WB-Inv.
1266fc729afSOlivier Houchard 	 *		Skipping the invalidate is merely an optimization.
1276fc729afSOlivier Houchard 	 *
1286fc729afSOlivier Houchard 	 *	All operations:
1296fc729afSOlivier Houchard 	 *		Valid virtual addresses must be passed to each
1306fc729afSOlivier Houchard 	 *		cache operation.
1316fc729afSOlivier Houchard 	 */
1326fc729afSOlivier Houchard 	void	(*cf_icache_sync_all)	(void);
1336fc729afSOlivier Houchard 	void	(*cf_icache_sync_range)	(vm_offset_t, vm_size_t);
1346fc729afSOlivier Houchard 
1356fc729afSOlivier Houchard 	void	(*cf_dcache_wbinv_all)	(void);
1366fc729afSOlivier Houchard 	void	(*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t);
1376fc729afSOlivier Houchard 	void	(*cf_dcache_inv_range)	(vm_offset_t, vm_size_t);
1386fc729afSOlivier Houchard 	void	(*cf_dcache_wb_range)	(vm_offset_t, vm_size_t);
1396fc729afSOlivier Houchard 
1406fc729afSOlivier Houchard 	void	(*cf_idcache_wbinv_all)	(void);
1416fc729afSOlivier Houchard 	void	(*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
1426fc729afSOlivier Houchard 
1436fc729afSOlivier Houchard 	/* Other functions */
1446fc729afSOlivier Houchard 
1456fc729afSOlivier Houchard 	void	(*cf_flush_prefetchbuf)	(void);
1466fc729afSOlivier Houchard 	void	(*cf_drain_writebuf)	(void);
1476fc729afSOlivier Houchard 	void	(*cf_flush_brnchtgt_C)	(void);
1486fc729afSOlivier Houchard 	void	(*cf_flush_brnchtgt_E)	(u_int va);
1496fc729afSOlivier Houchard 
1506fc729afSOlivier Houchard 	void	(*cf_sleep)		(int mode);
1516fc729afSOlivier Houchard 
1526fc729afSOlivier Houchard 	/* Soft functions */
1536fc729afSOlivier Houchard 
1546fc729afSOlivier Houchard 	int	(*cf_dataabt_fixup)	(void *arg);
1556fc729afSOlivier Houchard 	int	(*cf_prefetchabt_fixup)	(void *arg);
1566fc729afSOlivier Houchard 
1576fc729afSOlivier Houchard 	void	(*cf_context_switch)	(void);
1586fc729afSOlivier Houchard 
1596fc729afSOlivier Houchard 	void	(*cf_setup)		(char *string);
1606fc729afSOlivier Houchard };
1616fc729afSOlivier Houchard 
1626fc729afSOlivier Houchard extern struct cpu_functions cpufuncs;
1636fc729afSOlivier Houchard extern u_int cputype;
1646fc729afSOlivier Houchard 
1656fc729afSOlivier Houchard #define cpu_id()		cpufuncs.cf_id()
1666fc729afSOlivier Houchard #define	cpu_cpwait()		cpufuncs.cf_cpwait()
1676fc729afSOlivier Houchard 
1686fc729afSOlivier Houchard #define cpu_control(c, e)	cpufuncs.cf_control(c, e)
1696fc729afSOlivier Houchard #define cpu_domains(d)		cpufuncs.cf_domains(d)
1706fc729afSOlivier Houchard #define cpu_setttb(t)		cpufuncs.cf_setttb(t)
1716fc729afSOlivier Houchard #define cpu_faultstatus()	cpufuncs.cf_faultstatus()
1726fc729afSOlivier Houchard #define cpu_faultaddress()	cpufuncs.cf_faultaddress()
1736fc729afSOlivier Houchard 
1746fc729afSOlivier Houchard #define	cpu_tlb_flushID()	cpufuncs.cf_tlb_flushID()
1756fc729afSOlivier Houchard #define	cpu_tlb_flushID_SE(e)	cpufuncs.cf_tlb_flushID_SE(e)
1766fc729afSOlivier Houchard #define	cpu_tlb_flushI()	cpufuncs.cf_tlb_flushI()
1776fc729afSOlivier Houchard #define	cpu_tlb_flushI_SE(e)	cpufuncs.cf_tlb_flushI_SE(e)
1786fc729afSOlivier Houchard #define	cpu_tlb_flushD()	cpufuncs.cf_tlb_flushD()
1796fc729afSOlivier Houchard #define	cpu_tlb_flushD_SE(e)	cpufuncs.cf_tlb_flushD_SE(e)
1806fc729afSOlivier Houchard 
1816fc729afSOlivier Houchard #define	cpu_icache_sync_all()	cpufuncs.cf_icache_sync_all()
1826fc729afSOlivier Houchard #define	cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
1836fc729afSOlivier Houchard 
1846fc729afSOlivier Houchard #define	cpu_dcache_wbinv_all()	cpufuncs.cf_dcache_wbinv_all()
1856fc729afSOlivier Houchard #define	cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
1866fc729afSOlivier Houchard #define	cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
1876fc729afSOlivier Houchard #define	cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
1886fc729afSOlivier Houchard 
1896fc729afSOlivier Houchard #define	cpu_idcache_wbinv_all()	cpufuncs.cf_idcache_wbinv_all()
1906fc729afSOlivier Houchard #define	cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
1916fc729afSOlivier Houchard 
1926fc729afSOlivier Houchard #define	cpu_flush_prefetchbuf()	cpufuncs.cf_flush_prefetchbuf()
1936fc729afSOlivier Houchard #define	cpu_drain_writebuf()	cpufuncs.cf_drain_writebuf()
1946fc729afSOlivier Houchard #define	cpu_flush_brnchtgt_C()	cpufuncs.cf_flush_brnchtgt_C()
1956fc729afSOlivier Houchard #define	cpu_flush_brnchtgt_E(e)	cpufuncs.cf_flush_brnchtgt_E(e)
1966fc729afSOlivier Houchard 
1976fc729afSOlivier Houchard #define cpu_sleep(m)		cpufuncs.cf_sleep(m)
1986fc729afSOlivier Houchard 
1996fc729afSOlivier Houchard #define cpu_dataabt_fixup(a)		cpufuncs.cf_dataabt_fixup(a)
2006fc729afSOlivier Houchard #define cpu_prefetchabt_fixup(a)	cpufuncs.cf_prefetchabt_fixup(a)
2016fc729afSOlivier Houchard #define ABORT_FIXUP_OK		0	/* fixup succeeded */
2026fc729afSOlivier Houchard #define ABORT_FIXUP_FAILED	1	/* fixup failed */
2036fc729afSOlivier Houchard #define ABORT_FIXUP_RETURN	2	/* abort handler should return */
2046fc729afSOlivier Houchard 
2056fc729afSOlivier Houchard #define cpu_setup(a)			cpufuncs.cf_setup(a)
2066fc729afSOlivier Houchard 
2076fc729afSOlivier Houchard int	set_cpufuncs		(void);
2086fc729afSOlivier Houchard #define ARCHITECTURE_NOT_PRESENT	1	/* known but not configured */
2096fc729afSOlivier Houchard #define ARCHITECTURE_NOT_SUPPORTED	2	/* not known */
2106fc729afSOlivier Houchard 
2116fc729afSOlivier Houchard void	cpufunc_nullop		(void);
2126fc729afSOlivier Houchard int	cpufunc_null_fixup	(void *);
2136fc729afSOlivier Houchard int	early_abort_fixup	(void *);
2146fc729afSOlivier Houchard int	late_abort_fixup	(void *);
2156fc729afSOlivier Houchard u_int	cpufunc_id		(void);
2166fc729afSOlivier Houchard u_int	cpufunc_control		(u_int clear, u_int bic);
2176fc729afSOlivier Houchard void	cpufunc_domains		(u_int domains);
2186fc729afSOlivier Houchard u_int	cpufunc_faultstatus	(void);
2196fc729afSOlivier Houchard u_int	cpufunc_faultaddress	(void);
2206fc729afSOlivier Houchard 
2216fc729afSOlivier Houchard #ifdef CPU_ARM3
2226fc729afSOlivier Houchard u_int	arm3_control		(u_int clear, u_int bic);
2236fc729afSOlivier Houchard void	arm3_cache_flush	(void);
2246fc729afSOlivier Houchard #endif	/* CPU_ARM3 */
2256fc729afSOlivier Houchard 
2266fc729afSOlivier Houchard #if defined(CPU_ARM6) || defined(CPU_ARM7)
2276fc729afSOlivier Houchard void	arm67_setttb		(u_int ttb);
2286fc729afSOlivier Houchard void	arm67_tlb_flush		(void);
2296fc729afSOlivier Houchard void	arm67_tlb_purge		(u_int va);
2306fc729afSOlivier Houchard void	arm67_cache_flush	(void);
2316fc729afSOlivier Houchard void	arm67_context_switch	(void);
2326fc729afSOlivier Houchard #endif	/* CPU_ARM6 || CPU_ARM7 */
2336fc729afSOlivier Houchard 
2346fc729afSOlivier Houchard #ifdef CPU_ARM6
2356fc729afSOlivier Houchard void	arm6_setup		(char *string);
2366fc729afSOlivier Houchard #endif	/* CPU_ARM6 */
2376fc729afSOlivier Houchard 
2386fc729afSOlivier Houchard #ifdef CPU_ARM7
2396fc729afSOlivier Houchard void	arm7_setup		(char *string);
2406fc729afSOlivier Houchard #endif	/* CPU_ARM7 */
2416fc729afSOlivier Houchard 
2426fc729afSOlivier Houchard #ifdef CPU_ARM7TDMI
2436fc729afSOlivier Houchard int	arm7_dataabt_fixup	(void *arg);
2446fc729afSOlivier Houchard void	arm7tdmi_setup		(char *string);
2456fc729afSOlivier Houchard void	arm7tdmi_setttb		(u_int ttb);
2466fc729afSOlivier Houchard void	arm7tdmi_tlb_flushID	(void);
2476fc729afSOlivier Houchard void	arm7tdmi_tlb_flushID_SE	(u_int va);
2486fc729afSOlivier Houchard void	arm7tdmi_cache_flushID	(void);
2496fc729afSOlivier Houchard void	arm7tdmi_context_switch	(void);
2506fc729afSOlivier Houchard #endif /* CPU_ARM7TDMI */
2516fc729afSOlivier Houchard 
2526fc729afSOlivier Houchard #ifdef CPU_ARM8
2536fc729afSOlivier Houchard void	arm8_setttb		(u_int ttb);
2546fc729afSOlivier Houchard void	arm8_tlb_flushID	(void);
2556fc729afSOlivier Houchard void	arm8_tlb_flushID_SE	(u_int va);
2566fc729afSOlivier Houchard void	arm8_cache_flushID	(void);
2576fc729afSOlivier Houchard void	arm8_cache_flushID_E	(u_int entry);
2586fc729afSOlivier Houchard void	arm8_cache_cleanID	(void);
2596fc729afSOlivier Houchard void	arm8_cache_cleanID_E	(u_int entry);
2606fc729afSOlivier Houchard void	arm8_cache_purgeID	(void);
2616fc729afSOlivier Houchard void	arm8_cache_purgeID_E	(u_int entry);
2626fc729afSOlivier Houchard 
2636fc729afSOlivier Houchard void	arm8_cache_syncI	(void);
2646fc729afSOlivier Houchard void	arm8_cache_cleanID_rng	(vm_offset_t start, vm_size_t end);
2656fc729afSOlivier Houchard void	arm8_cache_cleanD_rng	(vm_offset_t start, vm_size_t end);
2666fc729afSOlivier Houchard void	arm8_cache_purgeID_rng	(vm_offset_t start, vm_size_t end);
2676fc729afSOlivier Houchard void	arm8_cache_purgeD_rng	(vm_offset_t start, vm_size_t end);
2686fc729afSOlivier Houchard void	arm8_cache_syncI_rng	(vm_offset_t start, vm_size_t end);
2696fc729afSOlivier Houchard 
2706fc729afSOlivier Houchard void	arm8_context_switch	(void);
2716fc729afSOlivier Houchard 
2726fc729afSOlivier Houchard void	arm8_setup		(char *string);
2736fc729afSOlivier Houchard 
2746fc729afSOlivier Houchard u_int	arm8_clock_config	(u_int, u_int);
2756fc729afSOlivier Houchard #endif
2766fc729afSOlivier Houchard 
2776fc729afSOlivier Houchard #ifdef CPU_SA110
2786fc729afSOlivier Houchard void	sa110_setup		(char *string);
2796fc729afSOlivier Houchard void	sa110_context_switch	(void);
2806fc729afSOlivier Houchard #endif	/* CPU_SA110 */
2816fc729afSOlivier Houchard 
2826fc729afSOlivier Houchard #if defined(CPU_SA1100) || defined(CPU_SA1110)
2836fc729afSOlivier Houchard void	sa11x0_drain_readbuf	(void);
2846fc729afSOlivier Houchard 
2856fc729afSOlivier Houchard void	sa11x0_context_switch	(void);
2866fc729afSOlivier Houchard void	sa11x0_cpu_sleep	(int mode);
2876fc729afSOlivier Houchard 
2886fc729afSOlivier Houchard void	sa11x0_setup		(char *string);
2896fc729afSOlivier Houchard #endif
2906fc729afSOlivier Houchard 
2916fc729afSOlivier Houchard #if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
2926fc729afSOlivier Houchard void	sa1_setttb		(u_int ttb);
2936fc729afSOlivier Houchard 
2946fc729afSOlivier Houchard void	sa1_tlb_flushID_SE	(u_int va);
2956fc729afSOlivier Houchard 
2966fc729afSOlivier Houchard void	sa1_cache_flushID	(void);
2976fc729afSOlivier Houchard void	sa1_cache_flushI	(void);
2986fc729afSOlivier Houchard void	sa1_cache_flushD	(void);
2996fc729afSOlivier Houchard void	sa1_cache_flushD_SE	(u_int entry);
3006fc729afSOlivier Houchard 
3016fc729afSOlivier Houchard void	sa1_cache_cleanID	(void);
3026fc729afSOlivier Houchard void	sa1_cache_cleanD	(void);
3036fc729afSOlivier Houchard void	sa1_cache_cleanD_E	(u_int entry);
3046fc729afSOlivier Houchard 
3056fc729afSOlivier Houchard void	sa1_cache_purgeID	(void);
3066fc729afSOlivier Houchard void	sa1_cache_purgeID_E	(u_int entry);
3076fc729afSOlivier Houchard void	sa1_cache_purgeD	(void);
3086fc729afSOlivier Houchard void	sa1_cache_purgeD_E	(u_int entry);
3096fc729afSOlivier Houchard 
3106fc729afSOlivier Houchard void	sa1_cache_syncI		(void);
3116fc729afSOlivier Houchard void	sa1_cache_cleanID_rng	(vm_offset_t start, vm_size_t end);
3126fc729afSOlivier Houchard void	sa1_cache_cleanD_rng	(vm_offset_t start, vm_size_t end);
3136fc729afSOlivier Houchard void	sa1_cache_purgeID_rng	(vm_offset_t start, vm_size_t end);
3146fc729afSOlivier Houchard void	sa1_cache_purgeD_rng	(vm_offset_t start, vm_size_t end);
3156fc729afSOlivier Houchard void	sa1_cache_syncI_rng	(vm_offset_t start, vm_size_t end);
3166fc729afSOlivier Houchard 
3176fc729afSOlivier Houchard #endif
3186fc729afSOlivier Houchard 
3196fc729afSOlivier Houchard #ifdef CPU_ARM9
3206fc729afSOlivier Houchard void	arm9_setttb		(u_int);
3216fc729afSOlivier Houchard 
3226fc729afSOlivier Houchard void	arm9_tlb_flushID_SE	(u_int va);
3236fc729afSOlivier Houchard 
3246fc729afSOlivier Houchard void	arm9_cache_flushID	(void);
3256fc729afSOlivier Houchard void	arm9_cache_flushID_SE	(u_int);
3266fc729afSOlivier Houchard void	arm9_cache_flushI	(void);
3276fc729afSOlivier Houchard void	arm9_cache_flushI_SE	(u_int);
3286fc729afSOlivier Houchard void	arm9_cache_flushD	(void);
3296fc729afSOlivier Houchard void	arm9_cache_flushD_SE	(u_int);
3306fc729afSOlivier Houchard 
3316fc729afSOlivier Houchard void	arm9_cache_cleanID	(void);
3326fc729afSOlivier Houchard 
3336fc729afSOlivier Houchard void	arm9_cache_syncI	(void);
3346fc729afSOlivier Houchard void	arm9_cache_flushID_rng	(vm_offset_t, vm_size_t);
3356fc729afSOlivier Houchard void	arm9_cache_flushD_rng	(vm_offset_t, vm_size_t);
3366fc729afSOlivier Houchard void	arm9_cache_syncI_rng	(vm_offset_t, vm_size_t);
3376fc729afSOlivier Houchard 
3386fc729afSOlivier Houchard void	arm9_context_switch	(void);
3396fc729afSOlivier Houchard 
3406fc729afSOlivier Houchard void	arm9_setup		(char *string);
3416fc729afSOlivier Houchard #endif
3426fc729afSOlivier Houchard 
3436fc729afSOlivier Houchard #ifdef CPU_ARM10
3446fc729afSOlivier Houchard void	arm10_setttb		(u_int);
3456fc729afSOlivier Houchard 
3466fc729afSOlivier Houchard void	arm10_tlb_flushID_SE	(u_int);
3476fc729afSOlivier Houchard void	arm10_tlb_flushI_SE	(u_int);
3486fc729afSOlivier Houchard 
3496fc729afSOlivier Houchard void	arm10_icache_sync_all	(void);
3506fc729afSOlivier Houchard void	arm10_icache_sync_range	(vm_offset_t, vm_size_t);
3516fc729afSOlivier Houchard 
3526fc729afSOlivier Houchard void	arm10_dcache_wbinv_all	(void);
3536fc729afSOlivier Houchard void	arm10_dcache_wbinv_range (vm_offset_t, vm_size_t);
3546fc729afSOlivier Houchard void	arm10_dcache_inv_range	(vm_offset_t, vm_size_t);
3556fc729afSOlivier Houchard void	arm10_dcache_wb_range	(vm_offset_t, vm_size_t);
3566fc729afSOlivier Houchard 
3576fc729afSOlivier Houchard void	arm10_idcache_wbinv_all	(void);
3586fc729afSOlivier Houchard void	arm10_idcache_wbinv_range (vm_offset_t, vm_size_t);
3596fc729afSOlivier Houchard 
3606fc729afSOlivier Houchard void	arm10_context_switch	(void);
3616fc729afSOlivier Houchard 
3626fc729afSOlivier Houchard void	arm10_setup		(char *string);
3636fc729afSOlivier Houchard 
3646fc729afSOlivier Houchard extern unsigned arm10_dcache_sets_max;
3656fc729afSOlivier Houchard extern unsigned arm10_dcache_sets_inc;
3666fc729afSOlivier Houchard extern unsigned arm10_dcache_index_max;
3676fc729afSOlivier Houchard extern unsigned arm10_dcache_index_inc;
3686fc729afSOlivier Houchard #endif
3696fc729afSOlivier Houchard 
3706fc729afSOlivier Houchard #if defined(CPU_ARM9) || defined(CPU_ARM10) || defined(CPU_SA110) || \
3716fc729afSOlivier Houchard     defined(CPU_SA1100) || defined(CPU_SA1110) || \
3726fc729afSOlivier Houchard     defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
3736fc729afSOlivier Houchard     defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
3746fc729afSOlivier Houchard 
3756fc729afSOlivier Houchard void	armv4_tlb_flushID	(void);
3766fc729afSOlivier Houchard void	armv4_tlb_flushI	(void);
3776fc729afSOlivier Houchard void	armv4_tlb_flushD	(void);
3786fc729afSOlivier Houchard void	armv4_tlb_flushD_SE	(u_int va);
3796fc729afSOlivier Houchard 
3806fc729afSOlivier Houchard void	armv4_drain_writebuf	(void);
3816fc729afSOlivier Houchard #endif
3826fc729afSOlivier Houchard 
3836fc729afSOlivier Houchard #if defined(CPU_IXP12X0)
3846fc729afSOlivier Houchard void	ixp12x0_drain_readbuf	(void);
3856fc729afSOlivier Houchard void	ixp12x0_context_switch	(void);
3866fc729afSOlivier Houchard void	ixp12x0_setup		(char *string);
3876fc729afSOlivier Houchard #endif
3886fc729afSOlivier Houchard 
3896fc729afSOlivier Houchard #if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
3906fc729afSOlivier Houchard     defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
3916fc729afSOlivier Houchard void	xscale_cpwait		(void);
3926fc729afSOlivier Houchard 
3936fc729afSOlivier Houchard void	xscale_cpu_sleep	(int mode);
3946fc729afSOlivier Houchard 
3956fc729afSOlivier Houchard u_int	xscale_control		(u_int clear, u_int bic);
3966fc729afSOlivier Houchard 
3976fc729afSOlivier Houchard void	xscale_setttb		(u_int ttb);
3986fc729afSOlivier Houchard 
3996fc729afSOlivier Houchard void	xscale_tlb_flushID_SE	(u_int va);
4006fc729afSOlivier Houchard 
4016fc729afSOlivier Houchard void	xscale_cache_flushID	(void);
4026fc729afSOlivier Houchard void	xscale_cache_flushI	(void);
4036fc729afSOlivier Houchard void	xscale_cache_flushD	(void);
4046fc729afSOlivier Houchard void	xscale_cache_flushD_SE	(u_int entry);
4056fc729afSOlivier Houchard 
4066fc729afSOlivier Houchard void	xscale_cache_cleanID	(void);
4076fc729afSOlivier Houchard void	xscale_cache_cleanD	(void);
4086fc729afSOlivier Houchard void	xscale_cache_cleanD_E	(u_int entry);
4096fc729afSOlivier Houchard 
4106fc729afSOlivier Houchard void	xscale_cache_clean_minidata (void);
4116fc729afSOlivier Houchard 
4126fc729afSOlivier Houchard void	xscale_cache_purgeID	(void);
4136fc729afSOlivier Houchard void	xscale_cache_purgeID_E	(u_int entry);
4146fc729afSOlivier Houchard void	xscale_cache_purgeD	(void);
4156fc729afSOlivier Houchard void	xscale_cache_purgeD_E	(u_int entry);
4166fc729afSOlivier Houchard 
4176fc729afSOlivier Houchard void	xscale_cache_syncI	(void);
4186fc729afSOlivier Houchard void	xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
4196fc729afSOlivier Houchard void	xscale_cache_cleanD_rng	(vm_offset_t start, vm_size_t end);
4206fc729afSOlivier Houchard void	xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
4216fc729afSOlivier Houchard void	xscale_cache_purgeD_rng	(vm_offset_t start, vm_size_t end);
4226fc729afSOlivier Houchard void	xscale_cache_syncI_rng	(vm_offset_t start, vm_size_t end);
4236fc729afSOlivier Houchard void	xscale_cache_flushD_rng	(vm_offset_t start, vm_size_t end);
4246fc729afSOlivier Houchard 
4256fc729afSOlivier Houchard void	xscale_context_switch	(void);
4266fc729afSOlivier Houchard 
4276fc729afSOlivier Houchard void	xscale_setup		(char *string);
4286fc729afSOlivier Houchard #endif	/* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
4296fc729afSOlivier Houchard 
4306fc729afSOlivier Houchard #define tlb_flush	cpu_tlb_flushID
4316fc729afSOlivier Houchard #define setttb		cpu_setttb
4326fc729afSOlivier Houchard #define drain_writebuf	cpu_drain_writebuf
4336fc729afSOlivier Houchard 
4346fc729afSOlivier Houchard /*
4356fc729afSOlivier Houchard  * Macros for manipulating CPU interrupts
4366fc729afSOlivier Houchard  */
4376fc729afSOlivier Houchard static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__));
4386fc729afSOlivier Houchard 
4396fc729afSOlivier Houchard static __inline u_int32_t
4406fc729afSOlivier Houchard __set_cpsr_c(u_int bic, u_int eor)
4416fc729afSOlivier Houchard {
4426fc729afSOlivier Houchard 	u_int32_t	tmp, ret;
4436fc729afSOlivier Houchard 
4446fc729afSOlivier Houchard 	__asm __volatile(
4456fc729afSOlivier Houchard 		"mrs     %0, cpsr\n"	/* Get the CPSR */
4466fc729afSOlivier Houchard 		"bic	 %1, %0, %2\n"	/* Clear bits */
4476fc729afSOlivier Houchard 		"eor	 %1, %1, %3\n"	/* XOR bits */
4486fc729afSOlivier Houchard 		"msr     cpsr_c, %1\n"	/* Set the control field of CPSR */
4496fc729afSOlivier Houchard 	: "=&r" (ret), "=&r" (tmp)
45024e01b0cSOlivier Houchard 	: "r" (bic), "r" (eor) : "memory");
4516fc729afSOlivier Houchard 
4526fc729afSOlivier Houchard 	return ret;
4536fc729afSOlivier Houchard }
4546fc729afSOlivier Houchard 
4556fc729afSOlivier Houchard #define disable_interrupts(mask)					\
4566fc729afSOlivier Houchard 	(__set_cpsr_c((mask) & (I32_bit | F32_bit), \
4576fc729afSOlivier Houchard 		      (mask) & (I32_bit | F32_bit)))
4586fc729afSOlivier Houchard 
4596fc729afSOlivier Houchard #define enable_interrupts(mask)						\
46024e01b0cSOlivier Houchard 	(__set_cpsr_c((mask | F32_bit) & (I32_bit | F32_bit), 0))
4616fc729afSOlivier Houchard 
4626fc729afSOlivier Houchard #define restore_interrupts(old_cpsr)					\
4636fc729afSOlivier Houchard 	(__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))
4646fc729afSOlivier Houchard 
46524e01b0cSOlivier Houchard #define intr_disable()	\
46624e01b0cSOlivier Houchard     disable_interrupts(I32_bit | F32_bit)
46724e01b0cSOlivier Houchard #define intr_restore(s)	\
46824e01b0cSOlivier Houchard     restore_interrupts(s)
4696fc729afSOlivier Houchard /* Functions to manipulate the CPSR. */
4706fc729afSOlivier Houchard u_int	SetCPSR(u_int bic, u_int eor);
4716fc729afSOlivier Houchard u_int	GetCPSR(void);
4726fc729afSOlivier Houchard 
4736fc729afSOlivier Houchard /*
4746fc729afSOlivier Houchard  * Functions to manipulate cpu r13
4756fc729afSOlivier Houchard  * (in arm/arm32/setstack.S)
4766fc729afSOlivier Houchard  */
4776fc729afSOlivier Houchard 
4786fc729afSOlivier Houchard void set_stackptr	__P((u_int mode, u_int address));
4796fc729afSOlivier Houchard u_int get_stackptr	__P((u_int mode));
4806fc729afSOlivier Houchard 
4816fc729afSOlivier Houchard /*
4826fc729afSOlivier Houchard  * Miscellany
4836fc729afSOlivier Houchard  */
4846fc729afSOlivier Houchard 
4856fc729afSOlivier Houchard int get_pc_str_offset	__P((void));
4866fc729afSOlivier Houchard 
4876fc729afSOlivier Houchard /*
4886fc729afSOlivier Houchard  * CPU functions from locore.S
4896fc729afSOlivier Houchard  */
4906fc729afSOlivier Houchard 
4916fc729afSOlivier Houchard void cpu_reset		__P((void)) __attribute__((__noreturn__));
4926fc729afSOlivier Houchard 
4936fc729afSOlivier Houchard /*
4946fc729afSOlivier Houchard  * Cache info variables.
4956fc729afSOlivier Houchard  */
4966fc729afSOlivier Houchard 
4976fc729afSOlivier Houchard /* PRIMARY CACHE VARIABLES */
4986fc729afSOlivier Houchard extern int	arm_picache_size;
4996fc729afSOlivier Houchard extern int	arm_picache_line_size;
5006fc729afSOlivier Houchard extern int	arm_picache_ways;
5016fc729afSOlivier Houchard 
5026fc729afSOlivier Houchard extern int	arm_pdcache_size;	/* and unified */
5036fc729afSOlivier Houchard extern int	arm_pdcache_line_size;
5046fc729afSOlivier Houchard extern int	arm_pdcache_ways;
5056fc729afSOlivier Houchard 
5066fc729afSOlivier Houchard extern int	arm_pcache_type;
5076fc729afSOlivier Houchard extern int	arm_pcache_unified;
5086fc729afSOlivier Houchard 
5096fc729afSOlivier Houchard extern int	arm_dcache_align;
5106fc729afSOlivier Houchard extern int	arm_dcache_align_mask;
5116fc729afSOlivier Houchard 
5126fc729afSOlivier Houchard #endif	/* _KERNEL */
5136fc729afSOlivier Houchard #endif	/* _MACHINE_CPUFUNC_H_ */
5146fc729afSOlivier Houchard 
5156fc729afSOlivier Houchard /* End of cpufunc.h */
516