1 /* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */ 2 3 /* 4 * Copyright (C) 2003-2004 Olivier Houchard 5 * Copyright (C) 1994-1997 Mark Brinicombe 6 * Copyright (C) 1994 Brini 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of Brini may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 31 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 33 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 34 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * $FreeBSD$ 37 */ 38 39 #ifndef _MACHINE_ATOMIC_H_ 40 #define _MACHINE_ATOMIC_H_ 41 42 43 44 #ifndef _LOCORE 45 46 #include <sys/types.h> 47 48 #ifndef I32_bit 49 #define I32_bit (1 << 7) /* IRQ disable */ 50 #endif 51 #ifndef F32_bit 52 #define F32_bit (1 << 6) /* FIQ disable */ 53 #endif 54 55 #define __with_interrupts_disabled(expr) \ 56 do { \ 57 u_int cpsr_save, tmp; \ 58 \ 59 __asm __volatile( \ 60 "mrs %0, cpsr;" \ 61 "orr %1, %0, %2;" \ 62 "msr cpsr_all, %1;" \ 63 : "=r" (cpsr_save), "=r" (tmp) \ 64 : "I" (I32_bit) \ 65 : "cc" ); \ 66 (expr); \ 67 __asm __volatile( \ 68 "msr cpsr_all, %0" \ 69 : /* no output */ \ 70 : "r" (cpsr_save) \ 71 : "cc" ); \ 72 } while(0) 73 74 static __inline void 75 atomic_set_32(volatile uint32_t *address, uint32_t setmask) 76 { 77 __with_interrupts_disabled( *address |= setmask); 78 } 79 80 static __inline void 81 atomic_set_ptr(volatile void *ptr, uint32_t src) 82 { 83 atomic_set_32((volatile uint32_t *)ptr, (uint32_t)src); 84 } 85 86 #define atomic_set_rel_int atomic_set_32 87 #define atomic_set_int atomic_set_32 88 #define atomic_readandclear_int atomic_readandclear_32 89 static __inline void 90 atomic_clear_32(volatile uint32_t *address, uint32_t clearmask) 91 { 92 __with_interrupts_disabled( *address &= ~clearmask); 93 } 94 95 static __inline void 96 atomic_clear_ptr(volatile void *ptr, uint32_t src) 97 { 98 atomic_clear_32((volatile uint32_t *)ptr, (uint32_t)src); 99 } 100 101 static __inline int 102 atomic_load_acq_int(volatile uint32_t *v) 103 { 104 int bla; 105 106 __with_interrupts_disabled(bla = *v); 107 return (bla); 108 } 109 110 #define atomic_clear_int atomic_clear_32 111 static __inline void 112 atomic_store_32(volatile uint32_t *dst, uint32_t src) 113 { 114 __with_interrupts_disabled(*dst = src); 115 } 116 117 static __inline void 118 atomic_store_ptr(volatile void *dst, void *src) 119 { 120 atomic_store_32((volatile uint32_t *)dst, (uint32_t) src); 121 } 122 123 #define atomic_store_rel_ptr atomic_store_ptr 124 #define atomic_store_rel_int atomic_store_32 125 126 static __inline uint32_t 127 atomic_readandclear_32(volatile u_int32_t *p) 128 { 129 uint32_t ret; 130 131 __with_interrupts_disabled((ret = *p) != 0 ? *p = 0 : 0); 132 return (ret); 133 } 134 135 static __inline u_int32_t 136 atomic_cmpset_32(volatile u_int32_t *p, u_int32_t cmpval, u_int32_t newval) 137 { 138 int done = 0; 139 __with_interrupts_disabled(*p = (*p == cmpval ? newval + done++ : *p)); 140 return (done); 141 } 142 143 static __inline void 144 atomic_add_32(volatile u_int32_t *p, u_int32_t val) 145 { 146 __with_interrupts_disabled(*p += val); 147 } 148 149 static __inline void 150 atomic_subtract_32(volatile u_int32_t *p, u_int32_t val) 151 { 152 __with_interrupts_disabled(*p -= val); 153 } 154 155 #define atomic_subtract_int atomic_subtract_32 156 #define atomic_subtract_rel_int atomic_subtract_32 157 #define atomic_subtract_acq_int atomic_subtract_32 158 #define atomic_add_int atomic_add_32 159 #define atomic_add_rel_int atomic_add_32 160 #define atomic_add_acq_int atomic_add_32 161 #define atomic_cmpset_int atomic_cmpset_32 162 #define atomic_cmpset_rel_int atomic_cmpset_32 163 #define atomic_cmpset_acq_int atomic_cmpset_32 164 165 static __inline u_int32_t 166 atomic_cmpset_ptr(volatile void *dst, void *exp, void *src) 167 { 168 return (atomic_cmpset_32((volatile u_int32_t *)dst, (u_int32_t)exp, 169 (u_int32_t)src)); 170 } 171 172 static __inline u_int32_t 173 atomic_cmpset_rel_32(volatile u_int32_t *p, u_int32_t cmpval, u_int32_t newval) 174 { 175 return (atomic_cmpset_32(p, cmpval, newval)); 176 } 177 178 static __inline u_int32_t 179 atomic_cmpset_rel_ptr(volatile void *dst, void *exp, void *src) 180 { 181 return (atomic_cmpset_32((volatile u_int32_t *)dst, 182 (u_int32_t)exp, (u_int32_t)src)); 183 } 184 185 #define atomic_cmpset_acq_ptr atomic_cmpset_ptr 186 187 #if !defined(ATOMIC_SET_BIT_NOINLINE) 188 189 #define atomic_set_bit(a,m) atomic_set_32(a,m) 190 #define atomic_clear_bit(a,m) atomic_clear_32(a,m) 191 192 #endif 193 194 #undef __with_interrupts_disabled 195 196 #endif /* _LOCORE */ 197 #endif /* _MACHINE_ATOMIC_H_ */ 198