1 /* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */ 2 3 /*- 4 * Copyright (C) 2003-2004 Olivier Houchard 5 * Copyright (C) 1994-1997 Mark Brinicombe 6 * Copyright (C) 1994 Brini 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of Brini may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 31 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 33 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 34 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * $FreeBSD$ 37 */ 38 39 #ifndef _MACHINE_ATOMIC_H_ 40 #define _MACHINE_ATOMIC_H_ 41 42 43 44 #ifndef _LOCORE 45 46 #include <sys/types.h> 47 48 #ifndef I32_bit 49 #define I32_bit (1 << 7) /* IRQ disable */ 50 #endif 51 #ifndef F32_bit 52 #define F32_bit (1 << 6) /* FIQ disable */ 53 #endif 54 55 #define __with_interrupts_disabled(expr) \ 56 do { \ 57 u_int cpsr_save, tmp; \ 58 \ 59 __asm __volatile( \ 60 "mrs %0, cpsr;" \ 61 "orr %1, %0, %2;" \ 62 "msr cpsr_all, %1;" \ 63 : "=r" (cpsr_save), "=r" (tmp) \ 64 : "I" (I32_bit) \ 65 : "cc" ); \ 66 (expr); \ 67 __asm __volatile( \ 68 "msr cpsr_all, %0" \ 69 : /* no output */ \ 70 : "r" (cpsr_save) \ 71 : "cc" ); \ 72 } while(0) 73 74 #define ARM_RAS_START 0xe0000004 75 #define ARM_RAS_END 0xe0000008 76 77 static __inline uint32_t 78 __swp(uint32_t val, volatile uint32_t *ptr) 79 { 80 __asm __volatile("swp %0, %1, [%2]" 81 : "=&r" (val) : "r" (val) , "r" (ptr) : "memory"); 82 return (val); 83 } 84 85 86 #ifdef _KERNEL 87 static __inline void 88 atomic_set_32(volatile uint32_t *address, uint32_t setmask) 89 { 90 __with_interrupts_disabled(*address |= setmask); 91 } 92 93 static __inline void 94 atomic_clear_32(volatile uint32_t *address, uint32_t clearmask) 95 { 96 __with_interrupts_disabled(*address &= ~clearmask); 97 } 98 99 static __inline u_int32_t 100 atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval) 101 { 102 int ret; 103 104 __with_interrupts_disabled( 105 { 106 if (*p == cmpval) { 107 *p = newval; 108 ret = 1; 109 } else { 110 ret = 0; 111 } 112 }); 113 return (ret); 114 } 115 116 static __inline void 117 atomic_add_32(volatile u_int32_t *p, u_int32_t val) 118 { 119 __with_interrupts_disabled(*p += val); 120 } 121 122 static __inline void 123 atomic_subtract_32(volatile u_int32_t *p, u_int32_t val) 124 { 125 __with_interrupts_disabled(*p -= val); 126 } 127 128 #else /* !_KERNEL */ 129 130 static __inline u_int32_t 131 atomic_cmpset_32(volatile u_int32_t *p, volatile u_int32_t cmpval, volatile u_int32_t newval) 132 { 133 register int done, ras_start; 134 135 __asm __volatile("1:\n" 136 "mov %0, #0xe0000008\n" 137 "adr %1, 2f\n" 138 "str %1, [%0]\n" 139 "adr %1, 1b\n" 140 "mov %0, #0xe0000004\n" 141 "str %1, [%0]\n" 142 "ldr %1, [%2]\n" 143 "cmp %1, %3\n" 144 "streq %4, [%2]\n" 145 "2:\n" 146 "moveq %1, #1\n" 147 "movne %1, #0\n" 148 : "=r" (ras_start), "=r" (done) 149 ,"+r" (p), "+r" (cmpval), "+r" (newval)); 150 return (done); 151 } 152 153 static __inline void 154 atomic_add_32(volatile u_int32_t *p, u_int32_t val) 155 { 156 int ras_start, start; 157 158 __asm __volatile("1:\n" 159 "mov %0, #0xe0000008\n" 160 "adr %1, 2f\n" 161 "str %1, [%0]\n" 162 "adr %1, 1b\n" 163 "mov %0, #0xe0000004\n" 164 "str %1, [%0]\n" 165 "ldr %1, [%2]\n" 166 "add %1, %1, %3\n" 167 "str %1, [%2]\n" 168 "2:\n" 169 : "=r" (ras_start), "=r" (start), "+r" (p), "+r" (val)); 170 } 171 172 static __inline void 173 atomic_subtract_32(volatile u_int32_t *p, u_int32_t val) 174 { 175 int ras_start, start; 176 177 __asm __volatile("1:\n" 178 "mov %0, #0xe0000008\n" 179 "adr %1, 2f\n" 180 "str %1, [%0]\n" 181 "adr %1, 1b\n" 182 "mov %0, #0xe0000004\n" 183 "str %1, [%0]\n" 184 "ldr %1, [%2]\n" 185 "sub %1, %1, %3\n" 186 "str %1, [%2]\n" 187 "2:\n" 188 : "=r" (ras_start), "=r" (start), "+r" (p), "+r" (val)); 189 } 190 191 static __inline void 192 atomic_set_32(volatile uint32_t *address, uint32_t setmask) 193 { 194 int ras_start, start; 195 196 __asm __volatile("1:\n" 197 "mov %0, #0xe0000008\n" 198 "adr %1, 2f\n" 199 "str %1, [%0]\n" 200 "adr %1, 1b\n" 201 "mov %0, #0xe0000004\n" 202 "str %1, [%0]\n" 203 "ldr %1, [%2]\n" 204 "orr %1, %1, %3\n" 205 "str %1, [%2]\n" 206 "2:\n" 207 : "=r" (ras_start), "=r" (start), "+r" (address), "+r" (setmask)); 208 } 209 210 static __inline void 211 atomic_clear_32(volatile uint32_t *address, uint32_t clearmask) 212 { 213 int ras_start, start; 214 215 __asm __volatile("1:\n" 216 "mov %0, #0xe0000008\n" 217 "adr %1, 2f\n" 218 "str %1, [%0]\n" 219 "adr %1, 1b\n" 220 "mov %0, #0xe0000004\n" 221 "str %1, [%0]\n" 222 "ldr %1, [%2]\n" 223 "bic %1, %1, %3\n" 224 "str %1, [%2]\n" 225 "2:\n" 226 : "=r" (ras_start), "=r" (start), "+r" (address), "+r" (clearmask)); 227 228 } 229 #endif /* _KERNEL */ 230 231 static __inline int 232 atomic_load_32(volatile uint32_t *v) 233 { 234 235 return (*v); 236 } 237 238 static __inline void 239 atomic_store_32(volatile uint32_t *dst, uint32_t src) 240 { 241 *dst = src; 242 } 243 244 static __inline uint32_t 245 atomic_readandclear_32(volatile u_int32_t *p) 246 { 247 248 return (__swp(0, p)); 249 } 250 251 #undef __with_interrupts_disabled 252 253 #endif /* _LOCORE */ 254 255 256 #define atomic_set_rel_int atomic_set_32 257 #define atomic_set_int atomic_set_32 258 #define atomic_readandclear_int atomic_readandclear_32 259 #define atomic_clear_int atomic_clear_32 260 #define atomic_subtract_int atomic_subtract_32 261 #define atomic_subtract_rel_int atomic_subtract_32 262 #define atomic_subtract_acq_int atomic_subtract_32 263 #define atomic_add_int atomic_add_32 264 #define atomic_add_rel_int atomic_add_32 265 #define atomic_add_acq_int atomic_add_32 266 #define atomic_cmpset_int atomic_cmpset_32 267 #define atomic_cmpset_rel_int atomic_cmpset_32 268 #define atomic_cmpset_rel_ptr atomic_cmpset_ptr 269 #define atomic_cmpset_acq_int atomic_cmpset_32 270 #define atomic_cmpset_acq_ptr atomic_cmpset_ptr 271 #define atomic_store_rel_ptr atomic_store_ptr 272 #define atomic_store_rel_int atomic_store_32 273 #define atomic_cmpset_rel_32 atomic_cmpset_32 274 #define atomic_smpset_rel_ptr atomic_cmpset_ptr 275 #define atomic_load_acq_int atomic_load_32 276 #define atomic_clear_ptr(ptr, bit) atomic_clear_32( \ 277 (volatile uint32_t *)ptr, (uint32_t)bit) 278 #define atomic_store_ptr(ptr, bit) atomic_store_32( \ 279 (volatile uint32_t *)ptr, (uint32_t)bit) 280 #define atomic_cmpset_ptr(dst, exp, s) atomic_cmpset_32( \ 281 (volatile uint32_t *)dst, (uint32_t)exp, (uint32_t)s) 282 #define atomic_set_ptr(ptr, src) atomic_set_32( \ 283 (volatile uint32_t *)ptr, (uint32_t)src) 284 285 #endif /* _MACHINE_ATOMIC_H_ */ 286