1 /* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * $FreeBSD$ 39 */ 40 41 #ifndef MACHINE_ARMREG_H 42 #define MACHINE_ARMREG_H 43 44 #define INSN_SIZE 4 45 #define INSN_COND_MASK 0xf0000000 /* Condition mask */ 46 #define PSR_MODE 0x0000001f /* mode mask */ 47 #define PSR_USR26_MODE 0x00000000 48 #define PSR_FIQ26_MODE 0x00000001 49 #define PSR_IRQ26_MODE 0x00000002 50 #define PSR_SVC26_MODE 0x00000003 51 #define PSR_USR32_MODE 0x00000010 52 #define PSR_FIQ32_MODE 0x00000011 53 #define PSR_IRQ32_MODE 0x00000012 54 #define PSR_SVC32_MODE 0x00000013 55 #define PSR_ABT32_MODE 0x00000017 56 #define PSR_UND32_MODE 0x0000001b 57 #define PSR_SYS32_MODE 0x0000001f 58 #define PSR_32_MODE 0x00000010 59 #define PSR_FLAGS 0xf0000000 /* flags */ 60 61 #define PSR_C_bit (1 << 29) /* carry */ 62 63 /* The high-order byte is always the implementor */ 64 #define CPU_ID_IMPLEMENTOR_MASK 0xff000000 65 #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 66 #define CPU_ID_DEC 0x44000000 /* 'D' */ 67 #define CPU_ID_INTEL 0x69000000 /* 'i' */ 68 #define CPU_ID_TI 0x54000000 /* 'T' */ 69 #define CPU_ID_FARADAY 0x66000000 /* 'f' */ 70 71 /* How to decide what format the CPUID is in. */ 72 #define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 73 #define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 74 #define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 75 76 /* On ARM3 and ARM6, this byte holds the foundry ID. */ 77 #define CPU_ID_FOUNDRY_MASK 0x00ff0000 78 #define CPU_ID_FOUNDRY_VLSI 0x00560000 79 80 /* On ARM7 it holds the architecture and variant (sub-model) */ 81 #define CPU_ID_7ARCH_MASK 0x00800000 82 #define CPU_ID_7ARCH_V3 0x00000000 83 #define CPU_ID_7ARCH_V4T 0x00800000 84 #define CPU_ID_7VARIANT_MASK 0x007f0000 85 86 /* On more recent ARMs, it does the same, but in a different format */ 87 #define CPU_ID_ARCH_MASK 0x000f0000 88 #define CPU_ID_ARCH_V3 0x00000000 89 #define CPU_ID_ARCH_V4 0x00010000 90 #define CPU_ID_ARCH_V4T 0x00020000 91 #define CPU_ID_ARCH_V5 0x00030000 92 #define CPU_ID_ARCH_V5T 0x00040000 93 #define CPU_ID_ARCH_V5TE 0x00050000 94 #define CPU_ID_ARCH_V5TEJ 0x00060000 95 #define CPU_ID_ARCH_V6 0x00070000 96 #define CPU_ID_CPUID_SCHEME 0x000f0000 97 #define CPU_ID_VARIANT_MASK 0x00f00000 98 99 /* Next three nybbles are part number */ 100 #define CPU_ID_PARTNO_MASK 0x0000fff0 101 102 /* Intel XScale has sub fields in part number */ 103 #define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 104 #define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 105 #define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 106 107 /* And finally, the revision number. */ 108 #define CPU_ID_REVISION_MASK 0x0000000f 109 110 /* Individual CPUs are probably best IDed by everything but the revision. */ 111 #define CPU_ID_CPU_MASK 0xfffffff0 112 113 /* Fake CPU IDs for ARMs without CP15 */ 114 #define CPU_ID_ARM2 0x41560200 115 #define CPU_ID_ARM250 0x41560250 116 117 /* Pre-ARM7 CPUs -- [15:12] == 0 */ 118 #define CPU_ID_ARM3 0x41560300 119 #define CPU_ID_ARM600 0x41560600 120 #define CPU_ID_ARM610 0x41560610 121 #define CPU_ID_ARM620 0x41560620 122 123 /* ARM7 CPUs -- [15:12] == 7 */ 124 #define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 125 #define CPU_ID_ARM710 0x41007100 126 #define CPU_ID_ARM7500 0x41027100 127 #define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ 128 #define CPU_ID_ARM7500FE 0x41077100 129 #define CPU_ID_ARM710T 0x41807100 130 #define CPU_ID_ARM720T 0x41807200 131 #define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 132 #define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 133 134 /* Post-ARM7 CPUs */ 135 #define CPU_ID_ARM810 0x41018100 136 #define CPU_ID_ARM920T 0x41129200 137 #define CPU_ID_ARM920T_ALT 0x41009200 138 #define CPU_ID_ARM922T 0x41029220 139 #define CPU_ID_ARM926EJS 0x41069260 140 #define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 141 #define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 142 #define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 143 #define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 144 #define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 145 #define CPU_ID_ARM1022ES 0x4105a220 146 #define CPU_ID_ARM1026EJS 0x4106a260 147 #define CPU_ID_ARM1136JS 0x4107b360 148 #define CPU_ID_ARM1136JSR1 0x4117b360 149 #define CPU_ID_CORTEXA8R1 0x411fc080 150 #define CPU_ID_CORTEXA8R2 0x412fc080 151 #define CPU_ID_CORTEXA8R3 0x413fc080 152 #define CPU_ID_CORTEXA9R1 0x411fc090 153 #define CPU_ID_CORTEXA9R2 0x412fc090 154 #define CPU_ID_SA110 0x4401a100 155 #define CPU_ID_SA1100 0x4401a110 156 #define CPU_ID_TI925T 0x54029250 157 #define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ 158 #define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */ 159 #define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ 160 161 /* 162 * LokiPlus core has also ID set to 0x41159260 and this define cause execution of unsupported 163 * L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID. 164 */ 165 #ifdef SOC_MV_LOKIPLUS 166 #define CPU_ID_MV88FR571_41 0x00000000 167 #else 168 #define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ 169 #endif 170 171 #define CPU_ID_MV88SV581X_V6 0x560F5810 /* Marvell Sheeva 88SV581x v6 Core */ 172 #define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */ 173 #define CPU_ID_MV88SV584X 0x561F5840 /* Marvell Sheeva 88SV584x v6 Core */ 174 /* Marvell's CPUIDs with ARM ID in implementor field */ 175 #define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */ 176 #define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */ 177 #define CPU_ID_ARM_88SV584X 0x410FB024 /* Marvell Sheeva 88SV584x v6 Core */ 178 179 #define CPU_ID_FA526 0x66015260 180 #define CPU_ID_FA626TE 0x66056260 181 #define CPU_ID_SA1110 0x6901b110 182 #define CPU_ID_IXP1200 0x6901c120 183 #define CPU_ID_80200 0x69052000 184 #define CPU_ID_PXA250 0x69052100 /* sans core revision */ 185 #define CPU_ID_PXA210 0x69052120 186 #define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 187 #define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 188 #define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 189 #define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 190 #define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 191 #define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 192 #define CPU_ID_PXA27X 0x69054110 193 #define CPU_ID_80321_400 0x69052420 194 #define CPU_ID_80321_600 0x69052430 195 #define CPU_ID_80321_400_B0 0x69052c20 196 #define CPU_ID_80321_600_B0 0x69052c30 197 #define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */ 198 #define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */ 199 #define CPU_ID_81342 0x69056810 200 #define CPU_ID_IXP425 0x690541c0 201 #define CPU_ID_IXP425_533 0x690541c0 202 #define CPU_ID_IXP425_400 0x690541d0 203 #define CPU_ID_IXP425_266 0x690541f0 204 #define CPU_ID_IXP435 0x69054040 205 #define CPU_ID_IXP465 0x69054200 206 207 /* ARM3-specific coprocessor 15 registers */ 208 #define ARM3_CP15_FLUSH 1 209 #define ARM3_CP15_CONTROL 2 210 #define ARM3_CP15_CACHEABLE 3 211 #define ARM3_CP15_UPDATEABLE 4 212 #define ARM3_CP15_DISRUPTIVE 5 213 214 /* ARM3 Control register bits */ 215 #define ARM3_CTL_CACHE_ON 0x00000001 216 #define ARM3_CTL_SHARED 0x00000002 217 #define ARM3_CTL_MONITOR 0x00000004 218 219 /* CPUID registers */ 220 #define ARM_PFR0_ARM_ISA_MASK 0x0000000f 221 222 #define ARM_PFR0_THUMB_MASK 0x000000f0 223 #define ARM_PFR0_THUMB 0x10 224 #define ARM_PFR0_THUMB2 0x30 225 226 #define ARM_PFR0_JAZELLE_MASK 0x00000f00 227 #define ARM_PFR0_THUMBEE_MASK 0x0000f000 228 229 #define ARM_PFR1_ARMV4_MASK 0x0000000f 230 #define ARM_PFR1_SEC_EXT_MASK 0x000000f0 231 #define ARM_PFR1_MICROCTRL_MASK 0x00000f00 232 233 /* 234 * Post-ARM3 CP15 registers: 235 * 236 * 1 Control register 237 * 238 * 2 Translation Table Base 239 * 240 * 3 Domain Access Control 241 * 242 * 4 Reserved 243 * 244 * 5 Fault Status 245 * 246 * 6 Fault Address 247 * 248 * 7 Cache/write-buffer Control 249 * 250 * 8 TLB Control 251 * 252 * 9 Cache Lockdown 253 * 254 * 10 TLB Lockdown 255 * 256 * 11 Reserved 257 * 258 * 12 Reserved 259 * 260 * 13 Process ID (for FCSE) 261 * 262 * 14 Reserved 263 * 264 * 15 Implementation Dependent 265 */ 266 267 /* Some of the definitions below need cleaning up for V3/V4 architectures */ 268 269 /* CPU control register (CP15 register 1) */ 270 #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 271 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 272 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 273 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 274 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 275 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 276 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 277 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 278 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 279 #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 280 #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 281 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 282 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 283 #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 284 #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 285 #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 286 #define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */ 287 #define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ 288 289 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 290 291 /* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 292 #define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 293 #define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 294 /* Note: XSCale core 3 uses those for LLR DCcahce attributes */ 295 #define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 296 #define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 297 #define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 298 #define XSCALE_AUXCTL_MD_MASK 0x00000030 299 300 /* Xscale Core 3 only */ 301 #define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */ 302 303 /* Marvell Extra Features Register (CP15 register 1, opcode2 0) */ 304 #define MV_DC_REPLACE_LOCK 0x80000000 /* Replace DCache Lock */ 305 #define MV_DC_STREAM_ENABLE 0x20000000 /* DCache Streaming Switch */ 306 #define MV_WA_ENABLE 0x10000000 /* Enable Write Allocate */ 307 #define MV_L2_PREFETCH_DISABLE 0x01000000 /* L2 Cache Prefetch Disable */ 308 #define MV_L2_INV_EVICT_ERR 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 309 #define MV_L2_ENABLE 0x00400000 /* L2 Cache enable */ 310 #define MV_IC_REPLACE_LOCK 0x00080000 /* Replace ICache Lock */ 311 #define MV_BGH_ENABLE 0x00040000 /* Branch Global History Register Enable */ 312 #define MV_BTB_DISABLE 0x00020000 /* Branch Target Buffer Disable */ 313 #define MV_L1_PARERR_ENABLE 0x00010000 /* L1 Parity Error Enable */ 314 315 /* Cache type register definitions */ 316 #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 317 #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 318 #define CPU_CT_S (1U << 24) /* split cache */ 319 #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 320 #define CPU_CT_FORMAT(x) ((x) >> 29) 321 322 #define CPU_CT_CTYPE_WT 0 /* write-through */ 323 #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 324 #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 325 #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 326 #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 327 328 #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 329 #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 330 #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 331 #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 332 333 #define CPU_CT_ARMV7 0x4 334 /* ARM v7 Cache type definitions */ 335 #define CPUV7_CT_CTYPE_WT (1 << 31) 336 #define CPUV7_CT_CTYPE_WB (1 << 30) 337 #define CPUV7_CT_CTYPE_RA (1 << 29) 338 #define CPUV7_CT_CTYPE_WA (1 << 28) 339 340 #define CPUV7_CT_xSIZE_LEN(x) ((x) & 0x7) /* line size */ 341 #define CPUV7_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x3ff) /* associativity */ 342 #define CPUV7_CT_xSIZE_SET(x) (((x) >> 13) & 0x7fff) /* num sets */ 343 344 #define CPU_CLIDR_CTYPE(reg,x) (((reg) >> ((x) * 3)) & 0x7) 345 #define CPU_CLIDR_LOUIS(reg) (((reg) >> 21) & 0x7) 346 #define CPU_CLIDR_LOC(reg) (((reg) >> 24) & 0x7) 347 #define CPU_CLIDR_LOUU(reg) (((reg) >> 27) & 0x7) 348 349 #define CACHE_ICACHE 1 350 #define CACHE_DCACHE 2 351 #define CACHE_SEP_CACHE 3 352 #define CACHE_UNI_CACHE 4 353 354 /* Fault status register definitions */ 355 356 #define FAULT_TYPE_MASK 0x0f 357 #define FAULT_USER 0x10 358 359 #define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 360 #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 361 #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 362 #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 363 #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 364 #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 365 #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 366 #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 367 #define FAULT_ALIGN_0 0x01 /* Alignment */ 368 #define FAULT_ALIGN_1 0x03 /* Alignment */ 369 #define FAULT_TRANS_S 0x05 /* Translation -- Section */ 370 #define FAULT_TRANS_P 0x07 /* Translation -- Page */ 371 #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 372 #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 373 #define FAULT_PERM_S 0x0d /* Permission -- Section */ 374 #define FAULT_PERM_P 0x0f /* Permission -- Page */ 375 376 #define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 377 378 /* 379 * Address of the vector page, low and high versions. 380 */ 381 #ifndef __ASSEMBLER__ 382 #define ARM_VECTORS_LOW 0x00000000U 383 #define ARM_VECTORS_HIGH 0xffff0000U 384 #else 385 #define ARM_VECTORS_LOW 0 386 #define ARM_VECTORS_HIGH 0xffff0000 387 #endif 388 389 /* 390 * ARM Instructions 391 * 392 * 3 3 2 2 2 393 * 1 0 9 8 7 0 394 * +-------+-------------------------------------------------------+ 395 * | cond | instruction dependant | 396 * |c c c c| | 397 * +-------+-------------------------------------------------------+ 398 */ 399 400 #define INSN_SIZE 4 /* Always 4 bytes */ 401 #define INSN_COND_MASK 0xf0000000 /* Condition mask */ 402 #define INSN_COND_AL 0xe0000000 /* Always condition */ 403 404 #define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 405 406 #endif /* !MACHINE_ARMREG_H */ 407