xref: /freebsd/sys/arm/include/armreg.h (revision 2f6a179eb910129fb812c1ad1bdc300da1203dc0)
1 /*	$NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $	*/
2 
3 /*-
4  * Copyright (c) 1998, 2001 Ben Harris
5  * Copyright (c) 1994-1996 Mark Brinicombe.
6  * Copyright (c) 1994 Brini.
7  * All rights reserved.
8  *
9  * This code is derived from software written for Brini by Mark Brinicombe
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  * 3. All advertising materials mentioning features or use of this software
20  *    must display the following acknowledgement:
21  *	This product includes software developed by Brini.
22  * 4. The name of the company nor the name of the author may be used to
23  *    endorse or promote products derived from this software without specific
24  *    prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
27  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
28  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29  * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36  * SUCH DAMAGE.
37  *
38  * $FreeBSD$
39  */
40 
41 #ifndef MACHINE_ARMREG_H
42 #define MACHINE_ARMREG_H
43 
44 #define INSN_SIZE	4
45 #define INSN_COND_MASK	0xf0000000	/* Condition mask */
46 #define PSR_MODE        0x0000001f      /* mode mask */
47 #define PSR_USR26_MODE  0x00000000
48 #define PSR_FIQ26_MODE  0x00000001
49 #define PSR_IRQ26_MODE  0x00000002
50 #define PSR_SVC26_MODE  0x00000003
51 #define PSR_USR32_MODE  0x00000010
52 #define PSR_FIQ32_MODE  0x00000011
53 #define PSR_IRQ32_MODE  0x00000012
54 #define PSR_SVC32_MODE  0x00000013
55 #define PSR_ABT32_MODE  0x00000017
56 #define PSR_UND32_MODE  0x0000001b
57 #define PSR_SYS32_MODE  0x0000001f
58 #define PSR_32_MODE     0x00000010
59 #define PSR_FLAGS	0xf0000000    /* flags */
60 
61 #define PSR_C_bit (1 << 29)       /* carry */
62 
63 /* The high-order byte is always the implementor */
64 #define CPU_ID_IMPLEMENTOR_MASK	0xff000000
65 #define CPU_ID_ARM_LTD		0x41000000 /* 'A' */
66 #define CPU_ID_DEC		0x44000000 /* 'D' */
67 #define CPU_ID_INTEL		0x69000000 /* 'i' */
68 #define	CPU_ID_TI		0x54000000 /* 'T' */
69 #define	CPU_ID_FARADAY		0x66000000 /* 'f' */
70 
71 /* How to decide what format the CPUID is in. */
72 #define CPU_ID_ISOLD(x)		(((x) & 0x0000f000) == 0x00000000)
73 #define CPU_ID_IS7(x)		(((x) & 0x0000f000) == 0x00007000)
74 #define CPU_ID_ISNEW(x)		(!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x))
75 
76 /* On ARM3 and ARM6, this byte holds the foundry ID. */
77 #define CPU_ID_FOUNDRY_MASK	0x00ff0000
78 #define CPU_ID_FOUNDRY_VLSI	0x00560000
79 
80 /* On ARM7 it holds the architecture and variant (sub-model) */
81 #define CPU_ID_7ARCH_MASK	0x00800000
82 #define CPU_ID_7ARCH_V3		0x00000000
83 #define CPU_ID_7ARCH_V4T	0x00800000
84 #define CPU_ID_7VARIANT_MASK	0x007f0000
85 
86 /* On more recent ARMs, it does the same, but in a different format */
87 #define CPU_ID_ARCH_MASK	0x000f0000
88 #define CPU_ID_ARCH_V3		0x00000000
89 #define CPU_ID_ARCH_V4		0x00010000
90 #define CPU_ID_ARCH_V4T		0x00020000
91 #define CPU_ID_ARCH_V5		0x00030000
92 #define CPU_ID_ARCH_V5T		0x00040000
93 #define CPU_ID_ARCH_V5TE	0x00050000
94 #define CPU_ID_ARCH_V5TEJ	0x00060000
95 #define CPU_ID_ARCH_V6		0x00070000
96 #define CPU_ID_VARIANT_MASK	0x00f00000
97 
98 /* Next three nybbles are part number */
99 #define CPU_ID_PARTNO_MASK	0x0000fff0
100 
101 /* Intel XScale has sub fields in part number */
102 #define CPU_ID_XSCALE_COREGEN_MASK	0x0000e000 /* core generation */
103 #define CPU_ID_XSCALE_COREREV_MASK	0x00001c00 /* core revision */
104 #define CPU_ID_XSCALE_PRODUCT_MASK	0x000003f0 /* product number */
105 
106 /* And finally, the revision number. */
107 #define CPU_ID_REVISION_MASK	0x0000000f
108 
109 /* Individual CPUs are probably best IDed by everything but the revision. */
110 #define CPU_ID_CPU_MASK		0xfffffff0
111 
112 /* Fake CPU IDs for ARMs without CP15 */
113 #define CPU_ID_ARM2		0x41560200
114 #define CPU_ID_ARM250		0x41560250
115 
116 /* Pre-ARM7 CPUs -- [15:12] == 0 */
117 #define CPU_ID_ARM3		0x41560300
118 #define CPU_ID_ARM600		0x41560600
119 #define CPU_ID_ARM610		0x41560610
120 #define CPU_ID_ARM620		0x41560620
121 
122 /* ARM7 CPUs -- [15:12] == 7 */
123 #define CPU_ID_ARM700		0x41007000 /* XXX This is a guess. */
124 #define CPU_ID_ARM710		0x41007100
125 #define CPU_ID_ARM7500		0x41027100
126 #define CPU_ID_ARM710A		0x41047100 /* inc ARM7100 */
127 #define CPU_ID_ARM7500FE	0x41077100
128 #define CPU_ID_ARM710T		0x41807100
129 #define CPU_ID_ARM720T		0x41807200
130 #define CPU_ID_ARM740T8K	0x41807400 /* XXX no MMU, 8KB cache */
131 #define CPU_ID_ARM740T4K	0x41817400 /* XXX no MMU, 4KB cache */
132 
133 /* Post-ARM7 CPUs */
134 #define CPU_ID_ARM810		0x41018100
135 #define CPU_ID_ARM920T		0x41129200
136 #define CPU_ID_ARM920T_ALT	0x41009200
137 #define CPU_ID_ARM922T		0x41029220
138 #define CPU_ID_ARM926EJS	0x41069260
139 #define CPU_ID_ARM940T		0x41029400 /* XXX no MMU */
140 #define CPU_ID_ARM946ES		0x41049460 /* XXX no MMU */
141 #define	CPU_ID_ARM966ES		0x41049660 /* XXX no MMU */
142 #define	CPU_ID_ARM966ESR1	0x41059660 /* XXX no MMU */
143 #define CPU_ID_ARM1020E		0x4115a200 /* (AKA arm10 rev 1) */
144 #define CPU_ID_ARM1022ES	0x4105a220
145 #define CPU_ID_ARM1026EJS	0x4106a260
146 #define CPU_ID_ARM1136JS	0x4107b360
147 #define CPU_ID_ARM1136JSR1	0x4117b360
148 #define CPU_ID_SA110		0x4401a100
149 #define CPU_ID_SA1100		0x4401a110
150 #define	CPU_ID_TI925T		0x54029250
151 #define	CPU_ID_FA526		0x66015260
152 #define CPU_ID_SA1110		0x6901b110
153 #define CPU_ID_IXP1200		0x6901c120
154 #define CPU_ID_80200		0x69052000
155 #define CPU_ID_PXA250    	0x69052100 /* sans core revision */
156 #define CPU_ID_PXA210    	0x69052120
157 #define CPU_ID_PXA250A		0x69052100 /* 1st version Core */
158 #define CPU_ID_PXA210A		0x69052120 /* 1st version Core */
159 #define CPU_ID_PXA250B		0x69052900 /* 3rd version Core */
160 #define CPU_ID_PXA210B		0x69052920 /* 3rd version Core */
161 #define CPU_ID_PXA250C		0x69052d00 /* 4th version Core */
162 #define CPU_ID_PXA210C		0x69052d20 /* 4th version Core */
163 #define	CPU_ID_PXA27X		0x69054110
164 #define	CPU_ID_80321_400	0x69052420
165 #define	CPU_ID_80321_600	0x69052430
166 #define	CPU_ID_80321_400_B0	0x69052c20
167 #define	CPU_ID_80321_600_B0	0x69052c30
168 #define	CPU_ID_80219_400	0x69052e20 /* A0 stepping/revision. */
169 #define	CPU_ID_80219_600	0x69052e30 /* A0 stepping/revision. */
170 #define	CPU_ID_81342		0x69056810
171 #define	CPU_ID_IXP425_533	0x690541c0
172 #define	CPU_ID_IXP425_400	0x690541d0
173 #define	CPU_ID_IXP425_266	0x690541f0
174 
175 /* ARM3-specific coprocessor 15 registers */
176 #define ARM3_CP15_FLUSH		1
177 #define ARM3_CP15_CONTROL	2
178 #define ARM3_CP15_CACHEABLE	3
179 #define ARM3_CP15_UPDATEABLE	4
180 #define ARM3_CP15_DISRUPTIVE	5
181 
182 /* ARM3 Control register bits */
183 #define ARM3_CTL_CACHE_ON	0x00000001
184 #define ARM3_CTL_SHARED		0x00000002
185 #define ARM3_CTL_MONITOR	0x00000004
186 
187 /*
188  * Post-ARM3 CP15 registers:
189  *
190  *	1	Control register
191  *
192  *	2	Translation Table Base
193  *
194  *	3	Domain Access Control
195  *
196  *	4	Reserved
197  *
198  *	5	Fault Status
199  *
200  *	6	Fault Address
201  *
202  *	7	Cache/write-buffer Control
203  *
204  *	8	TLB Control
205  *
206  *	9	Cache Lockdown
207  *
208  *	10	TLB Lockdown
209  *
210  *	11	Reserved
211  *
212  *	12	Reserved
213  *
214  *	13	Process ID (for FCSE)
215  *
216  *	14	Reserved
217  *
218  *	15	Implementation Dependent
219  */
220 
221 /* Some of the definitions below need cleaning up for V3/V4 architectures */
222 
223 /* CPU control register (CP15 register 1) */
224 #define CPU_CONTROL_MMU_ENABLE	0x00000001 /* M: MMU/Protection unit enable */
225 #define CPU_CONTROL_AFLT_ENABLE	0x00000002 /* A: Alignment fault enable */
226 #define CPU_CONTROL_DC_ENABLE	0x00000004 /* C: IDC/DC enable */
227 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */
228 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
229 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
230 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */
231 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */
232 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
233 #define CPU_CONTROL_ROM_ENABLE	0x00000200 /* R: ROM protection bit */
234 #define CPU_CONTROL_CPCLK	0x00000400 /* F: Implementation defined */
235 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
236 #define CPU_CONTROL_IC_ENABLE   0x00001000 /* I: IC enable */
237 #define CPU_CONTROL_VECRELOC	0x00002000 /* V: Vector relocation */
238 #define CPU_CONTROL_ROUNDROBIN	0x00004000 /* RR: Predictable replacement */
239 #define CPU_CONTROL_V4COMPAT	0x00008000 /* L4: ARMv4 compat LDR R15 etc */
240 #define CPU_CONTROL_L2_ENABLE	0x04000000 /* L2 Cache enabled */
241 
242 #define CPU_CONTROL_IDC_ENABLE	CPU_CONTROL_DC_ENABLE
243 
244 /* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */
245 #define	XSCALE_AUXCTL_K		0x00000001 /* dis. write buffer coalescing */
246 #define	XSCALE_AUXCTL_P		0x00000002 /* ECC protect page table access */
247 /* Note: XSCale core 3 uses those for LLR DCcahce attributes */
248 #define	XSCALE_AUXCTL_MD_WB_RA	0x00000000 /* mini-D$ wb, read-allocate */
249 #define	XSCALE_AUXCTL_MD_WB_RWA	0x00000010 /* mini-D$ wb, read/write-allocate */
250 #define	XSCALE_AUXCTL_MD_WT	0x00000020 /* mini-D$ wt, read-allocate */
251 #define	XSCALE_AUXCTL_MD_MASK	0x00000030
252 
253 /* Xscale Core 3 only */
254 #define XSCALE_AUXCTL_LLR	0x00000400 /* Enable L2 for LLR Cache */
255 
256 /* Cache type register definitions */
257 #define	CPU_CT_ISIZE(x)		((x) & 0xfff)		/* I$ info */
258 #define	CPU_CT_DSIZE(x)		(((x) >> 12) & 0xfff)	/* D$ info */
259 #define	CPU_CT_S		(1U << 24)		/* split cache */
260 #define	CPU_CT_CTYPE(x)		(((x) >> 25) & 0xf)	/* cache type */
261 
262 #define	CPU_CT_CTYPE_WT		0	/* write-through */
263 #define	CPU_CT_CTYPE_WB1	1	/* write-back, clean w/ read */
264 #define	CPU_CT_CTYPE_WB2	2	/* w/b, clean w/ cp15,7 */
265 #define	CPU_CT_CTYPE_WB6	6	/* w/b, cp15,7, lockdown fmt A */
266 #define	CPU_CT_CTYPE_WB7	7	/* w/b, cp15,7, lockdown fmt B */
267 
268 #define	CPU_CT_xSIZE_LEN(x)	((x) & 0x3)		/* line size */
269 #define	CPU_CT_xSIZE_M		(1U << 2)		/* multiplier */
270 #define	CPU_CT_xSIZE_ASSOC(x)	(((x) >> 3) & 0x7)	/* associativity */
271 #define	CPU_CT_xSIZE_SIZE(x)	(((x) >> 6) & 0x7)	/* size */
272 
273 /* Fault status register definitions */
274 
275 #define FAULT_TYPE_MASK 0x0f
276 #define FAULT_USER      0x10
277 
278 #define FAULT_WRTBUF_0  0x00 /* Vector Exception */
279 #define FAULT_WRTBUF_1  0x02 /* Terminal Exception */
280 #define FAULT_BUSERR_0  0x04 /* External Abort on Linefetch -- Section */
281 #define FAULT_BUSERR_1  0x06 /* External Abort on Linefetch -- Page */
282 #define FAULT_BUSERR_2  0x08 /* External Abort on Non-linefetch -- Section */
283 #define FAULT_BUSERR_3  0x0a /* External Abort on Non-linefetch -- Page */
284 #define FAULT_BUSTRNL1  0x0c /* External abort on Translation -- Level 1 */
285 #define FAULT_BUSTRNL2  0x0e /* External abort on Translation -- Level 2 */
286 #define FAULT_ALIGN_0   0x01 /* Alignment */
287 #define FAULT_ALIGN_1   0x03 /* Alignment */
288 #define FAULT_TRANS_S   0x05 /* Translation -- Section */
289 #define FAULT_TRANS_P   0x07 /* Translation -- Page */
290 #define FAULT_DOMAIN_S  0x09 /* Domain -- Section */
291 #define FAULT_DOMAIN_P  0x0b /* Domain -- Page */
292 #define FAULT_PERM_S    0x0d /* Permission -- Section */
293 #define FAULT_PERM_P    0x0f /* Permission -- Page */
294 
295 #define	FAULT_IMPRECISE	0x400	/* Imprecise exception (XSCALE) */
296 
297 /*
298  * Address of the vector page, low and high versions.
299  */
300 #define	ARM_VECTORS_LOW		0x00000000U
301 #define	ARM_VECTORS_HIGH	0xffff0000U
302 
303 /*
304  * ARM Instructions
305  *
306  *       3 3 2 2 2
307  *       1 0 9 8 7                                                     0
308  *      +-------+-------------------------------------------------------+
309  *      | cond  |              instruction dependant                    |
310  *      |c c c c|                                                       |
311  *      +-------+-------------------------------------------------------+
312  */
313 
314 #define INSN_SIZE		4		/* Always 4 bytes */
315 #define INSN_COND_MASK		0xf0000000	/* Condition mask */
316 #define INSN_COND_AL		0xe0000000	/* Always condition */
317 
318 #define THUMB_INSN_SIZE		2		/* Some are 4 bytes.  */
319 
320 #endif /* !MACHINE_ARMREG_H */
321