1 /*- 2 * Copyright (c) 2013 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Vybrid Family Universal Asynchronous Receiver/Transmitter 29 * Chapter 49, Vybrid Reference Manual, Rev. 5, 07/2013 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include "opt_ddb.h" 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/bus.h> 40 #include <sys/conf.h> 41 #include <sys/kdb.h> 42 #include <machine/bus.h> 43 44 #include <dev/uart/uart.h> 45 #include <dev/uart/uart_cpu.h> 46 #include <dev/uart/uart_cpu_fdt.h> 47 #include <dev/uart/uart_bus.h> 48 49 #include "uart_if.h" 50 51 #define UART_BDH 0x00 /* Baud Rate Registers: High */ 52 #define UART_BDL 0x01 /* Baud Rate Registers: Low */ 53 #define UART_C1 0x02 /* Control Register 1 */ 54 #define UART_C2 0x03 /* Control Register 2 */ 55 #define UART_S1 0x04 /* Status Register 1 */ 56 #define UART_S2 0x05 /* Status Register 2 */ 57 #define UART_C3 0x06 /* Control Register 3 */ 58 #define UART_D 0x07 /* Data Register */ 59 #define UART_MA1 0x08 /* Match Address Registers 1 */ 60 #define UART_MA2 0x09 /* Match Address Registers 2 */ 61 #define UART_C4 0x0A /* Control Register 4 */ 62 #define UART_C5 0x0B /* Control Register 5 */ 63 #define UART_ED 0x0C /* Extended Data Register */ 64 #define UART_MODEM 0x0D /* Modem Register */ 65 #define UART_IR 0x0E /* Infrared Register */ 66 #define UART_PFIFO 0x10 /* FIFO Parameters */ 67 #define UART_CFIFO 0x11 /* FIFO Control Register */ 68 #define UART_SFIFO 0x12 /* FIFO Status Register */ 69 #define UART_TWFIFO 0x13 /* FIFO Transmit Watermark */ 70 #define UART_TCFIFO 0x14 /* FIFO Transmit Count */ 71 #define UART_RWFIFO 0x15 /* FIFO Receive Watermark */ 72 #define UART_RCFIFO 0x16 /* FIFO Receive Count */ 73 #define UART_C7816 0x18 /* 7816 Control Register */ 74 #define UART_IE7816 0x19 /* 7816 Interrupt Enable Register */ 75 #define UART_IS7816 0x1A /* 7816 Interrupt Status Register */ 76 #define UART_WP7816T0 0x1B /* 7816 Wait Parameter Register */ 77 #define UART_WP7816T1 0x1B /* 7816 Wait Parameter Register */ 78 #define UART_WN7816 0x1C /* 7816 Wait N Register */ 79 #define UART_WF7816 0x1D /* 7816 Wait FD Register */ 80 #define UART_ET7816 0x1E /* 7816 Error Threshold Register */ 81 #define UART_TL7816 0x1F /* 7816 Transmit Length Register */ 82 #define UART_C6 0x21 /* CEA709.1-B Control Register 6 */ 83 #define UART_PCTH 0x22 /* CEA709.1-B Packet Cycle Time Counter High */ 84 #define UART_PCTL 0x23 /* CEA709.1-B Packet Cycle Time Counter Low */ 85 #define UART_B1T 0x24 /* CEA709.1-B Beta1 Timer */ 86 #define UART_SDTH 0x25 /* CEA709.1-B Secondary Delay Timer High */ 87 #define UART_SDTL 0x26 /* CEA709.1-B Secondary Delay Timer Low */ 88 #define UART_PRE 0x27 /* CEA709.1-B Preamble */ 89 #define UART_TPL 0x28 /* CEA709.1-B Transmit Packet Length */ 90 #define UART_IE 0x29 /* CEA709.1-B Interrupt Enable Register */ 91 #define UART_WB 0x2A /* CEA709.1-B WBASE */ 92 #define UART_S3 0x2B /* CEA709.1-B Status Register */ 93 #define UART_S4 0x2C /* CEA709.1-B Status Register */ 94 #define UART_RPL 0x2D /* CEA709.1-B Received Packet Length */ 95 #define UART_RPREL 0x2E /* CEA709.1-B Received Preamble Length */ 96 #define UART_CPW 0x2F /* CEA709.1-B Collision Pulse Width */ 97 #define UART_RIDT 0x30 /* CEA709.1-B Receive Indeterminate Time */ 98 #define UART_TIDT 0x31 /* CEA709.1-B Transmit Indeterminate Time */ 99 100 #define UART_C2_TE (1 << 3) /* Transmitter Enable */ 101 #define UART_C2_TIE (1 << 7) /* Transmitter Interrupt Enable */ 102 #define UART_C2_RE (1 << 2) /* Receiver Enable */ 103 #define UART_C2_RIE (1 << 5) /* Receiver Interrupt Enable */ 104 #define UART_S1_TDRE (1 << 7) /* Transmit Data Register Empty Flag */ 105 #define UART_S1_RDRF (1 << 5) /* Receive Data Register Full Flag */ 106 #define UART_S2_LBKDIF (1 << 7) /* LIN Break Detect Interrupt Flag */ 107 108 #define UART_C4_BRFA 0x1f /* Baud Rate Fine Adjust */ 109 #define UART_BDH_SBR 0x1f /* UART Baud Rate Bits */ 110 111 /* 112 * Low-level UART interface. 113 */ 114 static int vf_uart_probe(struct uart_bas *bas); 115 static void vf_uart_init(struct uart_bas *bas, int, int, int, int); 116 static void vf_uart_term(struct uart_bas *bas); 117 static void vf_uart_putc(struct uart_bas *bas, int); 118 static int vf_uart_rxready(struct uart_bas *bas); 119 static int vf_uart_getc(struct uart_bas *bas, struct mtx *); 120 121 void uart_reinit(struct uart_softc *,int,int); 122 123 static struct uart_ops uart_vybrid_ops = { 124 .probe = vf_uart_probe, 125 .init = vf_uart_init, 126 .term = vf_uart_term, 127 .putc = vf_uart_putc, 128 .rxready = vf_uart_rxready, 129 .getc = vf_uart_getc, 130 }; 131 132 static int 133 vf_uart_probe(struct uart_bas *bas) 134 { 135 136 return (0); 137 } 138 139 static void 140 vf_uart_init(struct uart_bas *bas, int baudrate, int databits, 141 int stopbits, int parity) 142 { 143 144 } 145 146 static void 147 vf_uart_term(struct uart_bas *bas) 148 { 149 150 } 151 152 static void 153 vf_uart_putc(struct uart_bas *bas, int c) 154 { 155 156 while (!(uart_getreg(bas, UART_S1) & UART_S1_TDRE)) 157 ; 158 159 uart_setreg(bas, UART_D, c); 160 } 161 162 static int 163 vf_uart_rxready(struct uart_bas *bas) 164 { 165 int usr1; 166 167 usr1 = uart_getreg(bas, UART_S1); 168 if (usr1 & UART_S1_RDRF) { 169 return (1); 170 } 171 172 return (0); 173 } 174 175 static int 176 vf_uart_getc(struct uart_bas *bas, struct mtx *hwmtx) 177 { 178 int c; 179 180 uart_lock(hwmtx); 181 182 while (!(uart_getreg(bas, UART_S1) & UART_S1_RDRF)) 183 ; 184 185 c = uart_getreg(bas, UART_D); 186 uart_unlock(hwmtx); 187 188 return (c & 0xff); 189 } 190 191 /* 192 * High-level UART interface. 193 */ 194 struct vf_uart_softc { 195 struct uart_softc base; 196 }; 197 198 void 199 uart_reinit(struct uart_softc *sc, int clkspeed, int baud) 200 { 201 struct uart_bas *bas; 202 int sbr; 203 int brfa; 204 int reg; 205 206 bas = &sc->sc_bas; 207 if (!bas) { 208 printf("Error: cant reconfigure bas\n"); 209 return; 210 } 211 212 uart_setreg(bas, UART_MODEM, 0x00); 213 214 /* 215 * Disable transmitter and receiver 216 * for a while. 217 */ 218 reg = uart_getreg(bas, UART_C2); 219 reg &= ~(UART_C2_RE | UART_C2_TE); 220 uart_setreg(bas, UART_C2, 0x00); 221 222 uart_setreg(bas, UART_C1, 0x00); 223 224 sbr = (uint16_t) (clkspeed / (baud * 16)); 225 brfa = (clkspeed / baud) - (sbr * 16); 226 227 reg = uart_getreg(bas, UART_BDH); 228 reg &= ~UART_BDH_SBR; 229 reg |= ((sbr & 0x1f00) >> 8); 230 uart_setreg(bas, UART_BDH, reg); 231 232 reg = sbr & 0x00ff; 233 uart_setreg(bas, UART_BDL, reg); 234 235 reg = uart_getreg(bas, UART_C4); 236 reg &= ~UART_C4_BRFA; 237 reg |= (brfa & UART_C4_BRFA); 238 uart_setreg(bas, UART_C4, reg); 239 240 reg = uart_getreg(bas, UART_C2); 241 reg |= (UART_C2_RE | UART_C2_TE); 242 uart_setreg(bas, UART_C2, reg); 243 244 } 245 246 static int vf_uart_bus_attach(struct uart_softc *); 247 static int vf_uart_bus_detach(struct uart_softc *); 248 static int vf_uart_bus_flush(struct uart_softc *, int); 249 static int vf_uart_bus_getsig(struct uart_softc *); 250 static int vf_uart_bus_ioctl(struct uart_softc *, int, intptr_t); 251 static int vf_uart_bus_ipend(struct uart_softc *); 252 static int vf_uart_bus_param(struct uart_softc *, int, int, int, int); 253 static int vf_uart_bus_probe(struct uart_softc *); 254 static int vf_uart_bus_receive(struct uart_softc *); 255 static int vf_uart_bus_setsig(struct uart_softc *, int); 256 static int vf_uart_bus_transmit(struct uart_softc *); 257 258 static kobj_method_t vf_uart_methods[] = { 259 KOBJMETHOD(uart_attach, vf_uart_bus_attach), 260 KOBJMETHOD(uart_detach, vf_uart_bus_detach), 261 KOBJMETHOD(uart_flush, vf_uart_bus_flush), 262 KOBJMETHOD(uart_getsig, vf_uart_bus_getsig), 263 KOBJMETHOD(uart_ioctl, vf_uart_bus_ioctl), 264 KOBJMETHOD(uart_ipend, vf_uart_bus_ipend), 265 KOBJMETHOD(uart_param, vf_uart_bus_param), 266 KOBJMETHOD(uart_probe, vf_uart_bus_probe), 267 KOBJMETHOD(uart_receive, vf_uart_bus_receive), 268 KOBJMETHOD(uart_setsig, vf_uart_bus_setsig), 269 KOBJMETHOD(uart_transmit, vf_uart_bus_transmit), 270 { 0, 0 } 271 }; 272 273 static struct uart_class uart_vybrid_class = { 274 "vybrid", 275 vf_uart_methods, 276 sizeof(struct vf_uart_softc), 277 .uc_ops = &uart_vybrid_ops, 278 .uc_range = 0x100, 279 .uc_rclk = 24000000, /* TODO: get value from CCM */ 280 .uc_rshift = 0 281 }; 282 283 static struct ofw_compat_data compat_data[] = { 284 {"fsl,mvf600-uart", (uintptr_t)&uart_vybrid_class}, 285 {NULL, (uintptr_t)NULL}, 286 }; 287 UART_FDT_CLASS_AND_DEVICE(compat_data); 288 289 static int 290 vf_uart_bus_attach(struct uart_softc *sc) 291 { 292 struct uart_bas *bas; 293 int reg; 294 295 bas = &sc->sc_bas; 296 297 sc->sc_hwiflow = 0; 298 sc->sc_hwoflow = 0; 299 300 uart_reinit(sc, 66000000, 115200); 301 302 reg = uart_getreg(bas, UART_C2); 303 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) { 304 reg &= ~UART_C2_RIE; 305 } else { 306 reg |= UART_C2_RIE; 307 } 308 uart_setreg(bas, UART_C2, reg); 309 310 return (0); 311 } 312 313 static int 314 vf_uart_bus_detach(struct uart_softc *sc) 315 { 316 317 /* TODO */ 318 return (0); 319 } 320 321 static int 322 vf_uart_bus_flush(struct uart_softc *sc, int what) 323 { 324 325 /* TODO */ 326 return (0); 327 } 328 329 static int 330 vf_uart_bus_getsig(struct uart_softc *sc) 331 { 332 333 /* TODO */ 334 return (0); 335 } 336 337 static int 338 vf_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 339 { 340 struct uart_bas *bas; 341 int error; 342 343 bas = &sc->sc_bas; 344 error = 0; 345 uart_lock(sc->sc_hwmtx); 346 switch (request) { 347 case UART_IOCTL_BREAK: 348 /* TODO */ 349 break; 350 case UART_IOCTL_BAUD: 351 /* TODO */ 352 *(int*)data = 115200; 353 break; 354 default: 355 error = EINVAL; 356 break; 357 } 358 uart_unlock(sc->sc_hwmtx); 359 360 return (error); 361 } 362 363 static int 364 vf_uart_bus_ipend(struct uart_softc *sc) 365 { 366 struct uart_bas *bas; 367 int ipend; 368 uint32_t usr1, usr2; 369 int reg; 370 int sfifo; 371 372 bas = &sc->sc_bas; 373 ipend = 0; 374 375 uart_lock(sc->sc_hwmtx); 376 377 usr1 = uart_getreg(bas, UART_S1); 378 usr2 = uart_getreg(bas, UART_S2); 379 sfifo = uart_getreg(bas, UART_SFIFO); 380 381 /* ack usr2 */ 382 uart_setreg(bas, UART_S2, usr2); 383 384 if (usr1 & UART_S1_TDRE) { 385 reg = uart_getreg(bas, UART_C2); 386 reg &= ~(UART_C2_TIE); 387 uart_setreg(bas, UART_C2, reg); 388 389 if (sc->sc_txbusy != 0) { 390 ipend |= SER_INT_TXIDLE; 391 } 392 } 393 394 if (usr1 & UART_S1_RDRF) { 395 reg = uart_getreg(bas, UART_C2); 396 reg &= ~(UART_C2_RIE); 397 uart_setreg(bas, UART_C2, reg); 398 399 ipend |= SER_INT_RXREADY; 400 } 401 402 if (usr2 & UART_S2_LBKDIF) { 403 ipend |= SER_INT_BREAK; 404 } 405 406 uart_unlock(sc->sc_hwmtx); 407 408 return (ipend); 409 } 410 411 static int 412 vf_uart_bus_param(struct uart_softc *sc, int baudrate, int databits, 413 int stopbits, int parity) 414 { 415 416 uart_lock(sc->sc_hwmtx); 417 vf_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity); 418 uart_unlock(sc->sc_hwmtx); 419 420 return (0); 421 } 422 423 static int 424 vf_uart_bus_probe(struct uart_softc *sc) 425 { 426 int error; 427 428 error = vf_uart_probe(&sc->sc_bas); 429 if (error) 430 return (error); 431 432 sc->sc_rxfifosz = 1; 433 sc->sc_txfifosz = 1; 434 435 device_set_desc(sc->sc_dev, "Vybrid Family UART"); 436 return (0); 437 } 438 439 static int 440 vf_uart_bus_receive(struct uart_softc *sc) 441 { 442 struct uart_bas *bas; 443 int reg; 444 int c; 445 446 bas = &sc->sc_bas; 447 uart_lock(sc->sc_hwmtx); 448 449 /* Read FIFO */ 450 while (uart_getreg(bas, UART_S1) & UART_S1_RDRF) { 451 if (uart_rx_full(sc)) { 452 /* No space left in input buffer */ 453 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 454 break; 455 } 456 457 c = uart_getreg(bas, UART_D); 458 uart_rx_put(sc, c); 459 } 460 461 /* Reenable Data Ready interrupt */ 462 reg = uart_getreg(bas, UART_C2); 463 reg |= (UART_C2_RIE); 464 uart_setreg(bas, UART_C2, reg); 465 466 uart_unlock(sc->sc_hwmtx); 467 return (0); 468 } 469 470 static int 471 vf_uart_bus_setsig(struct uart_softc *sc, int sig) 472 { 473 struct uart_bas *bas; 474 int reg; 475 476 /* TODO: implement (?) */ 477 478 /* XXX workaround to have working console on mount prompt */ 479 /* Enable RX interrupt */ 480 bas = &sc->sc_bas; 481 if (sc->sc_sysdev != NULL && sc->sc_sysdev->type == UART_DEV_CONSOLE) { 482 reg = uart_getreg(bas, UART_C2); 483 reg |= (UART_C2_RIE); 484 uart_setreg(bas, UART_C2, reg); 485 } 486 487 return (0); 488 } 489 490 static int 491 vf_uart_bus_transmit(struct uart_softc *sc) 492 { 493 struct uart_bas *bas = &sc->sc_bas; 494 int i; 495 int reg; 496 497 bas = &sc->sc_bas; 498 uart_lock(sc->sc_hwmtx); 499 500 /* Fill TX FIFO */ 501 for (i = 0; i < sc->sc_txdatasz; i++) { 502 uart_setreg(bas, UART_D, sc->sc_txbuf[i] & 0xff); 503 uart_barrier(&sc->sc_bas); 504 } 505 506 sc->sc_txbusy = 1; 507 508 /* Call me when ready */ 509 reg = uart_getreg(bas, UART_C2); 510 reg |= (UART_C2_TIE); 511 uart_setreg(bas, UART_C2, reg); 512 513 uart_unlock(sc->sc_hwmtx); 514 515 return (0); 516 } 517