1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Vybrid Family Serial Peripheral Interface (SPI) 29 * Chapter 47, Vybrid Reference Manual, Rev. 5, 07/2013 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/malloc.h> 41 #include <sys/rman.h> 42 #include <sys/timeet.h> 43 #include <sys/timetc.h> 44 #include <sys/watchdog.h> 45 46 #include <dev/spibus/spi.h> 47 #include <dev/spibus/spibusvar.h> 48 49 #include "spibus_if.h" 50 51 #include <dev/fdt/fdt_common.h> 52 #include <dev/ofw/openfirm.h> 53 #include <dev/ofw/ofw_bus.h> 54 #include <dev/ofw/ofw_bus_subr.h> 55 56 #include <machine/bus.h> 57 #include <machine/fdt.h> 58 #include <machine/cpu.h> 59 #include <machine/intr.h> 60 61 #include <arm/freescale/vybrid/vf_common.h> 62 63 #define SPI_FIFO_SIZE 4 64 65 #define SPI_MCR 0x00 /* Module Configuration */ 66 #define MCR_MSTR (1 << 31) /* Master/Slave Mode Select */ 67 #define MCR_CONT_SCKE (1 << 30) /* Continuous SCK Enable */ 68 #define MCR_FRZ (1 << 27) /* Freeze */ 69 #define MCR_PCSIS_S 16 /* Peripheral Chip Select */ 70 #define MCR_PCSIS_M 0x3f 71 #define MCR_MDIS (1 << 14) /* Module Disable */ 72 #define MCR_CLR_TXF (1 << 11) /* Clear TX FIFO */ 73 #define MCR_CLR_RXF (1 << 10) /* Clear RX FIFO */ 74 #define MCR_HALT (1 << 0) /* Starts and stops SPI transfers */ 75 #define SPI_TCR 0x08 /* Transfer Count */ 76 #define SPI_CTAR0 0x0C /* Clock and Transfer Attributes */ 77 #define SPI_CTAR0_SLAVE 0x0C /* Clock and Transfer Attributes */ 78 #define SPI_CTAR1 0x10 /* Clock and Transfer Attributes */ 79 #define SPI_CTAR2 0x14 /* Clock and Transfer Attributes */ 80 #define SPI_CTAR3 0x18 /* Clock and Transfer Attributes */ 81 #define CTAR_FMSZ_M 0xf 82 #define CTAR_FMSZ_S 27 /* Frame Size */ 83 #define CTAR_FMSZ_8 0x7 /* 8 bits */ 84 #define CTAR_CPOL (1 << 26) /* Clock Polarity */ 85 #define CTAR_CPHA (1 << 25) /* Clock Phase */ 86 #define CTAR_LSBFE (1 << 24) /* Less significant bit first */ 87 #define CTAR_PCSSCK_M 0x3 88 #define CTAR_PCSSCK_S 22 /* PCS to SCK Delay Prescaler */ 89 #define CTAR_PBR_M 0x3 90 #define CTAR_PBR_S 16 /* Baud Rate Prescaler */ 91 #define CTAR_PBR_7 0x3 /* Divide by 7 */ 92 #define CTAR_CSSCK_M 0xf 93 #define CTAR_CSSCK_S 12 /* PCS to SCK Delay Scaler */ 94 #define CTAR_BR_M 0xf 95 #define CTAR_BR_S 0 /* Baud Rate Scaler */ 96 #define SPI_SR 0x2C /* Status Register */ 97 #define SR_TCF (1 << 31) /* Transfer Complete Flag */ 98 #define SR_EOQF (1 << 28) /* End of Queue Flag */ 99 #define SR_TFFF (1 << 25) /* Transmit FIFO Fill Flag */ 100 #define SR_RFDF (1 << 17) /* Receive FIFO Drain Flag */ 101 #define SPI_RSER 0x30 /* DMA/Interrupt Select */ 102 #define RSER_EOQF_RE (1 << 28) /* Finished Request Enable */ 103 #define SPI_PUSHR 0x34 /* PUSH TX FIFO In Master Mode */ 104 #define PUSHR_CONT (1 << 31) /* Continuous Peripheral CS */ 105 #define PUSHR_EOQ (1 << 27) /* End Of Queue */ 106 #define PUSHR_CTCNT (1 << 26) /* Clear Transfer Counter */ 107 #define PUSHR_PCS_M 0x3f 108 #define PUSHR_PCS_S 16 /* Select PCS signals */ 109 110 #define SPI_PUSHR_SLAVE 0x34 /* PUSH TX FIFO Register In Slave Mode */ 111 #define SPI_POPR 0x38 /* POP RX FIFO Register */ 112 #define SPI_TXFR0 0x3C /* Transmit FIFO Registers */ 113 #define SPI_TXFR1 0x40 114 #define SPI_TXFR2 0x44 115 #define SPI_TXFR3 0x48 116 #define SPI_RXFR0 0x7C /* Receive FIFO Registers */ 117 #define SPI_RXFR1 0x80 118 #define SPI_RXFR2 0x84 119 #define SPI_RXFR3 0x88 120 121 struct spi_softc { 122 struct resource *res[2]; 123 bus_space_tag_t bst; 124 bus_space_handle_t bsh; 125 void *ih; 126 }; 127 128 static struct resource_spec spi_spec[] = { 129 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 130 { SYS_RES_IRQ, 0, RF_ACTIVE }, 131 { -1, 0 } 132 }; 133 134 static int 135 spi_probe(device_t dev) 136 { 137 138 if (!ofw_bus_status_okay(dev)) 139 return (ENXIO); 140 141 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-spi")) 142 return (ENXIO); 143 144 device_set_desc(dev, "Vybrid Family Serial Peripheral Interface"); 145 return (BUS_PROBE_DEFAULT); 146 } 147 148 static int 149 spi_attach(device_t dev) 150 { 151 struct spi_softc *sc; 152 uint32_t reg; 153 154 sc = device_get_softc(dev); 155 156 if (bus_alloc_resources(dev, spi_spec, sc->res)) { 157 device_printf(dev, "could not allocate resources\n"); 158 return (ENXIO); 159 } 160 161 /* Memory interface */ 162 sc->bst = rman_get_bustag(sc->res[0]); 163 sc->bsh = rman_get_bushandle(sc->res[0]); 164 165 reg = READ4(sc, SPI_MCR); 166 reg |= MCR_MSTR; 167 reg &= ~(MCR_CONT_SCKE | MCR_MDIS | MCR_FRZ); 168 reg &= ~(MCR_PCSIS_M << MCR_PCSIS_S); 169 reg |= (MCR_PCSIS_M << MCR_PCSIS_S); /* PCS Active low */ 170 reg |= (MCR_CLR_TXF | MCR_CLR_RXF); 171 WRITE4(sc, SPI_MCR, reg); 172 173 reg = READ4(sc, SPI_RSER); 174 reg |= RSER_EOQF_RE; 175 WRITE4(sc, SPI_RSER, reg); 176 177 reg = READ4(sc, SPI_MCR); 178 reg &= ~MCR_HALT; 179 WRITE4(sc, SPI_MCR, reg); 180 181 reg = READ4(sc, SPI_CTAR0); 182 reg &= ~(CTAR_FMSZ_M << CTAR_FMSZ_S); 183 reg |= (CTAR_FMSZ_8 << CTAR_FMSZ_S); 184 /* 185 * TODO: calculate BR 186 * SCK baud rate = ( fsys / PBR ) * (1 + DBR) / BR 187 * 188 * reg &= ~(CTAR_BR_M << CTAR_BR_S); 189 */ 190 reg &= ~CTAR_CPOL; /* Polarity */ 191 reg |= CTAR_CPHA; 192 /* 193 * Set LSB (Less significant bit first) 194 * must be used for some applications, e.g. some LCDs 195 */ 196 reg |= CTAR_LSBFE; 197 WRITE4(sc, SPI_CTAR0, reg); 198 199 reg = READ4(sc, SPI_CTAR0); 200 reg &= ~(CTAR_PBR_M << CTAR_PBR_S); 201 reg |= (CTAR_PBR_7 << CTAR_PBR_S); 202 WRITE4(sc, SPI_CTAR0, reg); 203 204 device_add_child(dev, "spibus", 0); 205 return (bus_generic_attach(dev)); 206 } 207 208 static int 209 spi_txrx(struct spi_softc *sc, uint8_t *out_buf, 210 uint8_t *in_buf, int bufsz, int cs) 211 { 212 uint32_t reg, wreg; 213 uint32_t txcnt; 214 uint32_t i; 215 216 txcnt = 0; 217 218 for (i = 0; i < bufsz; i++) { 219 txcnt++; 220 wreg = out_buf[i]; 221 wreg |= PUSHR_CONT; 222 wreg |= (cs << PUSHR_PCS_S); 223 if (i == 0) 224 wreg |= PUSHR_CTCNT; 225 if (i == (bufsz - 1) || txcnt == SPI_FIFO_SIZE) 226 wreg |= PUSHR_EOQ; 227 WRITE4(sc, SPI_PUSHR, wreg); 228 229 if (i == (bufsz - 1) || txcnt == SPI_FIFO_SIZE) { 230 txcnt = 0; 231 232 /* Wait last entry in a queue to be transmitted */ 233 while((READ4(sc, SPI_SR) & SR_EOQF) == 0) 234 continue; 235 236 reg = READ4(sc, SPI_SR); 237 reg |= (SR_TCF | SR_EOQF); 238 WRITE4(sc, SPI_SR, reg); 239 } 240 241 /* Wait until RX FIFO is empty */ 242 while((READ4(sc, SPI_SR) & SR_RFDF) == 0) 243 continue; 244 245 in_buf[i] = READ1(sc, SPI_POPR); 246 } 247 248 return (0); 249 } 250 251 static int 252 spi_transfer(device_t dev, device_t child, struct spi_command *cmd) 253 { 254 struct spi_softc *sc; 255 uint32_t cs; 256 257 sc = device_get_softc(dev); 258 259 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, 260 ("%s: TX/RX command sizes should be equal", __func__)); 261 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, 262 ("%s: TX/RX data sizes should be equal", __func__)); 263 264 /* get the proper chip select */ 265 spibus_get_cs(child, &cs); 266 267 /* Command */ 268 spi_txrx(sc, cmd->tx_cmd, cmd->rx_cmd, cmd->tx_cmd_sz, cs); 269 270 /* Data */ 271 spi_txrx(sc, cmd->tx_data, cmd->rx_data, cmd->tx_data_sz, cs); 272 273 return (0); 274 } 275 276 static device_method_t spi_methods[] = { 277 /* Device interface */ 278 DEVMETHOD(device_probe, spi_probe), 279 DEVMETHOD(device_attach, spi_attach), 280 /* SPI interface */ 281 DEVMETHOD(spibus_transfer, spi_transfer), 282 { 0, 0 } 283 }; 284 285 static driver_t spi_driver = { 286 "spi", 287 spi_methods, 288 sizeof(struct spi_softc), 289 }; 290 291 static devclass_t spi_devclass; 292 293 DRIVER_MODULE(spi, simplebus, spi_driver, spi_devclass, 0, 0); 294