1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Vybrid Family Serial Peripheral Interface (SPI) 29 * Chapter 47, Vybrid Reference Manual, Rev. 5, 07/2013 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/malloc.h> 41 #include <sys/rman.h> 42 #include <sys/timeet.h> 43 #include <sys/timetc.h> 44 #include <sys/watchdog.h> 45 46 #include <dev/spibus/spi.h> 47 #include <dev/spibus/spibusvar.h> 48 49 #include "spibus_if.h" 50 51 #include <dev/fdt/fdt_common.h> 52 #include <dev/ofw/openfirm.h> 53 #include <dev/ofw/ofw_bus.h> 54 #include <dev/ofw/ofw_bus_subr.h> 55 56 #include <machine/bus.h> 57 #include <machine/cpu.h> 58 #include <machine/intr.h> 59 60 #include <arm/freescale/vybrid/vf_common.h> 61 62 #define SPI_FIFO_SIZE 4 63 64 #define SPI_MCR 0x00 /* Module Configuration */ 65 #define MCR_MSTR (1 << 31) /* Master/Slave Mode Select */ 66 #define MCR_CONT_SCKE (1 << 30) /* Continuous SCK Enable */ 67 #define MCR_FRZ (1 << 27) /* Freeze */ 68 #define MCR_PCSIS_S 16 /* Peripheral Chip Select */ 69 #define MCR_PCSIS_M 0x3f 70 #define MCR_MDIS (1 << 14) /* Module Disable */ 71 #define MCR_CLR_TXF (1 << 11) /* Clear TX FIFO */ 72 #define MCR_CLR_RXF (1 << 10) /* Clear RX FIFO */ 73 #define MCR_HALT (1 << 0) /* Starts and stops SPI transfers */ 74 #define SPI_TCR 0x08 /* Transfer Count */ 75 #define SPI_CTAR0 0x0C /* Clock and Transfer Attributes */ 76 #define SPI_CTAR0_SLAVE 0x0C /* Clock and Transfer Attributes */ 77 #define SPI_CTAR1 0x10 /* Clock and Transfer Attributes */ 78 #define SPI_CTAR2 0x14 /* Clock and Transfer Attributes */ 79 #define SPI_CTAR3 0x18 /* Clock and Transfer Attributes */ 80 #define CTAR_FMSZ_M 0xf 81 #define CTAR_FMSZ_S 27 /* Frame Size */ 82 #define CTAR_FMSZ_8 0x7 /* 8 bits */ 83 #define CTAR_CPOL (1 << 26) /* Clock Polarity */ 84 #define CTAR_CPHA (1 << 25) /* Clock Phase */ 85 #define CTAR_LSBFE (1 << 24) /* Less significant bit first */ 86 #define CTAR_PCSSCK_M 0x3 87 #define CTAR_PCSSCK_S 22 /* PCS to SCK Delay Prescaler */ 88 #define CTAR_PBR_M 0x3 89 #define CTAR_PBR_S 16 /* Baud Rate Prescaler */ 90 #define CTAR_PBR_7 0x3 /* Divide by 7 */ 91 #define CTAR_CSSCK_M 0xf 92 #define CTAR_CSSCK_S 12 /* PCS to SCK Delay Scaler */ 93 #define CTAR_BR_M 0xf 94 #define CTAR_BR_S 0 /* Baud Rate Scaler */ 95 #define SPI_SR 0x2C /* Status Register */ 96 #define SR_TCF (1 << 31) /* Transfer Complete Flag */ 97 #define SR_EOQF (1 << 28) /* End of Queue Flag */ 98 #define SR_TFFF (1 << 25) /* Transmit FIFO Fill Flag */ 99 #define SR_RFDF (1 << 17) /* Receive FIFO Drain Flag */ 100 #define SPI_RSER 0x30 /* DMA/Interrupt Select */ 101 #define RSER_EOQF_RE (1 << 28) /* Finished Request Enable */ 102 #define SPI_PUSHR 0x34 /* PUSH TX FIFO In Master Mode */ 103 #define PUSHR_CONT (1 << 31) /* Continuous Peripheral CS */ 104 #define PUSHR_EOQ (1 << 27) /* End Of Queue */ 105 #define PUSHR_CTCNT (1 << 26) /* Clear Transfer Counter */ 106 #define PUSHR_PCS_M 0x3f 107 #define PUSHR_PCS_S 16 /* Select PCS signals */ 108 109 #define SPI_PUSHR_SLAVE 0x34 /* PUSH TX FIFO Register In Slave Mode */ 110 #define SPI_POPR 0x38 /* POP RX FIFO Register */ 111 #define SPI_TXFR0 0x3C /* Transmit FIFO Registers */ 112 #define SPI_TXFR1 0x40 113 #define SPI_TXFR2 0x44 114 #define SPI_TXFR3 0x48 115 #define SPI_RXFR0 0x7C /* Receive FIFO Registers */ 116 #define SPI_RXFR1 0x80 117 #define SPI_RXFR2 0x84 118 #define SPI_RXFR3 0x88 119 120 struct spi_softc { 121 struct resource *res[2]; 122 bus_space_tag_t bst; 123 bus_space_handle_t bsh; 124 void *ih; 125 }; 126 127 static struct resource_spec spi_spec[] = { 128 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 129 { SYS_RES_IRQ, 0, RF_ACTIVE }, 130 { -1, 0 } 131 }; 132 133 static int 134 spi_probe(device_t dev) 135 { 136 137 if (!ofw_bus_status_okay(dev)) 138 return (ENXIO); 139 140 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-spi")) 141 return (ENXIO); 142 143 device_set_desc(dev, "Vybrid Family Serial Peripheral Interface"); 144 return (BUS_PROBE_DEFAULT); 145 } 146 147 static int 148 spi_attach(device_t dev) 149 { 150 struct spi_softc *sc; 151 uint32_t reg; 152 153 sc = device_get_softc(dev); 154 155 if (bus_alloc_resources(dev, spi_spec, sc->res)) { 156 device_printf(dev, "could not allocate resources\n"); 157 return (ENXIO); 158 } 159 160 /* Memory interface */ 161 sc->bst = rman_get_bustag(sc->res[0]); 162 sc->bsh = rman_get_bushandle(sc->res[0]); 163 164 reg = READ4(sc, SPI_MCR); 165 reg |= MCR_MSTR; 166 reg &= ~(MCR_CONT_SCKE | MCR_MDIS | MCR_FRZ); 167 reg &= ~(MCR_PCSIS_M << MCR_PCSIS_S); 168 reg |= (MCR_PCSIS_M << MCR_PCSIS_S); /* PCS Active low */ 169 reg |= (MCR_CLR_TXF | MCR_CLR_RXF); 170 WRITE4(sc, SPI_MCR, reg); 171 172 reg = READ4(sc, SPI_RSER); 173 reg |= RSER_EOQF_RE; 174 WRITE4(sc, SPI_RSER, reg); 175 176 reg = READ4(sc, SPI_MCR); 177 reg &= ~MCR_HALT; 178 WRITE4(sc, SPI_MCR, reg); 179 180 reg = READ4(sc, SPI_CTAR0); 181 reg &= ~(CTAR_FMSZ_M << CTAR_FMSZ_S); 182 reg |= (CTAR_FMSZ_8 << CTAR_FMSZ_S); 183 /* 184 * TODO: calculate BR 185 * SCK baud rate = ( fsys / PBR ) * (1 + DBR) / BR 186 * 187 * reg &= ~(CTAR_BR_M << CTAR_BR_S); 188 */ 189 reg &= ~CTAR_CPOL; /* Polarity */ 190 reg |= CTAR_CPHA; 191 /* 192 * Set LSB (Less significant bit first) 193 * must be used for some applications, e.g. some LCDs 194 */ 195 reg |= CTAR_LSBFE; 196 WRITE4(sc, SPI_CTAR0, reg); 197 198 reg = READ4(sc, SPI_CTAR0); 199 reg &= ~(CTAR_PBR_M << CTAR_PBR_S); 200 reg |= (CTAR_PBR_7 << CTAR_PBR_S); 201 WRITE4(sc, SPI_CTAR0, reg); 202 203 device_add_child(dev, "spibus", 0); 204 return (bus_generic_attach(dev)); 205 } 206 207 static int 208 spi_txrx(struct spi_softc *sc, uint8_t *out_buf, 209 uint8_t *in_buf, int bufsz, int cs) 210 { 211 uint32_t reg, wreg; 212 uint32_t txcnt; 213 uint32_t i; 214 215 txcnt = 0; 216 217 for (i = 0; i < bufsz; i++) { 218 txcnt++; 219 wreg = out_buf[i]; 220 wreg |= PUSHR_CONT; 221 wreg |= (cs << PUSHR_PCS_S); 222 if (i == 0) 223 wreg |= PUSHR_CTCNT; 224 if (i == (bufsz - 1) || txcnt == SPI_FIFO_SIZE) 225 wreg |= PUSHR_EOQ; 226 WRITE4(sc, SPI_PUSHR, wreg); 227 228 if (i == (bufsz - 1) || txcnt == SPI_FIFO_SIZE) { 229 txcnt = 0; 230 231 /* Wait last entry in a queue to be transmitted */ 232 while((READ4(sc, SPI_SR) & SR_EOQF) == 0) 233 continue; 234 235 reg = READ4(sc, SPI_SR); 236 reg |= (SR_TCF | SR_EOQF); 237 WRITE4(sc, SPI_SR, reg); 238 } 239 240 /* Wait until RX FIFO is empty */ 241 while((READ4(sc, SPI_SR) & SR_RFDF) == 0) 242 continue; 243 244 in_buf[i] = READ1(sc, SPI_POPR); 245 } 246 247 return (0); 248 } 249 250 static int 251 spi_transfer(device_t dev, device_t child, struct spi_command *cmd) 252 { 253 struct spi_softc *sc; 254 uint32_t cs; 255 256 sc = device_get_softc(dev); 257 258 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, 259 ("%s: TX/RX command sizes should be equal", __func__)); 260 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, 261 ("%s: TX/RX data sizes should be equal", __func__)); 262 263 /* get the proper chip select */ 264 spibus_get_cs(child, &cs); 265 266 /* Command */ 267 spi_txrx(sc, cmd->tx_cmd, cmd->rx_cmd, cmd->tx_cmd_sz, cs); 268 269 /* Data */ 270 spi_txrx(sc, cmd->tx_data, cmd->rx_data, cmd->tx_data_sz, cs); 271 272 return (0); 273 } 274 275 static device_method_t spi_methods[] = { 276 /* Device interface */ 277 DEVMETHOD(device_probe, spi_probe), 278 DEVMETHOD(device_attach, spi_attach), 279 /* SPI interface */ 280 DEVMETHOD(spibus_transfer, spi_transfer), 281 { 0, 0 } 282 }; 283 284 static driver_t spi_driver = { 285 "spi", 286 spi_methods, 287 sizeof(struct spi_softc), 288 }; 289 290 static devclass_t spi_devclass; 291 292 DRIVER_MODULE(spi, simplebus, spi_driver, spi_devclass, 0, 0); 293