1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Vybrid Family Enhanced Direct Memory Access Controller (eDMA) 29 * Chapter 21, Vybrid Reference Manual, Rev. 5, 07/2013 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/malloc.h> 41 #include <sys/rman.h> 42 #include <sys/timeet.h> 43 #include <sys/timetc.h> 44 #include <sys/watchdog.h> 45 46 #include <dev/ofw/openfirm.h> 47 #include <dev/ofw/ofw_bus.h> 48 #include <dev/ofw/ofw_bus_subr.h> 49 50 #include <machine/bus.h> 51 #include <machine/cpu.h> 52 #include <machine/intr.h> 53 54 #include <arm/freescale/vybrid/vf_edma.h> 55 #include <arm/freescale/vybrid/vf_dmamux.h> 56 #include <arm/freescale/vybrid/vf_common.h> 57 58 struct edma_channel { 59 uint32_t enabled; 60 uint32_t mux_num; 61 uint32_t mux_src; 62 uint32_t mux_chn; 63 uint32_t (*ih) (void *, int); 64 void *ih_user; 65 }; 66 67 static struct edma_channel edma_map[EDMA_NUM_CHANNELS]; 68 69 static struct resource_spec edma_spec[] = { 70 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 71 { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* TCD */ 72 { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Transfer complete */ 73 { SYS_RES_IRQ, 1, RF_ACTIVE }, /* Error Interrupt */ 74 { -1, 0 } 75 }; 76 77 static int 78 edma_probe(device_t dev) 79 { 80 81 if (!ofw_bus_status_okay(dev)) 82 return (ENXIO); 83 84 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-edma")) 85 return (ENXIO); 86 87 device_set_desc(dev, "Vybrid Family eDMA Controller"); 88 return (BUS_PROBE_DEFAULT); 89 } 90 91 static void 92 edma_transfer_complete_intr(void *arg) 93 { 94 struct edma_channel *ch; 95 struct edma_softc *sc; 96 int interrupts; 97 int i; 98 99 sc = arg; 100 101 interrupts = READ4(sc, DMA_INT); 102 WRITE1(sc, DMA_CINT, CINT_CAIR); 103 104 for (i = 0; i < EDMA_NUM_CHANNELS; i++) { 105 if (interrupts & (0x1 << i)) { 106 ch = &edma_map[i]; 107 if (ch->enabled == 1) { 108 if (ch->ih != NULL) { 109 ch->ih(ch->ih_user, i); 110 } 111 } 112 } 113 } 114 } 115 116 static void 117 edma_err_intr(void *arg) 118 { 119 struct edma_softc *sc; 120 int reg; 121 122 sc = arg; 123 124 reg = READ4(sc, DMA_ERR); 125 126 #if 0 127 device_printf(sc->dev, "DMA_ERR 0x%08x, ES 0x%08x\n", 128 reg, READ4(sc, DMA_ES)); 129 #endif 130 131 WRITE1(sc, DMA_CERR, CERR_CAEI); 132 } 133 134 static int 135 channel_free(struct edma_softc *sc, int chnum) 136 { 137 struct edma_channel *ch; 138 139 ch = &edma_map[chnum]; 140 ch->enabled = 0; 141 142 dmamux_configure(ch->mux_num, ch->mux_src, ch->mux_chn, 0); 143 144 return (0); 145 } 146 147 static int 148 channel_configure(struct edma_softc *sc, int mux_grp, int mux_src) 149 { 150 struct edma_channel *ch; 151 int channel_first; 152 int mux_num; 153 int chnum; 154 int i; 155 156 if ((sc->device_id == 0 && mux_grp == 1) || \ 157 (sc->device_id == 1 && mux_grp == 0)) { 158 channel_first = NCHAN_PER_MUX; 159 mux_num = (sc->device_id * 2) + 1; 160 } else { 161 channel_first = 0; 162 mux_num = sc->device_id * 2; 163 } 164 165 /* Take first unused eDMA channel */ 166 ch = NULL; 167 for (i = channel_first; i < (channel_first + NCHAN_PER_MUX); i++) { 168 ch = &edma_map[i]; 169 if (ch->enabled == 0) { 170 break; 171 } 172 ch = NULL; 173 } 174 175 if (ch == NULL) { 176 /* Can't find free channel */ 177 return (-1); 178 } 179 180 chnum = i; 181 182 ch->enabled = 1; 183 ch->mux_num = mux_num; 184 ch->mux_src = mux_src; 185 ch->mux_chn = (chnum - channel_first); /* 0 to 15 */ 186 187 dmamux_configure(ch->mux_num, ch->mux_src, ch->mux_chn, 1); 188 189 return (chnum); 190 } 191 192 static int 193 dma_stop(struct edma_softc *sc, int chnum) 194 { 195 int reg; 196 197 reg = READ4(sc, DMA_ERQ); 198 reg &= ~(0x1 << chnum); 199 WRITE4(sc, DMA_ERQ, reg); 200 201 return (0); 202 } 203 204 static int 205 dma_setup(struct edma_softc *sc, struct tcd_conf *tcd) 206 { 207 struct edma_channel *ch; 208 int chnum; 209 int reg; 210 211 chnum = tcd->channel; 212 213 ch = &edma_map[chnum]; 214 ch->ih = tcd->ih; 215 ch->ih_user = tcd->ih_user; 216 217 TCD_WRITE4(sc, DMA_TCDn_SADDR(chnum), tcd->saddr); 218 TCD_WRITE4(sc, DMA_TCDn_DADDR(chnum), tcd->daddr); 219 220 reg = (tcd->smod << TCD_ATTR_SMOD_SHIFT); 221 reg |= (tcd->dmod << TCD_ATTR_DMOD_SHIFT); 222 reg |= (tcd->ssize << TCD_ATTR_SSIZE_SHIFT); 223 reg |= (tcd->dsize << TCD_ATTR_DSIZE_SHIFT); 224 TCD_WRITE2(sc, DMA_TCDn_ATTR(chnum), reg); 225 226 TCD_WRITE2(sc, DMA_TCDn_SOFF(chnum), tcd->soff); 227 TCD_WRITE2(sc, DMA_TCDn_DOFF(chnum), tcd->doff); 228 TCD_WRITE4(sc, DMA_TCDn_SLAST(chnum), tcd->slast); 229 TCD_WRITE4(sc, DMA_TCDn_DLASTSGA(chnum), tcd->dlast_sga); 230 TCD_WRITE4(sc, DMA_TCDn_NBYTES_MLOFFYES(chnum), tcd->nbytes); 231 232 reg = tcd->nmajor; /* Current Major Iteration Count */ 233 TCD_WRITE2(sc, DMA_TCDn_CITER_ELINKNO(chnum), reg); 234 TCD_WRITE2(sc, DMA_TCDn_BITER_ELINKNO(chnum), reg); 235 236 reg = (TCD_CSR_INTMAJOR); 237 if(tcd->majorelink == 1) { 238 reg |= TCD_CSR_MAJORELINK; 239 reg |= (tcd->majorelinkch << TCD_CSR_MAJORELINKCH_SHIFT); 240 } 241 TCD_WRITE2(sc, DMA_TCDn_CSR(chnum), reg); 242 243 /* Enable requests */ 244 reg = READ4(sc, DMA_ERQ); 245 reg |= (0x1 << chnum); 246 WRITE4(sc, DMA_ERQ, reg); 247 248 /* Enable error interrupts */ 249 reg = READ4(sc, DMA_EEI); 250 reg |= (0x1 << chnum); 251 WRITE4(sc, DMA_EEI, reg); 252 253 return (0); 254 } 255 256 static int 257 dma_request(struct edma_softc *sc, int chnum) 258 { 259 int reg; 260 261 /* Start */ 262 reg = TCD_READ2(sc, DMA_TCDn_CSR(chnum)); 263 reg |= TCD_CSR_START; 264 TCD_WRITE2(sc, DMA_TCDn_CSR(chnum), reg); 265 266 return (0); 267 } 268 269 static int 270 edma_attach(device_t dev) 271 { 272 struct edma_softc *sc; 273 phandle_t node; 274 int dts_value; 275 int len; 276 277 sc = device_get_softc(dev); 278 sc->dev = dev; 279 280 if ((node = ofw_bus_get_node(sc->dev)) == -1) 281 return (ENXIO); 282 283 if ((len = OF_getproplen(node, "device-id")) <= 0) 284 return (ENXIO); 285 286 OF_getencprop(node, "device-id", &dts_value, len); 287 sc->device_id = dts_value; 288 289 sc->dma_stop = dma_stop; 290 sc->dma_setup = dma_setup; 291 sc->dma_request = dma_request; 292 sc->channel_configure = channel_configure; 293 sc->channel_free = channel_free; 294 295 if (bus_alloc_resources(dev, edma_spec, sc->res)) { 296 device_printf(dev, "could not allocate resources\n"); 297 return (ENXIO); 298 } 299 300 /* Memory interface */ 301 sc->bst = rman_get_bustag(sc->res[0]); 302 sc->bsh = rman_get_bushandle(sc->res[0]); 303 sc->bst_tcd = rman_get_bustag(sc->res[1]); 304 sc->bsh_tcd = rman_get_bushandle(sc->res[1]); 305 306 /* Setup interrupt handlers */ 307 if (bus_setup_intr(dev, sc->res[2], INTR_TYPE_BIO | INTR_MPSAFE, 308 NULL, edma_transfer_complete_intr, sc, &sc->tc_ih)) { 309 device_printf(dev, "Unable to alloc DMA intr resource.\n"); 310 return (ENXIO); 311 } 312 313 if (bus_setup_intr(dev, sc->res[3], INTR_TYPE_BIO | INTR_MPSAFE, 314 NULL, edma_err_intr, sc, &sc->err_ih)) { 315 device_printf(dev, "Unable to alloc DMA Err intr resource.\n"); 316 return (ENXIO); 317 } 318 319 return (0); 320 } 321 322 static device_method_t edma_methods[] = { 323 DEVMETHOD(device_probe, edma_probe), 324 DEVMETHOD(device_attach, edma_attach), 325 { 0, 0 } 326 }; 327 328 static driver_t edma_driver = { 329 "edma", 330 edma_methods, 331 sizeof(struct edma_softc), 332 }; 333 334 static devclass_t edma_devclass; 335 336 DRIVER_MODULE(edma, simplebus, edma_driver, edma_devclass, 0, 0); 337