1 /*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * Vybrid Family Display Control Unit (DCU4) 29 * Chapter 55, Vybrid Reference Manual, Rev. 5, 07/2013 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/malloc.h> 41 #include <sys/rman.h> 42 #include <sys/timeet.h> 43 #include <sys/timetc.h> 44 #include <sys/watchdog.h> 45 #include <sys/fbio.h> 46 #include <sys/consio.h> 47 #include <sys/eventhandler.h> 48 49 #include <dev/fdt/fdt_common.h> 50 #include <dev/ofw/openfirm.h> 51 #include <dev/ofw/ofw_bus.h> 52 #include <dev/ofw/ofw_bus_subr.h> 53 54 #include <dev/vt/vt.h> 55 #include <dev/vt/colors/vt_termcolors.h> 56 57 #include <machine/bus.h> 58 #include <machine/fdt.h> 59 #include <machine/cpu.h> 60 #include <machine/intr.h> 61 62 #include "fb_if.h" 63 64 #include <arm/freescale/vybrid/vf_common.h> 65 66 #define DCU_CTRLDESCCURSOR1 0x000 /* Control Descriptor Cursor 1 */ 67 #define DCU_CTRLDESCCURSOR2 0x004 /* Control Descriptor Cursor 2 */ 68 #define DCU_CTRLDESCCURSOR3 0x008 /* Control Descriptor Cursor 3 */ 69 #define DCU_CTRLDESCCURSOR4 0x00C /* Control Descriptor Cursor 4 */ 70 #define DCU_DCU_MODE 0x010 /* DCU4 Mode */ 71 #define DCU_MODE_M 0x3 72 #define DCU_MODE_S 0 73 #define DCU_MODE_NORMAL 0x1 74 #define DCU_MODE_TEST 0x2 75 #define DCU_MODE_COLBAR 0x3 76 #define RASTER_EN (1 << 14) /* Raster scan of pixel data */ 77 #define DCU_BGND 0x014 /* Background */ 78 #define DCU_DISP_SIZE 0x018 /* Display Size */ 79 #define DELTA_M 0x7ff 80 #define DELTA_Y_S 16 81 #define DELTA_X_S 0 82 #define DCU_HSYN_PARA 0x01C /* Horizontal Sync Parameter */ 83 #define BP_H_SHIFT 22 84 #define PW_H_SHIFT 11 85 #define FP_H_SHIFT 0 86 #define DCU_VSYN_PARA 0x020 /* Vertical Sync Parameter */ 87 #define BP_V_SHIFT 22 88 #define PW_V_SHIFT 11 89 #define FP_V_SHIFT 0 90 #define DCU_SYNPOL 0x024 /* Synchronize Polarity */ 91 #define INV_HS (1 << 0) 92 #define INV_VS (1 << 1) 93 #define DCU_THRESHOLD 0x028 /* Threshold */ 94 #define LS_BF_VS_SHIFT 16 95 #define OUT_BUF_HIGH_SHIFT 8 96 #define OUT_BUF_LOW_SHIFT 0 97 #define DCU_INT_STATUS 0x02C /* Interrupt Status */ 98 #define DCU_INT_MASK 0x030 /* Interrupt Mask */ 99 #define DCU_COLBAR_1 0x034 /* COLBAR_1 */ 100 #define DCU_COLBAR_2 0x038 /* COLBAR_2 */ 101 #define DCU_COLBAR_3 0x03C /* COLBAR_3 */ 102 #define DCU_COLBAR_4 0x040 /* COLBAR_4 */ 103 #define DCU_COLBAR_5 0x044 /* COLBAR_5 */ 104 #define DCU_COLBAR_6 0x048 /* COLBAR_6 */ 105 #define DCU_COLBAR_7 0x04C /* COLBAR_7 */ 106 #define DCU_COLBAR_8 0x050 /* COLBAR_8 */ 107 #define DCU_DIV_RATIO 0x054 /* Divide Ratio */ 108 #define DCU_SIGN_CALC_1 0x058 /* Sign Calculation 1 */ 109 #define DCU_SIGN_CALC_2 0x05C /* Sign Calculation 2 */ 110 #define DCU_CRC_VAL 0x060 /* CRC Value */ 111 #define DCU_PDI_STATUS 0x064 /* PDI Status */ 112 #define DCU_PDI_STA_MSK 0x068 /* PDI Status Mask */ 113 #define DCU_PARR_ERR_STATUS1 0x06C /* Parameter Error Status 1 */ 114 #define DCU_PARR_ERR_STATUS2 0x070 /* Parameter Error Status 2 */ 115 #define DCU_PARR_ERR_STATUS3 0x07C /* Parameter Error Status 3 */ 116 #define DCU_MASK_PARR_ERR_ST1 0x080 /* Mask Parameter Error Status 1 */ 117 #define DCU_MASK_PARR_ERR_ST2 0x084 /* Mask Parameter Error Status 2 */ 118 #define DCU_MASK_PARR_ERR_ST3 0x090 /* Mask Parameter Error Status 3 */ 119 #define DCU_THRESHOLD_INP_BUF_1 0x094 /* Threshold Input 1 */ 120 #define DCU_THRESHOLD_INP_BUF_2 0x098 /* Threshold Input 2 */ 121 #define DCU_THRESHOLD_INP_BUF_3 0x09C /* Threshold Input 3 */ 122 #define DCU_LUMA_COMP 0x0A0 /* LUMA Component */ 123 #define DCU_CHROMA_RED 0x0A4 /* Red Chroma Components */ 124 #define DCU_CHROMA_GREEN 0x0A8 /* Green Chroma Components */ 125 #define DCU_CHROMA_BLUE 0x0AC /* Blue Chroma Components */ 126 #define DCU_CRC_POS 0x0B0 /* CRC Position */ 127 #define DCU_LYR_INTPOL_EN 0x0B4 /* Layer Interpolation Enable */ 128 #define DCU_LYR_LUMA_COMP 0x0B8 /* Layer Luminance Component */ 129 #define DCU_LYR_CHRM_RED 0x0BC /* Layer Chroma Red */ 130 #define DCU_LYR_CHRM_GRN 0x0C0 /* Layer Chroma Green */ 131 #define DCU_LYR_CHRM_BLUE 0x0C4 /* Layer Chroma Blue */ 132 #define DCU_COMP_IMSIZE 0x0C8 /* Compression Image Size */ 133 #define DCU_UPDATE_MODE 0x0CC /* Update Mode */ 134 #define READREG (1 << 30) 135 #define MODE (1 << 31) 136 #define DCU_UNDERRUN 0x0D0 /* Underrun */ 137 #define DCU_GLBL_PROTECT 0x100 /* Global Protection */ 138 #define DCU_SFT_LCK_BIT_L0 0x104 /* Soft Lock Bit Layer 0 */ 139 #define DCU_SFT_LCK_BIT_L1 0x108 /* Soft Lock Bit Layer 1 */ 140 #define DCU_SFT_LCK_DISP_SIZE 0x10C /* Soft Lock Display Size */ 141 #define DCU_SFT_LCK_HS_VS_PARA 0x110 /* Soft Lock Hsync/Vsync Parameter */ 142 #define DCU_SFT_LCK_POL 0x114 /* Soft Lock POL */ 143 #define DCU_SFT_LCK_L0_TRANSP 0x118 /* Soft Lock L0 Transparency */ 144 #define DCU_SFT_LCK_L1_TRANSP 0x11C /* Soft Lock L1 Transparency */ 145 146 /* Control Descriptor */ 147 #define DCU_CTRLDESCL(n, m) 0x200 + (0x40 * n) + 0x4 * (m - 1) 148 #define DCU_CTRLDESCLn_1(n) DCU_CTRLDESCL(n, 1) 149 #define DCU_CTRLDESCLn_2(n) DCU_CTRLDESCL(n, 2) 150 #define DCU_CTRLDESCLn_3(n) DCU_CTRLDESCL(n, 3) 151 #define TRANS_SHIFT 20 152 #define DCU_CTRLDESCLn_4(n) DCU_CTRLDESCL(n, 4) 153 #define BPP_MASK 0xf /* Bit per pixel Mask */ 154 #define BPP_SHIFT 16 /* Bit per pixel Shift */ 155 #define BPP24 0x5 156 #define EN_LAYER (1 << 31) /* Enable the layer */ 157 #define DCU_CTRLDESCLn_5(n) DCU_CTRLDESCL(n, 5) 158 #define DCU_CTRLDESCLn_6(n) DCU_CTRLDESCL(n, 6) 159 #define DCU_CTRLDESCLn_7(n) DCU_CTRLDESCL(n, 7) 160 #define DCU_CTRLDESCLn_8(n) DCU_CTRLDESCL(n, 8) 161 #define DCU_CTRLDESCLn_9(n) DCU_CTRLDESCL(n, 9) 162 163 #define DISPLAY_WIDTH 480 164 #define DISPLAY_HEIGHT 272 165 166 struct dcu_softc { 167 struct resource *res[2]; 168 bus_space_tag_t bst; 169 bus_space_handle_t bsh; 170 void *ih; 171 device_t dev; 172 device_t sc_fbd; /* fbd child */ 173 struct fb_info sc_info; 174 }; 175 176 static struct resource_spec dcu_spec[] = { 177 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 178 { SYS_RES_IRQ, 0, RF_ACTIVE }, 179 { -1, 0 } 180 }; 181 182 static int 183 dcu_probe(device_t dev) 184 { 185 186 if (!ofw_bus_status_okay(dev)) 187 return (ENXIO); 188 189 if (!ofw_bus_is_compatible(dev, "fsl,mvf600-dcu4")) 190 return (ENXIO); 191 192 device_set_desc(dev, "Vybrid Family Display Control Unit (DCU4)"); 193 return (BUS_PROBE_DEFAULT); 194 } 195 196 static void 197 dcu_intr(void *arg) 198 { 199 struct dcu_softc *sc; 200 int reg; 201 202 sc = arg; 203 204 /* Ack interrupts */ 205 reg = READ4(sc, DCU_INT_STATUS); 206 WRITE4(sc, DCU_INT_STATUS, reg); 207 208 /* TODO interrupt handler */ 209 } 210 211 static int 212 dcu_init(struct dcu_softc *sc) 213 { 214 int reg; 215 216 /* Configure DCU */ 217 reg = ((sc->sc_info.fb_height) << DELTA_Y_S); 218 reg |= (sc->sc_info.fb_width / 16); 219 WRITE4(sc, DCU_DISP_SIZE, reg); 220 221 /* TODO: export panel info to FDT */ 222 223 reg = (2 << BP_H_SHIFT); 224 reg |= (41 << PW_H_SHIFT); 225 reg |= (2 << FP_H_SHIFT); 226 WRITE4(sc, DCU_HSYN_PARA, reg); 227 228 reg = (2 << BP_V_SHIFT); 229 reg |= (10 << PW_V_SHIFT); 230 reg |= (2 << FP_V_SHIFT); 231 WRITE4(sc, DCU_VSYN_PARA, reg); 232 233 WRITE4(sc, DCU_BGND, 0); 234 WRITE4(sc, DCU_DIV_RATIO, 30); 235 236 reg = (INV_VS | INV_HS); 237 WRITE4(sc, DCU_SYNPOL, reg); 238 239 reg = (0x3 << LS_BF_VS_SHIFT); 240 reg |= (0x78 << OUT_BUF_HIGH_SHIFT); 241 reg |= (0 << OUT_BUF_LOW_SHIFT); 242 WRITE4(sc, DCU_THRESHOLD, reg); 243 244 /* Mask all the interrupts */ 245 WRITE4(sc, DCU_INT_MASK, 0xffffffff); 246 247 /* Setup first layer */ 248 reg = (sc->sc_info.fb_width | (sc->sc_info.fb_height << 16)); 249 WRITE4(sc, DCU_CTRLDESCLn_1(0), reg); 250 WRITE4(sc, DCU_CTRLDESCLn_2(0), 0x0); 251 WRITE4(sc, DCU_CTRLDESCLn_3(0), sc->sc_info.fb_pbase); 252 reg = (BPP24 << BPP_SHIFT); 253 reg |= EN_LAYER; 254 reg |= (0xFF << TRANS_SHIFT); /* completely opaque */ 255 WRITE4(sc, DCU_CTRLDESCLn_4(0), reg); 256 WRITE4(sc, DCU_CTRLDESCLn_5(0), 0xffffff); 257 WRITE4(sc, DCU_CTRLDESCLn_6(0), 0x0); 258 WRITE4(sc, DCU_CTRLDESCLn_7(0), 0x0); 259 WRITE4(sc, DCU_CTRLDESCLn_8(0), 0x0); 260 WRITE4(sc, DCU_CTRLDESCLn_9(0), 0x0); 261 262 /* Enable DCU in normal mode */ 263 reg = READ4(sc, DCU_DCU_MODE); 264 reg &= ~(DCU_MODE_M << DCU_MODE_S); 265 reg |= (DCU_MODE_NORMAL << DCU_MODE_S); 266 reg |= (RASTER_EN); 267 WRITE4(sc, DCU_DCU_MODE, reg); 268 WRITE4(sc, DCU_UPDATE_MODE, READREG); 269 270 return (0); 271 } 272 273 static int 274 dcu_attach(device_t dev) 275 { 276 struct dcu_softc *sc; 277 int err; 278 279 sc = device_get_softc(dev); 280 281 if (bus_alloc_resources(dev, dcu_spec, sc->res)) { 282 device_printf(dev, "could not allocate resources\n"); 283 return (ENXIO); 284 } 285 286 /* Memory interface */ 287 sc->bst = rman_get_bustag(sc->res[0]); 288 sc->bsh = rman_get_bushandle(sc->res[0]); 289 290 /* Setup interrupt handler */ 291 err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_BIO | INTR_MPSAFE, 292 NULL, dcu_intr, sc, &sc->ih); 293 if (err) { 294 device_printf(dev, "Unable to alloc interrupt resource.\n"); 295 return (ENXIO); 296 } 297 298 /* Bypass timing control (used for raw lcd panels) */ 299 tcon_bypass(); 300 301 sc->sc_info.fb_width = DISPLAY_WIDTH; 302 sc->sc_info.fb_height = DISPLAY_HEIGHT; 303 sc->sc_info.fb_stride = sc->sc_info.fb_width * 3; 304 sc->sc_info.fb_bpp = sc->sc_info.fb_depth = 24; 305 sc->sc_info.fb_size = sc->sc_info.fb_height * sc->sc_info.fb_stride; 306 sc->sc_info.fb_vbase = (intptr_t)contigmalloc(sc->sc_info.fb_size, 307 M_DEVBUF, M_ZERO, 0, ~0, PAGE_SIZE, 0); 308 sc->sc_info.fb_pbase = (intptr_t)vtophys(sc->sc_info.fb_vbase); 309 310 #if 0 311 printf("%dx%d [%d]\n", sc->sc_info.fb_width, sc->sc_info.fb_height, 312 sc->sc_info.fb_stride); 313 printf("pbase == 0x%08x\n", sc->sc_info.fb_pbase); 314 #endif 315 316 memset((int8_t *)sc->sc_info.fb_vbase, 0x0, sc->sc_info.fb_size); 317 318 dcu_init(sc); 319 320 sc->sc_info.fb_name = device_get_nameunit(dev); 321 322 /* Ask newbus to attach framebuffer device to me. */ 323 sc->sc_fbd = device_add_child(dev, "fbd", device_get_unit(dev)); 324 if (sc->sc_fbd == NULL) 325 device_printf(dev, "Can't attach fbd device\n"); 326 327 if (device_probe_and_attach(sc->sc_fbd) != 0) { 328 device_printf(sc->dev, "Failed to attach fbd device\n"); 329 } 330 331 return (0); 332 } 333 334 static struct fb_info * 335 dcu4_fb_getinfo(device_t dev) 336 { 337 struct dcu_softc *sc = device_get_softc(dev); 338 339 return (&sc->sc_info); 340 } 341 342 static device_method_t dcu_methods[] = { 343 DEVMETHOD(device_probe, dcu_probe), 344 DEVMETHOD(device_attach, dcu_attach), 345 346 /* Framebuffer service methods */ 347 DEVMETHOD(fb_getinfo, dcu4_fb_getinfo), 348 { 0, 0 } 349 }; 350 351 static driver_t dcu_driver = { 352 "fb", 353 dcu_methods, 354 sizeof(struct dcu_softc), 355 }; 356 357 static devclass_t dcu_devclass; 358 359 DRIVER_MODULE(fb, simplebus, dcu_driver, dcu_devclass, 0, 0); 360